JPH04219082A - Image pickup device and counter circuit used for the same - Google Patents

Abstract

PURPOSE:To offer an image pickup device with a little fixed pattern noise and the counter circuit used for the device. CONSTITUTION:The counter circuit in which a gray code where the number of simultaneous change of output signals 60-65 are always one is generated by plural counting stages 21-26, plural decoding means 27-36 and the number of simultaneous change adjusting means 37-42 and simultaneously where the number of simultaneous change of the output signals of the internal logical gates 27-42 is constant, as well is constituted. By generating the clock signal of a charge coupled device using this counter circuit, the influence of the fixed pattern noise is reduced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an imaging device such as a video camera using a solid-state imaging device and a counter circuit used therein.

0002

[Prior Art] A solid-state image sensor is a charge-coupled device (hereinafter referred to as C
The solid-state image sensor drive device plays the most important role in determining the performance of the video camera and other imaging devices. occupies .

FIG. 6 shows the configuration of a general video camera. In FIG. 6, light that passes through a lens 1 and reaches a CCD 2 is converted into an electrical signal by the CCD 2. In FIG. The output signal of the CCD 2 is supplied to a signal processing circuit 3, where it is converted into a video signal and then supplied to a subsequent video signal circuit (not shown).

The CCD 2 and signal processing circuit 3 are driven by a clock signal 12 and a synchronization signal 13 from a drive signal generation circuit 4, respectively. The drive signal generation circuit 4 includes a crystal oscillator 5, a clock generator 6, and a synchronization signal generator 7.

As shown in FIG. 7, the clock generator 6 includes an oscillation circuit 8 that generates a reference clock signal together with the crystal oscillator 5, and a binary code counter that divides the frequency of the output signal of the oscillation circuit 8. 9, a decoder 10 that decodes the output of the binary code counter 9, and a latch circuit 11 that latches the output of the decoder 10. A clock signal 12 output from the latch circuit 11 is used as a clock for charge transfer. The signal is supplied to the CCD 2 as a signal.

On the other hand, the synchronizing signal generator 7 basically includes a crystal oscillator, an oscillation circuit, and the like as the clock generator 6.
It consists of a binary code counter, a decoder, and a latch circuit. Then, the signal 13 output from the latch circuit is transmitted to the signal processing circuit 3 as shown by the broken line in FIG.
It is used as a synchronizing signal for signal processing, such as a synchronizing signal for a television signal, a clamp pulse, or a blanking pulse.

Conventionally, the clock generator 6 and the synchronizing signal generator 7 were constructed of separate semiconductor elements, but as can be seen from FIG. 7, these elements contain a common circuit. There is a demand for integrating these elements into one chip.

FIG. 6 shows the connection relationship when the clock generator 6 and the synchronizing signal generator 7 are integrated into one chip. In this case, the output signal 1 of the oscillation circuit 8 in the clock generator 6
4 is fed to a binary code counter in the synchronization signal generator 7. That is, the binary code counter included in the synchronization signal generator 7 continues to perform a counting operation in response to the output of the oscillation circuit 8 in the clock generator 6. A part of the output signal of the latch circuit included in the synchronization signal generator 7 is supplied as a control signal 15 to the binary code counter 9 in the clock generator 6, and the counting operation of the binary code counter 9 is stopped during the scanning period. , the counting operation is performed only during the retrace period.

As a result, the signals output from each latch circuit in the clock generator 6 and the synchronization signal generator 7 are the clock signal 12 for charge transfer and the synchronization signal 1 for signal processing.
3 is supplied to the CCD 2 and the signal processing circuit 3, respectively.

0010

However, in this way, the clock generator 6 and the synchronization signal generator 7 are integrated into one chip, and in particular, the counter for counting one horizontal period in the synchronization signal generator 7 is If it is configured with a binary code counter, jitter will be imparted to the high-speed pulses (for example, horizontal transfer pulses) supplied to the CCD 2 at timings when the number of simultaneous changes in the bits of the counter is large. As a result, there is a problem in that vertical striped fixed pattern noise appears on the finally obtained screen.

[0011] This problem will be explained in more detail. FIG. 8 shows input and output waveforms of the binary code counter. As is well known, the binary code counter shown in Fig. 8(a)
When the clock signal shown in is supplied, this clock signal is converted into 1/2, 1/4, 1/4, etc. by the binary code counter.
The frequency is sequentially divided into 1/8, etc., and the output signal shown in FIG. 8(b) is obtained.

If we pay attention to the number of bit changes in FIG. 8(b), we can see that five bits change simultaneously at timings t1 and t3. Furthermore, at timing t2, four bits change simultaneously.

When the clock generator 6 and the synchronization signal generator 7 are configured as a one-chip circuit, the timings t1, t2, and t2 when the number of output bit changes of the binary code counter is large
At t3, a trigger-like power supply current larger than the steady power supply current flows through the circuit. As a result, fixed pattern noise occurs in the video signals output from the CCD 2 and the signal processing circuit 3, and this appears as vertical stripes on the screen.

Furthermore, there is a problem in that the trigger-like power supply current also generates unnecessary radiation, which adversely affects the operation of peripheral circuits.

[0015] A similar problem also occurs when the counter of the clock generator 6 is constructed of a binary code counter.

In order to solve this problem, the present applicant has proposed an imaging device as shown in FIG. 9 (Japanese Patent Application No. 1-305402).

In FIG. 9, circuits having substantially the same functions as those in FIG. 7 are given the same reference numerals. As is clear from FIG. 9, here, the counters of the clock generator 6 and the synchronization signal generator 7 are configured with a Gray code counter 16. Note that the Gray code counter means a counter whose output signal always changes by 1 bit.

FIG. 10 shows input and output waveforms of the Gray code counter 16. When the clock signal (output signal of the oscillation circuit 8) shown in FIG. 10(a) is supplied to the Gray code counter 16, output signals as shown in FIG. 10(b) are generated from each output terminal of the Gray code counter 16. be done. As is clear from FIG. 10(b), in the Gray code counter 16, at every bit change timing,
Only one bit always changes.

Therefore, by decoding the output signal of the gray code counter 16 with the decoder 10 and latching the decoded output with the latch circuit 11, the CCD 2
A clock signal 12 for charge transfer can be supplied to the signal processing circuit 3, and a synchronization signal 13 for signal processing can be supplied to the signal processing circuit 3.

Note that when a Gray code counter is used, it is necessary to slightly change the specific configurations of the decoder 10 and latch circuit 11 compared to when a binary code counter is used, but this itself is extremely easy. ,
By changing the configurations of the decoder 10 and latch circuit 11 so as to obtain the necessary clock signal 12 and synchronization signal 13, the CCD 2 and signal processing circuit 3 can be driven in exactly the same manner as before.

As described above, by using the Gray code counter 16 as a counter, the number of simultaneous changes in the output of the counter can always be 1 bit. For this reason, CCD
2 or the fluctuation of the power supply current during driving of the signal processing circuit 3 can be suppressed, and as a result, it is possible to prevent fixed pattern noise of vertical stripes from appearing in a part of the finally obtained screen. Furthermore, the influence of unnecessary radiation on peripheral circuits can also be reduced.

The present invention provides an imaging device that can further reduce the influence of fixed pattern noise caused by a counter.

The present invention also provides an improved counter circuit that can be used as such a Gray code counter.

[0024]

SUMMARY OF THE INVENTION The imaging apparatus of the present invention is designed to generate fixed pattern noise outside the video signal frequency band due to changes in the output signal of each counting stage of a counter.

The counter circuit of the present invention generates a gray code in which the output signal of each counting stage always changes by only one bit, and also ensures that the number of simultaneous changes in the output signal of the internal logic gate is always constant. This is what I did.

[0026]

[Operation] Since the imaging device of the present invention uses a Gray code counter, fluctuations in the power supply voltage due to simultaneous changes in the output signals of the counter can be alleviated, and generation of fixed pattern noise of vertical stripes on the screen can be suppressed. Not only can you
Even if fixed pattern noise occurs, it can be generated outside the video signal band, so the noise component can be removed by a filter connected after the signal processing circuit. Therefore, the influence of fixed pattern noise on the video signal can be sufficiently reduced.

Furthermore, according to the counter circuit of the present invention,
Not only can a Gray code counter in which the number of simultaneous changes in the output signal of the counting stage is always 1, but also the number of simultaneous changes in the output signal of the internal logic gates always be constant. Therefore, if this counter circuit is used as a CCD driving device, high-quality images with less fixed pattern noise can be obtained.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a first embodiment of the present invention, and shows a counter circuit that can be used as the Gray code counter 16 shown in FIG. FIG. 2 shows the timing chart.

Before explaining the configuration and operation of the counter circuit shown in FIG. 1, the characteristics of the Gray code will first be explained with reference to the timing chart shown in FIG. 2 in order to facilitate understanding.

In FIG. 2, paying attention to bit changes in each counting stage, at the timing when a specific bit (for example, 64 in FIG. 4) changes from low level to high level (or from high level to low level), bit(
Only bit 63) in Figure 4 is high level, and the previous bit (63) is high level.
62, 61, 60) in FIG. 4 are all at low level.

The counter circuit shown in FIG. 1 realizes such bit changes. In FIG. 1, a clock signal input terminal 17 is supplied with a clock signal from, for example, the oscillation circuit 8 of FIG. This clock signal is
It is supplied to the clock terminal CK of all JK flip-flops 21-26.

On the other hand, all JK flip-flops 2
The J terminals and K terminals of the JK flip-flops 21 of the first stage are connected to the power supply terminal 18. The Q output terminal of the JK flip-flop 21 at the first stage is connected to the J terminal and the K terminal of the JK flip-flop 22 at the next stage. The NQ output terminal of the first-stage JK flip-flop 21 is connected to one input terminal of a logic gate 27 for logic decoding. The other input terminal of the logic gate 27 is connected to the second stage J.
-The Q output terminal of the K flip-flop 22 is connected. The output terminal of the logic gate 27 is the third stage J-
It is connected to the J terminal and K terminal of the K flip-flop 23.

[0033] Similarly, J from the 3rd stage to the 6th stage
- Between the K flip-flops 23, 24, 25, 26,
Logic gates 28-36 for logic decoding are connected as shown.

[0034] Also, the Q of a given JK flip-flop is
Logic gates 37 to 42 are connected to the output terminal and the NQ output terminal, respectively, as shown, for adjusting the number of simultaneous bit changes so that a uniform number of simultaneous changes is always obtained.

The above logic gates 27-36 and 37-
In addition to 42, there is also a logic gate 4 for adjusting the load capacitance.
3 to 59 are connected as shown in the figure.

Note that the terminal 20 is a power supply terminal or a high-level fixed potential. The output terminals 60 to 65 of the counter circuit are connected to the JK flip-flops 21 to 65, respectively.
It is connected to the Q output terminal of 26.

FIG. 2 shows voltage waveforms at various parts in FIG. 1, and the waveform numbers are indicated by the reference numbers of the corresponding parts in FIG. That is, 17 in FIG. 2 is the clock signal waveform input to the clock signal input terminal 17, 60 to 65 are the output signal waveforms of the output terminals 60 to 65, and 27 to 36 are the output waveforms of the logic gates 27 to 36 for logic decoding. , 37-42
are the output waveforms of the logic gates 37 to 42 for adjusting the number of simultaneous changes.

Note that 66 in FIG. 2 is a graph representing the number of simultaneous changes in the outputs of each logic gate.

Next, the operation of FIG. 1 will be explained with reference to FIG. When a clock signal is supplied to the clock signal input terminal 17, the JK flip-flop 21 at the first stage inverts the Q output at the falling edge of the clock signal. Therefore, for the clock signal waveform 17 in FIG.
The Q output waveform of the flip-flop 21 is 60 (21
)become that way.

Next, the first stage JK flip-flop 21
The Q output of is the J of the second stage J-K flip-flop 22.
Supplied to terminal and K terminal. Therefore, the second stage J-
The Q output of the K flip-flop 22 is inverted at the rising edge of the clock signal 17 when the Q output of the JK flip-flop 21 at the first stage is at a high level. As a result, the Q output waveform of the second-stage JK flip-flop 22 becomes as shown in 61 (22) in FIG. 2 with respect to the clock signal waveform 17.

Next, the first stage JK flip-flop 21
NQ output of and Q of second stage J-K flip-flop 22
The output is input to the logic gate 27, and the pulses decoded by the logic gate 27 are supplied to the J and K terminals of the third-stage JK flip-flop 23. Therefore, 3
The Q output of the J-K flip-flop 23 in the second stage is at a high level when the Q output of the J-K flip-flop 22 in the second stage is at a high level, and the NQ output of the J-K flip-flop 21 in the first stage is at a high level. , is inverted at the rising edge of the clock signal. As a result, the third stage J-K flip-flop 23
The Q output waveform of is shown in FIG. 2 for the clock signal waveform 17.
62(23).

[0042] Thereafter, similar operations are repeated. That is,
The Q output of the third-stage J-K flip-flop 23 and the NQ output of the first- and second-stage J-K flip-flops 21 and 22 are input to the logic gates 28 and 29, and the decoded pulses are input to the logic gates 28 and 29. is the fourth stage J-K flip-flop 24
supplied to

The logic gates 30, 31, and 32 are connected to the Q output of the fourth-stage JK flip-flop 24, and the logic gates 1, 2, and 3.
NQ of J-K flip-flops 21, 22, 23 in the row
The output is input, and the decoded pulse is supplied to the fifth stage JK flip-flop 25.

The Q output of the 5th stage and the NQ output of the 1st, 2nd, 3rd, and 4th stage are input to the logic gates 33 to 36, and the decoded pulses are sent to the JK flip-flop of the 6th stage. 26.

As a result, the Q outputs of the JK flip-flops 24 to 26 from the fourth stage onward, that is, the output terminals 63 to 65 of the counter circuit, are supplied with the output signals 63 (24) to 65 in FIG.
The output signal shown in (26) is obtained.

Logic gate 2 for logic decoding at this time
The output signal waveforms 7 to 36 are as shown in 27 to 36 in FIG. Furthermore, the logic gate 37 for adjusting the number of simultaneous changes
The output signal waveforms of 42 are as shown in 37 to 42 in FIG.

In FIG. 2, when attention is paid to the output signals 60 to 65 of the counter circuit, it can be seen that they are Gray code outputs in which the number of simultaneous changes is 1. Therefore, this counter circuit can be used as Gray code counter 1 in FIG.
6, it is possible to prevent fixed pattern noise of vertical stripes from appearing in a part of the screen. Furthermore, the influence of unnecessary radiation on peripheral circuits can also be reduced.

Furthermore, all the waveforms 60 to 65 in FIG.
If the numbers of simultaneous changes from 27 to 36 and from 37 to 42 are expressed graphically, it will look like 66 in FIG. In other words, 6 in Figure 2
At the first timing of 6, 61 changes from low level to high level and at the same time 39 changes from high level to low level, so the number of simultaneous changes is 2. At the next timing, 60 and 27 are changing simultaneously, and the number of simultaneous changes is 2. Furthermore, at the next timing, 62 and 3
8 are changing simultaneously, and the number of simultaneous changes is 2. Similarly, at the timing of all 66 bit changes in FIG. 4, the number of simultaneous changes is 2.

In this way, the counter circuit of FIG. 1 not only functions as a Gray code counter, but also allows the number of simultaneous changes in the output signals of the internal logic gates 27 to 42 to be 2 at all timings. can. Therefore, fluctuations in the power supply current due to changes in the output signals of internal logic gates can be suppressed, and in this respect, the effects of fixed pattern noise and unnecessary radiation can also be reduced.

In the counter circuit of FIG. 1, logic gates 28 to 29, 30 to 32, and 3 for logic decoding are used.
3 to 36 and logic gates 37 to 4 for adjusting the number of simultaneous changes.
The following contrivances have been made to the connection relationship of 0, and this configuration plays an important role in achieving a uniform number of simultaneous changes.

For example, the logic gates 28 and 29 are four-input AND gates, and a four-input AND gate is normally constructed as shown in FIG. However, in the case of FIG. 3, the lower bit I4 changes at a low frequency, whereas the upper bit I1 changes at a high frequency. Therefore, the lower bit I
The timing at which 4 and the upper bit I1 change simultaneously appears with a certain periodicity. If the number of simultaneous changes changes in a constant cycle in this way, a uniform number of simultaneous changes cannot be achieved.

On the other hand, in the counter circuit shown in FIG. 1, by inputting the output signal of the first logic gate 28 to the second logic gate 29, a 4-input AN
It realizes D-gate. With this configuration, the number of simultaneous changes in bits can always be kept constant. The same applies to the other logic gates 30-32, 33-36, and 37-40.

By the way, in the counter circuit of FIG. 1, logic gates 27 to 36 for logic decoding and logic decoders 37 to 36 for adjusting the number of simultaneous changes are connected to the NQ output terminals of each JK flip-flop 21 to 26. The number of 40 is different for each JK flip-flop.

That is, the NQ output terminal of the first-stage JK flip-flop 21 has five logic gates 27, 29,
32, 36, and 40 are connected. Four logic gates 28, 31, 35, and 39 are connected to the NQ output terminal of the second-stage JK flip-flop 22. Three logic gates 30, 34, and 38 are connected to the NQ output terminal of the third-stage JK flip-flop 23. The NQ output terminal of the fourth stage J-K flip-flop 24 is
Two logic gates 33 and 37 are connected. The NQ output terminal of the fifth stage J-K flip-flop 25 has a 1
logic gates 37 are connected. No logic gate is connected to the NQ output terminal of the JK flip-flop 26 at the final stage.

In this way, each JK flip-flop 2
If the numbers of logic gates 1 to 26 are different, the load capacitance of the output line of each counting stage of the counter circuit will be non-uniform. Therefore, counter noise of non-uniform level occurs with respect to the clock input signal.

In the embodiment shown in FIG. 1, in order to solve this problem, logic gates 43 to 59 for adjusting the load capacity are provided.
is added. Among these, the logic gate 43 is the second stage J
-K flip-flop 22. Logic gates 44 and 45 are the third stage J-K flip-flop 23
It is for. Logic gates 46 to 48 are for the fourth stage JK flip-flop 24. Logic gates 49 to 52 are the fifth stage J-K flip-flop 2
5. Logic gates 53 to 57 are for the JK flip-flop 26 in the sixth stage.

In this way, the first stage JK flip-flop 21 includes the five logic gates 27,
29, 32, 36, and 40 are connected. On the other hand, in addition to the aforementioned four logic gates 28, 31, 35, and 39, a logic gate 43 for capacitance adjustment is connected to the second stage J-K flip-flop 22, making a total of five logic gates. Connected. Furthermore, in addition to the aforementioned three logic gates 30, 34, and 38, logic gates 44 and 45 for capacitance adjustment are connected to the third stage J-K flip-flop 23, for a total of five logic gates. Connected. In addition to the aforementioned two logic gates 33 and 37, logic gates 46, 47, and 48 for capacity adjustment are connected to the fourth stage J-K flip-flop 24, for a total of five logic gates. Ru. Furthermore, 5
In addition to the one logic gate 37 described above, the JK flip-flop 25 in the third stage includes a logic gate 49 for capacitance adjustment,
50, 51, and 52 are connected, and in this case, a total of five logic gates are also connected. The final stage JK flip-flop 26 has five logic gates 53 for capacitance adjustment.
~57 are connected.

As described above, according to the configuration of FIG. 1, the total number of logic gates connected to the NQ output terminals of all JK flip-flops 21 to 26 can be set to five. Therefore, the load capacitance of the output line of each counting stage can be equalized. As a result, uneven levels of counter noise are no longer generated with respect to the clock input signal. Therefore, when the counter circuit of FIG. 1 is used as the Gray code counter 16 of FIG. 1, fixed pattern noise and unnecessary radiation can be suppressed in this respect as well.

In FIG. 1, logic gates 58 and 59 for adjusting the load capacity are used to process the output signals of the logic gates 37 to 42 for adjusting the number of simultaneous changes.

Although FIG. 1 shows a 6-bit counter circuit, it goes without saying that it can be constructed with any number of bits.

For example, when an n-bit counter circuit is constructed, the kth (k=n or k<n) bit J−K
The Q output of the J-K flip-flop of the k-1 bit and the NQ output of the J-K flip-flop of the k-2 bit to the 1st bit are connected to the J and K terminals of the flip-flop using logic gates. It is sufficient to supply decoded pulses.

In addition, in FIG. 1, the logic circuit of the counting stage is
It is composed of K flip-flops, and the logic gates 27 to 59 are composed of AND gates, so that the number of simultaneous changes in the logic gates 27 to 42 is always equal to the clock input signal (2 in the case of Fig. 1), and the load capacitance is also Although the counter circuit is configured to be uniform, depending on the purpose of the counter circuit, the logic circuit of the counting stage may be configured with a D flip-flop, an exclusive OR circuit, or the like.

Further, the logic gate for logic decoding may be replaced with a multi-input AND gate or another logic gate that is logically equivalent when viewed from the counting stage side, and the number of simultaneous changes and load capacitance may be changed. For example, NAND gates can be used as the logic gates 27 to 36 for logic decoding. However, in this case, it is necessary to perform phase inversion processing on the input side or the output side. At this time as well, when viewed from the counting stage side, it is logically equivalent to an AND gate.

Furthermore, logic gate 3 for adjusting the number of simultaneous changes
7 to 42 and logic gates 43 to 59 for adjusting load capacity.
The number of simultaneous changes and load capacity may be changed by changing to a multi-input AND gate or other logic circuit.

In any case, by appropriately combining such logic circuits, the number of simultaneous changes in the logic circuit output with respect to the clock input signal can be easily determined within the range of 2 or more and n-1 or less.

Next, a second embodiment of the present invention will be described. As mentioned above, according to the counter circuit of FIG. 1, the number of simultaneous changes in the output signal of the counting stage is always 1, and the number of simultaneous changes in the output signal of the internal logic gate is always 2, both of which are binary codes. The number of simultaneous changes is small compared to a counter. Therefore, using this counter circuit, CCD
By generating a clock signal or a synchronization signal for a signal processing circuit, fixed pattern noise and unnecessary radiation can be reduced.

The second embodiment of the present invention is intended to further reduce the effects of such fixed pattern noise and unnecessary radiation.

That is, in the second embodiment, the frequency of simultaneous change of the bits of the counter circuit is set to a frequency higher than the frequency band of the video signal, and as shown in FIG. to pass only the video signal,
A low-pass filter 67 is connected to remove noise components.

As is clear from FIG. 2, when the clock signal 17 is supplied to the counter circuit of FIG. Further, bit changes in the output signals 27 to 42 of the logic gates also occur in synchronization with the clock signal 17. In other words, the timing at which the simultaneous changes shown at 66 in FIG. 2 occur is synchronized with the clock signal 17.

Therefore, if the clock signal frequency is set to a frequency higher than the video signal frequency band, the frequency of simultaneous change shown at 66 in FIG. 2 also becomes higher than the video signal frequency band.

More specifically, if the period of simultaneous changes shown at 66 in FIG. 2 is T1, then the frequency f1 (=1
/T1) is set to be equal to or higher than the upper limit frequency f0 of the video signal frequency band, as shown in FIG. 5(c). The video signal frequency band varies depending on the television broadcasting system, and is 4.2MHz for the NTSC system, PAL,
In the SECAM system, the frequency is 5 MHz to 6 MHz.

In this way, even if fixed pattern noise occurs due to simultaneous bit changes, it will occur outside the video signal frequency band. For this reason,
As shown in FIG. 4, by connecting a low-pass filter 67 to the output side of the signal processing circuit 3 that passes only the video signal and removes noise components, the influence of noise can be greatly reduced.

In particular, when a counter circuit with a small number of bits changing simultaneously, such as the counter circuit shown in FIG. 1, is used, and the frequency of simultaneous changes is set outside the video signal band,
The noise removal effect is extremely noticeable.

However, if the frequency of simultaneous change is set outside the video signal band, it is not necessarily necessary to use a Gray code counter as the counter circuit; for example, a counter such as a Johnson counter or a ring counter may be used.

Furthermore, when using a counter circuit in which the number of simultaneous changes in bits fluctuates periodically, the frequency of the number of simultaneous changes may be set outside the video signal band.

For example, if the number of simultaneous changes in bits is
), the period T2 when the number of simultaneous changes is 4 and the period T3 when the number of simultaneous changes is 3.
As shown in FIG. 5(c), each frequency f2(
=1/T2) and f3=(1/T3) may be set so that they are outside the video signal band. The same applies to the case of Fig. 5(b), where the frequency f4 (=1/T4
) may be set outside the video signal band.

[0077]

[Effects of the Invention] According to the imaging device of the present invention, by generating fixed pattern noise outside the video signal band due to simultaneous changes in the output signals of the counter, the influence of fixed pattern noise on the video signal is sufficiently reduced. can do.

Furthermore, according to the counter circuit of the present invention,
Not only can a Gray code counter in which the number of simultaneous changes in the output signal of the counting stage is always 1, but also the number of simultaneous changes in the output signal of the internal logic gates always be constant. Therefore, if this counter circuit is used as a CCD driving device, high-quality images with less fixed pattern noise can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a counter circuit in a first embodiment of the present invention.

[Figure 2] Voltage waveform diagram of each part in Figure 1

[Figure 3] Block diagram showing a general 4-input AND gate

FIG. 4 is a block diagram showing an imaging device according to a second embodiment of the present invention.

[Figure 5] Characteristic diagram for explaining the operation in Figure 4

[Figure 6] Block diagram of a conventional imaging device

[Figure 7] Block diagram of a conventional imaging device

[Figure 8] Voltage waveform diagram for explaining the operation in Figure 7

[Figure 9
] Block diagram of an imaging device that is the premise of the present invention

[Figure 10]
Voltage waveform diagram to explain the operation in Figure 9

[Explanation of symbols]

17 Clock signal input terminals 18, 20 Power supply terminals 21 to 26 J-K flip-flops 27 to 36
Logic gates 37-42 for logic decoding Logic gates 43-59 for adjusting the number of simultaneous changes Logic gates 60-65 for adjusting load capacity Counting stage output terminal 67 Low-pass filter

Claims (10)

[Claims] 1. (a) a lens means; (b) a solid-state image sensor that converts light transmitted through the lens means into an electrical signal; (c) a signal processing circuit that processes an output signal of the solid-state image sensor; (d) ) a Gray code counter that counts clock signals and generates a Gray code; (e) means for supplying a clock signal and a synchronization signal to the solid-state image sensor and the signal processing circuit, respectively, according to the output signal of the Gray code counter; Prepare,
The above Gray code counter has (f) n (n is a natural number) bit counting stage, (g) k-1
(k is a natural number from 3 to n) The first bit-th counting stage
a plurality of logic decoding means for supplying to each input terminal of the n-bit counting stage a logic output equivalent to the product of the logic output of and the second logic output of all the counting stages from the (k-2)th bit onward; An imaging device characterized by comprising: 2. The logic decoding means comprises: (a) x (x is a natural number) multi-input logic circuits; (b) an output signal of a first multi-input logic circuit among the x multi-input logic circuits; is input to the second multi-input logic circuit, and the second
means for inputting the output signal of the multi-input logic circuit into a third multi-input logic circuit, and repeating this process up to the x-th multi-input logic circuit; (c) means for inputting the output signal of the x-th multi-input logic circuit into the The imaging device according to claim 1, further comprising means for supplying the input terminal to the input terminal of the counting stage. 3. The Gray code counter has (a) n (n is a natural number) bit counting stage, (b) k-1 (k is 3 or more n bits)
The first logical output of the counting stage of the following natural number) bit-th and k
- a plurality of logic decoding means for supplying a logic output equivalent to the product of the second logic outputs of all the counting stages from the second bit onwards to the input terminal of the n-bit counting stage; (c) each of the counting stages; A plurality of logic circuits for load adjustment are connected to the output terminal of the above-mentioned counting stage, and the sum of the number of logic circuits of the logic decoding means connected to the output terminal of each counting stage and the number of logic circuits for load capacity adjustment is calculated as follows: 2. The imaging apparatus according to claim 1, further comprising load capacity adjusting means for making the load capacity uniform for the counting stages. 4. The Gray code counter includes (a) n (n is a natural number) bit counting stage, (b) k-1 (k is 3 or more n bits)
The first logical output of the counting stage of the following natural number) bit-th and k
- a plurality of logic decoding means for supplying a logic output equivalent to the product of the second logic outputs of all the counting stages from the second bit onwards to the input terminal of the n-bit counting stage; (c) the plurality of logics; 2. The imaging apparatus according to claim 1, further comprising simultaneous change number adjusting means for adjusting the number of simultaneous change of output signals of each logic circuit constituting the decoding means. 5. (a) a lens means; (b) a solid-state image sensor that converts light transmitted through the lens means into an electrical signal; (c) a signal processing circuit that processes an output signal of the solid-state image sensor; (d) ) a counter means that counts clock signals and whose frequency of simultaneous change of the output signals of each counting stage is set outside the video signal band; (e) the solid-state imaging device and the signal processing according to the output signal of the counter means; An imaging device comprising means for supplying a clock signal and a synchronization signal to the circuits, respectively; (f) a filter means connected to an output side of the signal processing circuit and passing only the video signal. 6. The imaging apparatus according to claim 5, wherein the counter means is a Gray code counter. (a) n (n is a natural number) bit counting stage;
(b) Equivalent to the product of the first logical output of the counting stage of bit k-1 (k is a natural number from 3 to n) and the second logical output of all counting stages of bit k-2 and below. A counter circuit comprising a plurality of logic decoding means for supplying a logic output to an input terminal of the n-bit counting stage. 8. The logic decoding means comprises: (a) x (x is a natural number) multi-input logic circuits; (b) an output signal of a first multi-input logic circuit among the x multi-input logic circuits; is input to the second multi-input logic circuit, and the second
means for inputting the output signal of the multi-input logic circuit into a third multi-input logic circuit, and repeating this process up to the x-th multi-input logic circuit; (c) means for inputting the output signal of the x-th multi-input logic circuit into the 8. The counter circuit according to claim 7, further comprising means for supplying input terminals of the counting stage. (a) n (n is a natural number) bit counting stage;
(b) Equivalent to the product of the first logical output of the counting stage of bit k-1 (k is a natural number from 3 to n) and the second logical output of all counting stages of bit k-2 and below. a plurality of logic decoding means for supplying logic outputs to the input terminals of the n-bit counting stages; (c) a plurality of logic circuits for load adjustment are connected to the output terminals of each of the counting stages; A counter circuit comprising load capacitance adjusting means that equalizes the sum of the number of logic circuits of the logic decoding means connected and the number of logic circuits for load capacitance adjustment for all the counting stages. 10. (a) a counting stage of n (n is a natural number) bits, (b) a first logical output of the k-1 (k is a natural number from 3 to n inclusive) bit counting stage and k-2. (c) a plurality of logic decoding means for supplying a logic output equivalent to the product of the second logic outputs of all the counting stages below the bit-th to the input terminal of the n-bit counting stage; (c) the plurality of logic decoding means; A counter circuit comprising simultaneous change number adjusting means for adjusting the number of simultaneous changes in the output signals of each logic circuit constituting the counter circuit.