JPH1093873A - Synchronizing signal pulse generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a synchronizing signal pulse generation circuit for driving a solid-state image pickup element, which does not malfunctions even if the frequency of a reference clock pulse signal is high, suppresses whole consumption current and suppresses synchronous noise (FPN). SOLUTION: A counting circuit for counting the reference clock pulse signal is constituted by a Johnson counter where the D-type flip flops 1-8 of rise synchronous types are shift register-connected and the inverted output NQ of the D-type flip flop 8 in a final stage is fed back and connected to the D-type flip flop 1 in an initial stage. Thus, a state variable becomes uniform and synchronous noise (FPN) is suppressed. When the period of the reference clock pulse signal T>=tpd (CK→Q or CK→NA)+tSU (setup time) is satisfied, a normal operation is executed and therefore speed can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous signal pulse generating circuit (SSG) for driving a solid-state image sensor used in an image pickup system, and more particularly to a synchronous signal which operates at high speed and is effective in suppressing the occurrence of synchronous noise. The present invention relates to a pulse generation circuit.

[0002]

2. Description of the Related Art Generally, in order to operate a solid-state imaging device for a television camera, a pulse for driving the solid-state imaging device is formed by a horizontal synchronization pulse signal and a vertical synchronization pulse signal obtained from a synchronization signal generation circuit. is required.
FIG. 10 shows a configuration example of the imaging system in this case. In FIG. 10, 101 is a lens, 102 is a solid-state imaging device, 103 is a CDS circuit for suppressing random noise generated inside the solid-state imaging device, and 104 is a signal for performing processing such as gamma correction on an output signal of the CDS circuit 103. processing circuit, 105 is a drive control circuit of the solid-state imaging device 102, 106 is a synchronous signal pulse generating circuit, f ₀ is the reference clock pulse signal, H _D, V _D is the horizontal sync shows vertical sync pulse signal.

[0003] In general, a horizontal synchronization processing signal is formed by multi-stage frequency division by a counter during a video period. Therefore, when a conventional binary counter is used, the synchronization signal pulse generation circuit and the drive control circuit are integrated into a single semiconductor in order to cope with the integration of the video system on the mounting substrate to reduce the area occupied on the mounting board. When an integrated circuit is formed on a substrate, a synchronous signal pulse generating circuit interferes with a drive control circuit in the integrated circuit and strongly affects a video signal, and a fixed pattern noise (FPN) in the form of a tape appears in a video.

It is considered that this is because a voltage change due to an instantaneous current change of the power supply circuit accompanying the state transition of the binary counter affects a drive output including a drive control circuit.

In order to solve this problem, the Journal of the Institute of Television Engineers of Japan, Vol. 46, No. 1, pp. 97 to 99 (1992) disclose a counting circuit that performs a counting operation using a gray code. The Gray code is a code in which the number of changes of the flip-flop is always 1 for each state transition in a counting circuit having an N-stage configuration for n-counting in a decimal number, and has 6 counting stages (Q _{0 to} Q ₅ ) An example of a circuit configuration in the case is shown in FIG. 11, and a timing chart showing the operation is shown in FIG.
In FIG. 11, 111 is a main clock input terminal, and 112 to 114
Is a power supply voltage, 121 is a falling synchronous type JK flip-flop, and 122 to 126 are rising synchronous type J flip-flops.
K-type flip-flops 127 to 142 are two-input AND circuits.

As shown in FIG. 12 (E), the counting circuit composed of the Gray code counter always has a small number of state changes of 2, and there is no simultaneous change due to a carry. The number of simultaneous changes is equalized. Therefore, it is reported that the FPN signal is also suppressed, and the output image plane is reduced to a level without visual impairment.

Japanese Patent Application Laid-Open No. 6-261222 also discloses a synchronizing signal pulse generation circuit using a gray code counter having the same purpose. FIG. 13 shows the circuit configuration and FIG. 13 shows an operation timing chart. See Figure 14. In FIG. 13, 151 is an inverter circuit, 152, 155, 15
8,161,164 are rising synchronous type JK type flip-flops, 153,154,156,157,159,160,162,163 are 2-input AN
This is a D circuit. The above-mentioned publication also discloses that the count number of the gray code counter is switched in accordance with the number of pixels of the solid-state imaging device.

[0008]

By the way, when the above-mentioned conventional gray code counter is used for a synchronizing signal pulse generating circuit of a high-speed camera system, there is a problem that a malfunction occurs. Next, the reason will be described with reference to FIGS. In the counting circuit using the gray code counter shown in FIG. 13, the path indicated by the thick line is a critical path that determines the highest frequency of the counting circuit. More specifically, as shown in the timing chart of FIG. 14, the period (T)
/ 2) shows the rise delay time of the inverter circuit 151:
t _PLH (151) and the delay time from the clock input CK # to the output QN # of the JK flip-flop 152: t _PLH (1
52) and the rise delay time of the two-input AND circuits 154, 157, 160, 162: t _PLH (154), t _PLH (157), t _PLH (16
If the sum of 0), t _PLH (162) and the setup time of the JK flip-flop 164: t _SU (164) is not enough, the count-up cannot be performed and a malfunction occurs.

That is, when the duty ratio is 50%,
Half (T / 2) of the reference clock pulse signal needs to satisfy the following equation (1). T / 2 ≧ t _PLH (151) + t _PLH (152) + t _PLH (154) + t _PLH (157) + t _PLH (160) + t _PLH (162) + t _SU (164) (1)

In a C-MOS device, this value is about 14 ns in consideration of a design margin, so that it becomes difficult to design a reference clock pulse signal of 35 MH or more. In particular, when the number of bits increases due to the increase in the number of pixels, the gray code counter cannot be realized.

In the conventional counting circuit using a gray code counter, an extra gate is additionally connected in order to equalize the number of simultaneous changes. That is, the figure
In the one disclosed in the Journal of the Television Society shown in FIG. 11, two-input AND gates 137 to 142 are extra gates for equalizing the number of simultaneous changes, and those disclosed in Japanese Patent Application Laid-Open No. Hei 6-261222. In FIG. 15, the load capacitance matching circuit 170 shown in FIG. 15 corresponds to an extra gate for equalizing the number of simultaneous changes. FIG. 16 shows a circuit configuration example of the load capacitance matching circuit, and FIG. 17 shows operation timing. The addition of such an extra gate increases current consumption, and is not suitable for a high-speed camera due to heat generation and battery life.

Further, in the conventional technique, when a gray code counter is realized by N flip-flops, there are 2 ^N states in total. If there is a state that is not used by chance, a gate circuit for masking that state becomes necessary. In order to realize such a mask gate circuit, the circuit scale is inevitably increased,
As a result, it becomes increasingly difficult to equalize the number of simultaneous changes by using a gate circuit to be masked.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem in a conventional synchronous signal pulse generation circuit using a gray code counter. The present invention suppresses FPN by suppressing the number of simultaneous changes and suppresses a reference clock pulse signal. Synchronous signal pulse for driving a solid-state image sensor suitable for high-speed cameras, which does not malfunction even when the frequency is high, eliminates extra gates, suppresses overall current consumption, and eliminates the need for a mask circuit if the number of states is even. It is an object to provide a generating circuit.

[0014]

The gist of the present invention for solving the above problems is to use a Johnson counter in place of a binary counter or a gray code counter, operate at high speed, and generate synchronous noise (FPN). This constitutes a difficult synchronization signal pulse generation circuit. That is, in the first aspect of the present invention, a reference clock pulse signal is input, and the reference clock pulse signal is counted in a synchronous signal pulse generation circuit for driving a solid-state imaging device that generates a horizontal synchronization pulse signal and a vertical synchronization pulse signal. The counting circuit is constituted by a Johnson counter.

Next, FIG. 1 shows a circuit configuration for explaining the configuration of the counting circuit according to the first aspect of the present invention, and FIG. 2 shows its operation timing. FIG. 1 shows a configuration in which a hexagonal counter using the conventional gray code counter shown in FIGS. 11 and 13 is constituted by a Johnson counter. In FIG. 1, reference numerals 1 to 8 denote rising synchronous D-type flip-flops. A normal output Q ₀ of the D-type flip-flop 1 is supplied to a D input of the D-type flip-flop 2 and a normal output of the D-type flip-flop 2 is output. The force Q ₁ is a D flip-flop 3
Of D to the input, non-inverted output Q ₂ of the D-type flip-flop 3 to the D input of a D-type flip-flop 4, non-inverted output Q ₃ of the D-type flip-flop 4 to the D input of a D-type flip-flop 5, - .... Normal output Q of D-type flip-flop 7
₆ is a shift register connected to the D input of a D-type flip-flop 8, the inverted output NQ ₇ of the last stage D-type flip-flop 8 is feedback-connected to the D input of the first D-type flip-flop 1.

In the counting circuit configured as described above, each D-type flip-flop changes one bit at a time at the rise of the reference clock CK, as shown in FIG. Therefore, since the number of state changes is uniform as in the case of the gray code counter, the synchronizing noise (FPN) can be suppressed. Also, the operating frequency of the Johnson counter is
If the wiring delay is ignored, the condition for operating as a shift register even if the number of bits increases, the period T ≧ t _pd (CK → Q
Or, if CK → NQ delay time) + t _SU (setup time) is satisfied, the circuit operates normally. Even in CMOS devices
It has been confirmed that it operates with a clock of 200 MHz or more.

According to a second aspect of the present invention, there is provided a synchronous signal pulse generating circuit for driving a solid-state imaging device which receives a reference clock pulse signal and generates a horizontal synchronous pulse signal and a vertical synchronous pulse signal. The lower bit of the counting circuit that counts the number of bits is a Johnson counter, and the upper bit is a Gray code counter. According to a third aspect of the present invention, in the synchronous signal pulse generating circuit according to the second aspect, the count numbers of the Johnson counter and the gray code counter constituting the counting circuit are determined according to the number of pixels in the horizontal direction of the solid-state imaging device. It is configured so that it can be switched over.

FIG. 3 is a conceptual diagram showing each of the inventions according to the second and third aspects of the present invention. The lower bits of the counting circuit are Johnson counters (1 / X counter, M bits) 11,
The upper bits are the gray code counter (1 / Y counter,
Since the first stage is received by the Johnson counter 11, the FPN can be suppressed and the operation can be performed at high speed, as in the first embodiment. Further, in the invention according to claim 3, since the Johnson counter has M bits, it can be expressed as X = 2 × M, and since the Gray code counter has N bits, it can be expressed as Y = 2 ^N. Therefore, the number of horizontal pixels of the solid-state imaging device is X ×
If Y = 2 × M × 2 ^N and the number of pixels is even, a counting circuit can be easily realized. Then, the count numbers X,
By switching the value of Y, it is possible to correspond to a solid-state imaging device having various numbers of horizontal pixels.

[0019]

Next, an embodiment will be described. FIG. 4 shows a first example of the synchronization signal pulse generation circuit according to the present invention.
FIG. 5 is a circuit diagram showing the counting circuit according to the embodiment, and FIG. 5 is an explanatory diagram for explaining its operation. This embodiment corresponds to the first aspect of the present invention, and has a two-input OR circuit 21, a two-input AND circuit 22,
The configuration is such that a 7-input AND circuit 23 and a 7-input OR circuit 24 are added. The four circuits constitute a booby trap circuit (Booby Trap) 25. This booby trap circuit 25 is a circuit for returning to normal operation in order to prevent runaway or hang-up of the system when an arbitrary flip-flop may be inverted due to a malfunction such as noise. 5, the operation of the counting circuit including the booby trap circuit 25 will be described.

In the operation shown in FIG. 5, the count value is "0",
In this example, the operation is normal when "1", but the content of the D-type flip-flop 6 is inverted due to noise or the like when "2" and output to the output terminal Q5. In FIG. 5, dotted circles indicate erroneous bits. And
If the booby trap circuit is not provided, an erroneous bit propagates thereafter, so that the erroneous loop will not go out forever unless a system reset is performed. on the other hand,
When a booby trap circuit is provided, an erroneous bit propagates up to the count value of “3” and “4”, but when the count value becomes “5”, the operation returns to the normal operation.

Next, other features of the Johnson counter will be described. As a function of the synchronizing signal pulse generating circuit, it is necessary to generate a horizontal synchronizing pulse signal. For this purpose, the output of the counter must be decoded. In this case, the Gray code counter must decode based on information from all bits, but in the case of the Johnson counter, it can be created based on information from adjacent two bits, and can be realized with a very simple configuration. it can. For example, when it is desired to decode the count value 7, it can be constituted by one 2-input AND circuit 26 as shown in FIG. Moreover,
Since only one bit changes, a static hazard such as a binary counter does not occur.

Next, a second embodiment will be described with reference to FIG. This embodiment corresponds to the invention described in claim 2, and FIG. 8 is a timing chart for explaining the operation. The counting circuit has a drawback that when the count value is generally increased, the circuit size of the Johnson counter is increased, while the gray code counter is not suitable for high-speed operation because the number of critical path gates increases. In the present embodiment, both of the above disadvantages are complemented, and the lower bits of the counting circuit are constituted by a Johnson counter and the upper bits are constituted by a gray code counter.

The example shown in FIG. 7 comprises a hexagonal Johnson counter and a quaternary gray code counter.
It is a 24-digit counter. Reference numerals 31 to 36 denote rising-edge synchronous D-type flip-flops, 37 and 39 denote two-input OR circuits, 38 and 40 denote two-input AND circuits, and 41 and 42 denote exclusive logical product (Ex-NOR) circuits. Circuit enclosed by dotted line
The part consisting of 37 to 40 is the booby trap circuit 43, and FIG.
Have the same functions as those described in the first embodiment shown in FIG.

According to the second embodiment configured as described above, when only the Johnson counter is used,
Six D-type flip-flops, which are required for twelve, are sufficient. Also,
The critical path that determines the highest frequency of the counting circuit is a path indicated by a thick line in FIG. 7 when the count value changes from “3” to “4”. Therefore, if the following expression (2) is satisfied, normal operation is performed. Period T ≧ t _PHL (33: CK → NQ) + t _PHL (37) + t _PHL (38) + t _PHL (39) + t _SU (31) (2) This shows that even a CMOS device operates up to about 100 MHz.

Next, a third embodiment will be described with reference to FIG. This embodiment corresponds to the invention described in claim 3, 9, 51 M-bit Johnson counter, 52 N-bit Gray code counter 53 the output Q _m and N bits of M-bit Johnson counter 51 This is a toggle flip-flop connected between the EN terminals of the gray code counter 52. Table 1 shows that in the counting circuit thus configured, N = 8, the number of horizontal scanning lines H = 1024,
9 is a table showing the relationship between the value of M, the number of pixels of the solid-state imaging device, and the frequency f ₀ of the reference clock pulse signal when the frame period Tf = 1/30 seconds. That is, the number of pixels = counter value of the horizontal synchronization pulse signal generator × the number of horizontal scanning lines = ²⁸ × (2 × M) × 1024 × 50 × M (10,000 pixels) Further, frequency = number of pixels / period = (50 × M) × 30 = 15 × M (MHz). From this table, it can be seen that every time M increases by 1, the number of pixels increases by 500,000 pixels and the frequency increases by 15 MHz.

[0026]

[Table 1]

As described above, various counters can be created by changing the number of flip-flops constituting each counter in accordance with the number of pixels in the horizontal direction of the solid-state imaging device.

Although the three embodiments have been described above, it goes without saying that various modifications and application examples are possible without departing from the gist of the present invention.

[0029]

As described above with reference to the embodiments, according to the present invention, by suppressing the number of simultaneous changes, F
PN can be suppressed, malfunction does not occur even when the frequency of the reference clock pulse signal is high, and the total current consumption can be suppressed by removing extra gates. In addition, if the number of pixels in the horizontal direction is an even number, no mask circuit is required A synchronous signal pulse generation circuit for driving a solid-state imaging device suitable for a high-speed camera can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram showing a basic configuration of a counting circuit of a synchronization signal pulse generation circuit according to the first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the counting circuit shown in FIG.

FIG. 3 is a conceptual diagram for explaining the invention described in claims 2 and 3;

FIG. 4 is a circuit configuration diagram showing a counting circuit according to a specific first embodiment of the present invention.

FIG. 5 is a diagram for explaining an operation comparison depending on the presence or absence of a booby trap circuit in the counting circuit of the first embodiment shown in FIG. 4;

FIG. 6 is a diagram illustrating a configuration example of a decoding circuit of a Johnson counter.

FIG. 7 is a circuit diagram illustrating a counting circuit according to a second embodiment;

FIG. 8 is a timing chart for explaining the operation of the counting circuit shown in FIG. 7;

FIG. 9 is a block diagram illustrating a counting circuit according to a third embodiment;

FIG. 10 is a block diagram illustrating a system configuration example of a general television camera.

FIG. 11 is a circuit configuration diagram illustrating a configuration example of a conventional counting circuit.

12 is a timing chart for explaining the operation of the counting circuit shown in FIG.

FIG. 13 is a circuit configuration diagram showing another configuration example of a conventional counting circuit.

14 is a timing chart for explaining the operation of the counting circuit shown in FIG.

15 is a diagram illustrating a circuit configuration in which a load capacitance matching circuit is added to the conventional counting circuit illustrated in FIG. 13;

16 is a circuit configuration diagram illustrating a configuration example of a load capacitance matching circuit illustrated in FIG. 15;

17 is a timing chart for explaining the operation of the load capacitance matching circuit shown in FIG. 16;

[Explanation of symbols]

 1 to 8, 31 to 36 D-type flip-flops 21, 37, 39 2-input NOR circuit 22, 26, 38, 40 2-input AND circuit 23 7-input AND circuit 24 7-input NOR circuit 25, 43 Booby trap circuit 41, 42 Exclusive AND circuit 51 m-ary Johnson counter 52 n-ary Gray code counter 53 dog flip-flop

Claims (3)

[Claims] 1. A synchronous signal pulse generating circuit for driving a solid-state imaging device which receives a reference clock pulse signal and generates a horizontal synchronous pulse signal and a vertical synchronous pulse signal.
A synchronization signal pulse generating circuit, wherein a counting circuit for counting a reference clock pulse signal is constituted by a Johnson counter. 2. A synchronizing signal pulse generating circuit for driving a solid-state imaging device which receives a reference clock pulse signal and generates a horizontal synchronizing pulse signal and a vertical synchronizing pulse signal.
A synchronization signal pulse generation circuit, wherein lower bits of a counting circuit for counting a reference clock pulse signal are constituted by a Johnson counter, and upper bits are constituted by a gray code counter. 3. The apparatus according to claim 2, wherein the count numbers of the Johnson counter and the gray code counter forming the counting circuit are switched in accordance with the number of pixels in the horizontal direction of the solid-state imaging device. Synchronization signal pulse generation circuit.