JPH04218975A - Non-volatile semiconductor memory - Google Patents

Abstract

PURPOSE:To improve the pattern density of a non-volatile semiconductor memory by burying a control gate in a semiconductor substrate. CONSTITUTION:A control gate 26 is buried in a semiconductor substrate 20, and a floating gate 23 is deposited on the control gate 26 through an insulating film 8. Further, a source region 21 and a drain region 22 are formed, putting the control gate 26 therebetween.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory having a floating gate.

0002

2. Description of the Related Art In a conventional nonvolatile semiconductor memory having a floating gate, such as an ultraviolet erasable semiconductor memory (hereinafter referred to as an EPROM), device isolation between memory transistors is performed using a field oxide film using selective oxidation. A floating gate, an interlayer insulating film, and a control gate are layered on top.

18 to 20 show a conventional EPROM, in which FIG. 18 is a plan view, FIG. 19 is a sectional view taken along line AA' in FIG. 18, and FIG. 20 is a sectional view taken along line BB' in FIG. 18. .

In FIGS. 18 to 20, 1 is a P-type silicon substrate, 2 is a field oxide film for element isolation,
3 is a floating gate made of polysilicon arranged on a silicon substrate 1; 4 is a floating gate 3;
A control gate (word line) made of polysilicon is disposed above with an interlayer insulating film 5 interposed therebetween.

Reference numeral 6 denotes a source region, and numeral 7 denotes a drain region, each of which is an N+ type diffusion region in which the silicon substrate 1 is doped with an N type impurity such as arsenic (As) or phosphorus (P).

9 is an insulating film provided on the control gate 4, 10 is a contact hole provided in the insulating film 9, and the drain region 7 is connected to the metal wiring (not shown) through the contact hole 10. Ohmic contact is made.

Note that the area 11 surrounded by the chain line in FIG.
The area of each transistor is shown.

As is clear from FIG. 18, one contact hole is required for every two transistors.

[0009]

[Problem to be Solved by the Invention] Normally, the N+ type diffusion regions that become the source and drain regions are heated to a temperature of 900 to 950°C.
It is formed by a drive-in process. As mentioned above, in conventional EPROMs, this drive-in causes the diffusion region to diffuse laterally, shortening the effective transistor length (Leff), so the size of the polysilicon serving as the floating gate is made thicker. Therefore, integration beyond a certain level could not be achieved.

The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to improve the pattern density of a nonvolatile semiconductor memory.

[0011]

[Means for Solving the Problems] A nonvolatile semiconductor memory according to a first aspect of the present invention includes a semiconductor substrate of one conductivity type, a diffusion region of another conductivity type constituting a source region, and a diffusion region of another conductivity constituting a drain region. a control gate constituting a word line, which is sandwiched between the mold region and both diffusion regions and is buried in the substrate so that the upper surface thereof is flush with the diffusion region; It is characterized by consisting of a floating gate arranged in such a manner that the

[0012] Furthermore, it is preferable that the floating gate has a larger dimension in the channel direction than the control gate.

Furthermore, in the nonvolatile semiconductor memory according to the second aspect of the present invention, a semiconductor substrate of one conductivity type has diffusion regions of another conductivity type constituting source regions and drain regions of a plurality of memory transistors. Diffusion regions of other conductivity types are formed parallel to each other, and are embedded in the substrate so that the top surfaces of both diffusion regions and the floating gate are on the same plane, and a word line is connected to the diffusion region and the floating gate through an insulating film. An isolation region of one conductivity type is formed in the semiconductor substrate excluding the diffusion region, the floating gate, and the word line.

[0014]

[Operation] In the memory device of the first aspect of the present invention,
Since the control gate is buried in the substrate, lateral diffusion of the type diffusion region is suppressed, and the effective transistor length (Leff) is not shortened. Therefore, the polysilicon size can be reduced accordingly, and the integration density can be improved.

Furthermore, in the memory device according to the second aspect of the present invention, since the word line and the diffusion wiring (source region) can be formed to intersect with each other, there is no need to make a contact for each bit. Holes are no longer required and the size of the memory area can be reduced. Furthermore, in the memory device of the second invention, the floating gate is also embedded in the substrate, so when driving in the diffusion regions on both sides of the floating gate, lateral diffusion of this region is suppressed. Therefore, the effective transistor length does not become short.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS. 1 and 2. FIGS. 1 and 2 show an embodiment in which the present invention is applied to an EPROM using an N-channel MOS transistor.

FIG. 1 is a plan view, and FIG. 2 is a sectional view of FIG.

In FIGS. 1 and 2, 21 is an N+ type diffusion region constituting the source region of the memory transistor, and 22 is an N+ type diffusion region 22 constituting the drain region. The diffusion region 22, ie, the drain region, becomes a bit line, and the diffusion region 21, ie, the source region, becomes a ground line.

Reference numeral 26 denotes a control gate serving as a word drain, which is disposed between the diffusion regions 21 and 22 along both the diffusion regions 21 and 22. Polysilicon is buried in a recess 24 formed in the silicon substrate 20. The diffusion regions 21 and 22 are formed so as to be flush with the upper surfaces of the diffusion regions 21 and 22.

Reference numeral 25 is an interlayer insulating film made of silicon oxide. A floating gate 23 is placed on the control gate 26 with an insulating film 25 interposed therebetween. The floating gate 23 has a larger dimension in the channel direction than the control gate 26.

The diffusion regions 21 and 22 are connected to P or A by the self-alignment method from the floating gate 23.
It is formed by ion-implanting an N-type impurity of s. During this ion implantation, N-type impurities are also mixed into the polysilicon constituting the floating gate 23, so that the floating gate 23 has conductivity.

In the first example, the floating gate 23 is hatched upward to the left, and the word line 26 is hatched upward to the right.

[0023] Thus, the EPROM according to the first invention
In this case, a high voltage (5 to 1
5V), a channel is formed on the side and bottom of the control gate 26.

The voltage of the floating gate 23 increases due to capacitive coupling, and a channel is formed directly below.

When a voltage is applied to the drain region 22, a current flows from the source region 21 to the drain region 22, and hot electrons generated at the end of the drain region 22 jump into the floating gate 23, thereby performing writing. Erasing is performed by irradiating with ultraviolet light.

Furthermore, when the first invention is used in a FEPROM, erasing is performed by writing into hot holes.

Furthermore, by increasing the capacitance between the floating gate 23 and the control gate 26, the write efficiency is improved.

[0028] By increasing the on-state current of the transistor, the speed can be increased.

On the other hand, drive-in of the N+ type diffusion region usually requires heat treatment at 900 to 950°C. As mentioned above, in conventional EPROMs, this drive-in causes the diffusion region to diffuse laterally, shortening the effective transistor length (Leff), so the size of the polysilicon serving as the floating gate is made thicker. I needed to keep it.

On the other hand, in the first invention, since the control gate 26 is embedded in the substrate 20, the lateral diffusion of the N+ type diffusion regions 21 and 22 is suppressed.
The effective transistor length (Leff) does not become shorter. Therefore, the polysilicon size can be reduced accordingly, and the integration density can be improved.

Next, a method for manufacturing a memory according to the first invention will be explained.

After forming a field oxide film for element isolation, a depth of 1000 to 5000 Å is formed for forming word lines.
A recess 24 is formed on the substrate 20 by reactive ion etching (RIE) or the like. After that, the entire surface of the board 20 is covered with 10
Form a gate oxide film of 0 to 500 Å, with a film thickness of 1000 to 5
00 Å polysilicon is deposited over the entire surface.

[0033] Then, spin-on glass (SO
G) etc. to make the surface smooth. Thereafter, the entire surface is etched back until the surface of the substrate 20 is exposed, and the control gate 26 is embedded in the indentation 24 on the surface of the substrate 20.

After that, an interlayer insulating film 25 of SiO2, Si3N4, etc. is formed, and then polysilicon with a thickness of 1000 to 5000 Å is deposited, and this polysilicon is patterned to form a floating gate 23 shown in FIG. .

By the way, the EPRO of the first invention mentioned above
In M, a field oxide film is used to isolate the transistors from each other, and since the shape of the memory is determined by a total of three steps: field oxide film patterning, floating gate patterning, and control gate patterning, the mask Considering misalignment, integration cannot be achieved beyond a certain level.

Furthermore, since the EPROM of the first invention described above requires one contact hole for two transistors, the memory area becomes large, which is an obstacle to achieving integration. Ta.

A second aspect of the present invention provides a nonvolatile semiconductor memory that is further integrated.

A second embodiment of the present invention will be described below with reference to FIGS. 3 to 5. FIGS. 3 to 5 show an embodiment in which the present invention is applied to an EPROM using an N-channel MOS transistor.

3 is a plan view, FIG. 4 is a sectional view taken along the line CC' in FIG. 3, and FIG. 5 is a sectional view taken along the line DD' in FIG.

In the plan view of FIG. 3, an N+ type diffusion region 21 forming a source region and an N+ type diffusion region 22 forming a drain region of a plurality of memory transistors are shown in the vertical direction.
are formed alternately. The diffusion region 22 becomes the bit line and the diffusion region 21 becomes the ground line.

A floating gate 23 is disposed between the diffusion regions 21 and 22 along both diffusion regions 21 and 22, and polysilicon is embedded in a recess 24 formed in the silicon substrate 20. The upper surfaces of the diffusion regions 21 and 22 are formed to be flush with each other. 25 is an insulating film made of silicon oxide.

Diffusion regions 21 and 22 are formed by ion-implanting N-type impurities such as P or As using the floating gate 23 using a self-alignment method. During this ion implantation, the floating gate 23
N-type impurities are also mixed into the polysilicon that makes up the
The floating gate 23 is electrically conductive.

Reference numeral 26 denotes a word line (control gate) made of polysilicon, which is connected to the diffusion regions 21 and 2 on the substrate 20 via an insulating film 25 made of silicon oxide.
2, and a direction intersecting the floating gate 23,
That is, in FIG. 3, it is formed in the horizontal direction. This word line 26 is used as a mask when removing the unnecessary polysilicon region and oxide film of the floating gate 23.

28 is P+ used as an element isolation region.
This is a type diffusion region, and boron (B) is
It is formed in the substrate 20 by ion-implanting P-type impurities such as.

Reference numeral 29 denotes an insulating film made of silicon oxide that covers the sidewalls of the floating gate 23 and the upper and sidewalls of the word line 26.

In FIG. 3, the floating gate 23 is hatched upward to the right, and the word line 26 is hatched upward to the left.

In addition, the area 11 surrounded by the chain line in FIG.
The area of each transistor is shown.

As shown in FIGS. 3 to 5, memory transistors are formed adjacent to each other in the direction along the word line 26, and the regions of the diffusion regions 21 and 22 below the word line 26 are formed adjacent to each other. is the channel area.

As described above, the EPROM of the present invention does not require contact holes in the memory area.

Furthermore, since the memory area is determined by a photoresist process for patterning the polysilicon constituting the floating gate 23 and the polysilicon constituting the word line 26 into predetermined shapes, problems caused by misalignment can be avoided. Less margin is required, and the size of the memory area becomes smaller.

For example, the conventional EPROM shown in FIG. 18 using the standard 2 μm rule and the EPROM according to the present invention shown in FIG.
The PROM memory area (area indicated by a chain line) is as follows.

[0052] In the conventional EPROM, it is 35 μm2/bit, and in the EPROM of the present invention, it is 16 μm2/bit.
According to the present invention, the size is significantly reduced.

Furthermore, the drive-in of the N+ type diffusion region usually requires heat treatment at 900 to 950°C. As mentioned above, in conventional EPROMs, this drive-in causes the diffusion region to diffuse laterally, shortening the effective transistor length (Leff), so the size of the polysilicon serving as the floating gate is made thicker. I needed to keep it.

In contrast, in the present invention, since the floating gate 23 is buried in the substrate 20, the N
Lateral diffusion of the + type diffusion regions 21 and 22 is suppressed, and the effective transistor length (Leff) is not shortened. Therefore, the polysilicon size can be reduced accordingly, and the integration density can be improved.

Next, a method for manufacturing a memory according to the present invention will be explained with reference to FIGS. 6 to 17.

First, as shown in FIGS. 6 and 7, a resist 30 is applied to the surface of a silicon substrate 20, a striped pattern is formed by a lithography process, and reactive ions are applied using this resist 30 as a mask. The substrate 20 is etched away by etching (RIE) or the like to form a recess 24.

Note that FIG. 6 is a plan view, and FIG.
FIG.

Next, as shown in FIGS. 8 and 9, the substrate 2
After forming an oxide film 25 on the 0 surface by thermal oxidation or the like, polysilicon 31 is deposited, and spin-on glass (SOG) or the like is applied thereon to smooth the surface.

Note that FIG. 8 is a plan view, and FIG. 9 is taken along the line EE' in FIG.
FIG.

Next, as shown in FIGS. 10 and 11,
Etching is performed until the surface of the substrate 20 is exposed by etching back the entire surface. The etching conditions at this time are S
The etching rate of the material used for planarization such as OG and polysilicon is set to be equal.

By this etching, the floating gate 23 made of polysilicon is buried in the recess 24 of the substrate 20 and its surface is formed on the same plane as the substrate surface.

Furthermore, using this floating gate 23 as a mask, N-type impurity ions are implanted. This ion implantation uses As, P, etc. at a dose of 1×1015 to 1×1.
Do this at about 017. Then, the portion 32 where the N-type impurity is ion-implanted on the surface of the substrate 20 is removed by drive-in.
These become + type diffusion regions 21 and 22. Further, the N-type impurity implanted into the polysilicon constituting the floating gate 23 imparts conductivity to the polysilicon and reduces the specific resistance of the polysilicon.

10 is a plan view, and FIG. 11 is a plan view of FIG. 10.
-E' line sectional view.

Thereafter, as shown in FIGS. 12 to 14, the surface of the substrate 20 is oxidized to form an oxide film 27, and polysilicon that will become the word line 26 is deposited thereon. After applying a resist 33 to the polysilicon surface, a striped pattern is formed by a lithography process in a direction perpendicular to the diffusion regions 21 and 22 and the floating gate 23, and etching is performed using this resist 33 as a mask. Word lines 26 are formed by patterning polysilicon.

12 is a plan view, and FIG. 13 is a plan view of FIG. 12.
-E' line sectional view; FIG. 14 is a FF' line sectional view of FIG. 12.

After that, as shown in FIGS. 15 and 16,
Using the resist 33 as a mask, the oxide film 27 and unnecessary polysilicon of the floating gate 23 are removed by etching. Then, ion implantation is performed for isolation between elements. This ion implantation involves 1×101 boron (B)
This is done at about 2 to 1×10 14 .

At this time, the N+ type diffusion regions 21 and 22 are made of As.
, P, etc. are implanted at a high concentration, so it remains N+ type, and only the region 34 where N+ implantation is not performed and where there is no polysilicon word line 26 becomes a P+ type isolation region. .

15 is a plan view, and FIG. 16 is a plan view of FIG. 15.
-E' line sectional view.

After that, as shown in FIG. 17, the resist 3
After removing gate 3, oxidation is performed to form floating gate 2.
3 and the side walls and top surface of word line 26 are covered with an oxide film, and further coated with an oxide film such as PSG to form the EPROM shown in FIG.

In the above embodiment, an EPROM using an N-channel MOS transistor has been described, but it is also possible to use a P-channel MOS transistor by reversing the conductivity types of the substrate and the diffusion region.

[0071]

As explained above, in the nonvolatile semiconductor memory device according to the first aspect of the present invention, since the control gate is buried in the substrate, the lateral diffusion of the type diffusion region is suppressed, and the effective The actual transistor length (Leff) is not shortened. Therefore, the polysilicon size can be reduced accordingly, and the integration density can be improved.

In the nonvolatile semiconductor memory device according to the second aspect of the present invention, the word line and the diffusion wiring can be formed so as to intersect with each other, so there is no need to make a contact for each bit. is no longer necessary, and the size of the memory area can be reduced. Therefore, pattern density can be improved.

Furthermore, the nonvolatile semiconductor memory device has the following features:
Since the floating gate is embedded in the substrate, when driving in the diffusion regions on both sides of the floating gate, lateral diffusion of these regions is suppressed, so the effective transistor length is not shortened. Therefore, the dimensions of the polysilicon constituting the floating gate can be shortened, and the integration density can be further improved.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line AA in FIG. 1.

FIG. 3 is a plan view showing a second embodiment of the present invention.

4 is a sectional view taken along line C-C' in FIG. 3. FIG.

FIG. 5 is a sectional view taken along the line D-D' in FIG. 3.

[Fig. 6] EPR according to the embodiment of the second invention of the present invention
FIG. 3 is a plan view showing the first step of the OM manufacturing method.

FIG. 7 is a sectional view taken along the line E-E' in FIG. 6B.

[Fig. 8] EPR according to the embodiment of the second invention of the present invention
FIG. 3 is a plan view showing the second step of the OM manufacturing method.

FIG. 9 is a sectional view taken along the line E-E' in FIG. 8.

FIG. 10 EP according to the embodiment of the second invention of the present invention
FIG. 7 is a plan view showing the third step of the ROM manufacturing method.

11 is a sectional view taken along the line E-E' in FIG. 10.

FIG. 12 EP according to the embodiment of the second invention of the present invention
FIG. 7 is a plan view showing the fourth step of the ROM manufacturing method.

13 is a sectional view taken along the line E-E' in FIG. 12. FIG.

14 is a sectional view taken along line F-F' in FIG. 12.

FIG. 15 EP according to the embodiment of the second invention of the present invention
FIG. 7 is a plan view showing the fifth step of the ROM manufacturing method.

16 is a sectional view taken along the line E-E' in FIG. 15. FIG.

FIG. 17 EP according to the embodiment of the second invention of the present invention
FIG. 7 is a cross-sectional view showing the sixth step of the ROM manufacturing method.

FIG. 18 is a plan view of a conventional EPROM.

19 is a sectional view taken along line A-A' in FIG. 18.

20 is a sectional view taken along the line B-B' in FIG. 18.

[Explanation of symbols]

20 Silicon substrate 21 N+ type diffusion region 22 N+ type diffusion region 23 Floating gate 24 Recess 26 Control gate

Claims (3)

[Claims] 1. A semiconductor substrate of one conductivity type, a diffusion region of another conductivity type constituting a source region, a region of another conductivity type constituting a drain region, which is sandwiched between both diffusion regions and has the same upper surface as the diffusion region. A control gate constituting a word line embedded in the substrate so as to be flat;
A nonvolatile semiconductor memory comprising: a floating gate disposed on the gate electrode with an insulating film interposed therebetween. 2. The nonvolatile semiconductor memory according to claim 1, wherein the floating gate has a larger dimension in the channel direction than the control gate. 3. In a semiconductor substrate of one conductivity type, a diffusion region of another conductivity type constituting a source region of a plurality of memory transistors and a diffusion region of another conductivity type constituting a drain region are formed parallel to each other. A floating gate is embedded in the substrate so that the upper surface thereof is flush with the diffusion region, and is sandwiched between the two diffusion regions.
A word line is connected to the diffusion region and the flow through an insulating film.
A nonvolatile semiconductor memory characterized in that an isolation region of one conductivity type is formed in the semiconductor substrate, which is formed to intersect with the floating gate and excludes the diffusion region, the floating gate, and the word line. .