JPH04215443A - Semiconductor device and its production - Google Patents

Abstract

PURPOSE:To completely prevent the electrostatic breakage of an insulating film by providing an impurity area of the second conductivity type on the surface of a semiconductor substrate of the first conductivity type so as to form a diode and connecting the diode with a gate electrode. CONSTITUTION:A field oxide film 12 is formed on a p-type semiconductor substrate 10 and an element area is separated. An n-type impurity area 14 is provided on the surface of the p-type semiconductor substrate 10 at a prescribed position in the element separating area and a pn-junction diode is formed. The reverse direction pressure resistance of the diode is set at a prescribed value. On a channel area 20 sandwiched by n-type source/drain areas 16 and 18, for example, a gate electrode 24 composed of a polysilicon layer is formed through a gate oxide film 22. The extending part 25 of the gate electrode 24 is connected with an n-type impurity area 14 through a contact window opened on the field oxide film 12. Thus, even when the extending part 25 is electrostatically charged, a charge flows into the p-type semiconductor substrate 10, and the electrostatic breakage of the gate oxide film 22 is prevented.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to an insulated field effect transistor and a method of manufacturing the same.

0002

2. Description of the Related Art In recent years, as LSIs (Large Scale Integrated Circuits) have become faster and more highly integrated, gate insulating films of insulated field effect transistors have become thinner. Therefore, it has become necessary to take measures against electrostatic breakdown of the thinned gate insulating film even during the process.

That is, when ion implantation is performed using a large current, a gate electrode made of a floating polysilicon layer becomes charged, which causes a problem in that the gate insulating film is destroyed. Further, even in a dry etching process such as RIE (reactive ion etching), there is a problem in that the gate electrode is charged by etching ions and the gate insulating film is destroyed.

As the gate insulating film becomes thinner due to the miniaturization of devices, in order to prevent the gate insulating film from being destroyed or deteriorated due to charging of the gate electrode during the process, the following methods have been conventionally used. Countermeasures are being taken. That is, in the ion implantation process, for example, a filament for generating an electron shower is provided in a direction perpendicular to the ion beam to be implanted, and this filament is used to generate secondary electrons to cover the entire surface of the wafer, and the charged wafer, especially the gate electrode, is In the etching process, an oxide film or a P- implantation layer is provided on the back surface of the semiconductor substrate.
A method has been used in which a capacitor is formed in series with the gate capacitor to reduce the voltage applied to the gate insulating film.

[0005]

[Problems to be Solved by the Invention] However, with the above conventional techniques, it is not possible to completely prevent electrostatic breakdown of the gate insulating film due to charging of the gate electrode during the process, and a fundamental countermeasure has been desired. . SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device and a manufacturing method thereof that can completely prevent electrostatic breakdown of a gate insulating film during a process.

[0006]

[Means for Solving the Problems] The above object is to provide a first conductivity type semiconductor substrate, a second conductivity type source and drain region formed opposite to the surface of the semiconductor substrate, and a second conductivity type source and drain region formed opposite to the surface of the semiconductor substrate. In a semiconductor device having a gate electrode formed on a sandwiched channel region with a gate insulating film interposed therebetween, an impurity region of a second conductivity type is provided on the surface of the semiconductor substrate, and the impurity region is separated from the semiconductor substrate and the impurity region. This is achieved by a semiconductor device characterized in that a diode is formed, and an extension of the gate electrode is connected to the impurity region forming the diode.

In the above semiconductor device, an interlayer insulating film is formed on the extending portion of the gate electrode, and the interlayer insulating film is connected to the extending portion of the gate electrode through a contact window opened in the interlayer insulating film. This is achieved by a semiconductor device characterized in that a wiring layer is formed, and the impurity region constituting the diode is formed on the surface of the semiconductor substrate in the element isolation region below the contact window.

[0008]Furthermore, the above-mentioned problem involves a step of forming a field oxide film on a semiconductor substrate of a first conductivity type to form an element isolation region for isolating element regions, and a step of forming a field oxide film on the semiconductor substrate surface of the element isolation region. a step of providing an impurity region of two conductivity types and forming a diode composed of the semiconductor substrate and the impurity region; and after forming a gate insulating film on the semiconductor substrate in the element region, the field oxide film; Depositing a polysilicon layer on the impurity region and the gate insulating film, and etching the polysilicon layer into a predetermined shape to form a gate electrode on the gate insulating film and connecting it to the impurity region. A second conductivity type source is formed on the surface of the semiconductor substrate in the element region by forming an extended portion of the gate electrode and performing an ion implantation method using the gate electrode and the extended portion of the gate electrode as a mask. and a step of forming drain regions facing each other.

[0009] Furthermore, in the above method for manufacturing a semiconductor device, after the step of forming the source and drain regions,
Depositing an interlayer insulating film over the entire surface, and opening a contact window in the interlayer insulating film above the impurity region constituting the diode, and then connecting to the extended portion of the gate electrode through the contact window. This is achieved by a method for manufacturing a semiconductor device characterized by comprising a step of forming a wiring layer.

[0010] Furthermore, in the above method for manufacturing a semiconductor device, before the step of depositing a polysilicon layer on the field oxide film, the impurity region, and the gate insulating film,
This is achieved by a method for manufacturing a semiconductor device, which includes the step of filling an opening above the impurity region with a conductive filler.

[0011]

[Operation] That is, according to the present invention, a diode is formed by providing an impurity region of a second conductivity type on the surface of a semiconductor substrate of a first conductivity type, and this diode is connected to a gate electrode. Even if the gate electrode is charged in the process, the charge either flows forward through this diode into the semiconductor substrate, or alternatively, exceeds the breakdown voltage set low to a predetermined value and flows backward into the semiconductor substrate. Therefore, the voltage applied to the gate insulating film can be relaxed and electrostatic breakdown thereof can be prevented.

Particularly, a remarkable effect appears in the dry etching process for patterning the gate electrode, or in the process of performing ion implantation to form source and drain regions using the gate electrode as a mask.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on illustrative embodiments. 1(a) is a plan view showing an n-channel MOS transistor according to an embodiment of the present invention, and FIG. 1(b) is a plan view showing an n-channel MOS transistor according to an embodiment of the present invention.
) is a sectional view taken along the line X-X', and FIG. 1(c) is a cross-sectional view taken along the line Y-Y'.
FIG.

For example, a field oxide film 12 is formed on a p-type semiconductor substrate 10 to isolate device regions. Furthermore, the p-type semiconductor substrate 10 at a predetermined location in the element isolation region is
An n-type impurity region 14 is provided on the surface, forming a pn junction diode constituted by the p-type semiconductor substrate 10 and the n-type impurity region 14. The n-type impurity region 14 constituting this pn junction diode is formed by the field oxide film 1.
2 is separated from the element region of the p-type semiconductor substrate 10. And the reverse breakdown voltage of this pn junction diode is
It is set to a predetermined value.

Furthermore, n-type source and drain regions 16 and 18 are formed facing each other on the surface of the p-type semiconductor substrate 10 in the element region. These n-type source and drain regions 16
, 18, a gate electrode 24 made of, for example, a polysilicon layer is formed with a gate oxide film 22 interposed therebetween. Further, the extending portion 25 of the gate electrode 24 is connected to the n-type impurity region 14 through a contact window opened in the field oxide film 12.

An interlayer insulating film 26 made of, for example, a silicon oxide film is formed on the field oxide film 12, the n-type source and drain regions 16 and 18, the gate electrode 24, and its extension 25. Source and drain electrodes made of, for example, an Al layer are connected to the n-type source and drain regions 16 and 18 through contact windows 28 and 30 opened in the interlayer insulating film 26 above the n-type source and drain regions 16 and 18. 32 and 34 are formed, respectively. Further, a wiring layer 38 made of, for example, an Al layer is formed to be connected to the extended portion 25 of the gate electrode 24 via a contact window 36 opened in the interlayer insulating film 26 above the n-type impurity region 14. And an insulating film 4 as a protective film on the entire surface.
0 is formed to protect the entire element.

Next, a method for manufacturing the n-channel MOS transistor shown in FIG. 1 will be explained using process diagrams shown in FIGS. 2 and 3. A field oxide film 12 is formed on a p-type semiconductor substrate 10 by selective oxidation using a silicon nitride film (not shown) as a mask to isolate device regions. Subsequently, the field oxide film 12 at a predetermined position is selectively etched away to expose a region where a diode is to be formed on the surface of the p-type semiconductor substrate 10 in the element isolation region. Then, impurities are selectively added to the surface of the p-type semiconductor substrate 10 in this diode formation region to form an n-type impurity region 14. In this way, the p-type semiconductor substrate 10 and the n-type impurity region 14
and form a pn junction diode whose reverse breakdown voltage is set to a predetermined value (see FIG. 2(a)).

Here, after the field oxide film 12 was formed, a part of it was selectively etched away to expose the surface of the p-type semiconductor substrate 10 in the region where the diode was to be formed. During the formation, a silicon nitride film is also formed in the region where the diode is to be formed as a mask for selective oxidation, and after the selective oxidation, this silicon nitride film is removed and the surface of the p-type semiconductor substrate 10 in the region where the diode is to be formed is removed. may be exposed.

Next, after a gate oxide film 22 is formed on the p-type semiconductor substrate 10 in the element region, a polysilicon layer 24a is formed on the entire surface. This polysilicon layer 24a is formed on the gate oxide film 22 and also on the n-type impurity region 14 constituting the pn junction diode (
(See Figure 2(b)). Next, a resist 42 is applied to the entire surface, and then patterned into a predetermined shape using photolithography. Then, RIE is performed using this patterned resist 42 as a mask, and the polysilicon layer 24a is patterned into a predetermined shape to form an extension of the gate electrode 24 connected to the gate electrode 24 on the gate oxide film 22 and the n-type impurity region 14. The existing portion 25 is formed.

In the conventional etching process, the gate electrode 24 is charged by etching ions and a voltage is applied to the gate oxide film 22. However, in this embodiment, the gate electrode 24 and its extension 25 are Since it is connected to the p-type semiconductor substrate 10 via the type impurity region 14, and the reverse breakdown voltage of the pn junction diode constituted by the n-type impurity region 14 and the p-type semiconductor substrate 10 is set to a predetermined value. Therefore, when the positive charge on the gate electrode 24 exceeds a certain level and there is a risk of destroying the gate oxide film 22, the positive charge flows to the p-type semiconductor substrate 10 via the pn junction diode. Therefore, an amount of charge sufficient to cause electrostatic damage to the gate oxide film 22 is not accumulated in the gate electrode 24 (see FIG. 2(c)).

Next, the gate electrode 24 and its extension 2
5 and the field oxide film 12 as a mask, ions are implanted into the surface of the p-type semiconductor substrate 10 in the element region.
Type source and drain regions 16 and 18 are formed facing each other. As a result, a channel region 20 is formed on the surface of the p-type semiconductor substrate 10 sandwiched between the n-type source and drain regions 16 and 18.

In the conventional process of ion implantation with a large current, there was a risk that the gate electrode 24 serving as a mask would be charged and a voltage exceeding the withstand voltage would be applied to the underlying gate oxide film 22. In this example,
Gate electrode 24 and its extension 25 are n-type impurity region 1
4 to the p-type semiconductor substrate 10, the amount of positive charge charged to the gate electrode 24 is limited, and the voltage applied to the gate oxide film 22 is neutralized. Therefore, electrostatic damage to the gate oxide film 22 can be prevented (see FIG. 3(a)).

Next, in the same manner as in the conventional MOS transistor manufacturing method, an interlayer insulating film 26 made of a silicon oxide film is formed on the entire surface, and contact windows 28 are formed at predetermined positions.
After openings 30 and 36, an Al layer is deposited over the entire surface, and this Al layer is patterned into a predetermined shape. Then, the n-type source and drain regions 1 are connected through contact windows 28 and 30.
Gate and drain electrodes 32 and 34 made of Al layers connected to the gate electrodes 6 and 18 are formed, respectively, and an aluminum layer connected to the extension portion 25 of the gate electrode 24 through the contact window 36 is formed.
A wiring layer 38 consisting of an l layer is formed.

At this time, the contact window 36 where the extending portion 25 of the gate electrode 24 and the wiring layer 38 are connected is located above the n-type impurity region 14 constituting the pn junction diode. Conversely, the extension portion 2 of the gate electrode 24
It may be said that the n-type impurity region 14 is formed on the surface of the p-type semiconductor substrate 10 in the element isolation region located below the contact window 36 between the wiring layer 38 and the wiring layer 38.

Finally, an insulating film 40 as a protective film for protecting the entire element is formed over the entire surface (see FIG. 3(b)). According to this embodiment, a pn junction diode is formed by the n-type impurity region 14 provided on the surface of the p-type semiconductor substrate 10, and the gate electrode 24 is connected to the n-type impurity region 14 constituting the pn junction diode. Because the extension part 25 is connected, even if the gate electrode 24 and its extension part 25 are charged, if the breakdown voltage of the pn junction diode is exceeded, the positive charge on the gate electrode 24 becomes p-type. Since it flows into the semiconductor substrate 10, electrostatic damage to the gate oxide film 22 is prevented.

In particular, this effect is remarkable because the gate electrode 24 is easily charged by the ions used during the etching process for forming the gate electrode 24 and the ion implantation process using the gate electrode 24 as a mask. be. Of course, similar effects can be achieved in subsequent steps as well. Furthermore, since the n-type impurity region 14 is provided in the element isolation region, and is particularly located below the contact window 36 between the extending portion 25 of the gate electrode 24 and the wiring layer 38, the provision of the n-type impurity region 14 provides special protection. The degree of integration of the semiconductor device is not reduced.

Furthermore, the gate voltage applied to the gate electrode 24 is set to be sufficiently lower than the breakdown voltage of the pn junction diode composed of the n-type impurity region 14 and the p-type semiconductor substrate 10 during operation of the transistor. It is set. Therefore, the presence of the pn junction diode formed by the n-type impurity region 14 does not adversely affect the operation of the transistor.

Note that in the above embodiment, the n-type impurity region 14 and the gate electrode 24 are directly connected through the opening formed in the field oxide film 12; This n-type impurity region 14
The upper opening may be filled with a conductive filler 44 made of, for example, a W (tungsten) layer or a polycrystalline silicon layer. That is, most of the opening above the n-type impurity region 14 is filled with this filler 44, and the n-type impurity region 14 and the extension portion 25 of the gate electrode 24 are connected via this filler 44. become.

As a result, when the field oxide film 12 is sufficiently thick, a considerable step is formed in the opening above the n-type impurity region 14.
Since it plays the role of alleviating and preventing the occurrence of the step difference, the connection between the n-type impurity region 14 and the gate electrode 24 can be ensured. Further, in the above embodiment, the case of an n-channel MOS transistor was described, but the present invention is also applicable to a p-channel MOS transistor. That is, in this case, a p-type impurity region is formed on the surface of the n-type semiconductor substrate to constitute a pn junction diode. At this time, the positive charge charged on the gate electrode 24 flows in the forward direction of the junction pn junction diode formed by the n-type semiconductor substrate and the p-type impurity region. Note that in the transistor operation in this case, since a positive power supply voltage is applied to the n-type semiconductor substrate side, the presence of the pn junction diode does not adversely affect the transistor operation.

Furthermore, it goes without saying that the present invention can be applied to field effect transistors other than MOS type.

[0031]

As described above, according to the present invention, a diode is formed by providing an impurity region of a second conductivity type on the surface of a semiconductor substrate of a first conductivity type, and the extending portion of the gate electrode forms a diode. By being connected to the constituting impurity region, even if the gate electrode is charged during the process, the charge flows out to the semiconductor substrate via the diode, thereby preventing high voltage from being applied to the gate insulating film. Therefore, electrostatic breakdown of the gate insulating film can be prevented.

[0032] Thereby, it is possible to improve the yield in manufacturing the semiconductor device and to improve the reliability of the semiconductor device.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an n-channel MOS transistor according to an embodiment of the present invention.

2 is a process diagram (part 1) showing a method for manufacturing the MOS transistor shown in FIG. 1; FIG.

3 is a process diagram (part 2) showing a method for manufacturing the MOS transistor of FIG. 1; FIG.

FIG. 4: An n-channel MOS according to another embodiment of the present invention.
FIG. 2 is a diagram showing a transistor.

[Explanation of symbols]

10...p-type semiconductor substrate 12...Field oxide film 14...n-type impurity region 16...n-type source region 18...n-type drain region 20...Channel area 22...Gate oxide film 24a...Polysilicon layer 24...Gate electrode 25...Extended portion of gate electrode 26...Interlayer insulating film 28, 30, 36...Contact window 32...Source electrode 34...Drain electrode 38...Wiring layer 40...Insulating film 42...Resist 44...Filling material

Claims (5)

[Claims] 1. A semiconductor substrate of a first conductivity type, a source and drain region of a second conductivity type formed opposite to the surface of the semiconductor substrate, and a gate on a channel region sandwiched between the source and drain regions. In a semiconductor device having a gate electrode formed through an insulating film, an impurity region of a second conductivity type is provided on the surface of the semiconductor substrate, and a diode composed of the semiconductor substrate and the impurity region is formed, A semiconductor device, wherein an extended portion of the gate electrode is connected to the impurity region constituting the diode. 2. The semiconductor device according to claim 1,
An interlayer insulating film is formed on the extending portion of the gate electrode, a wiring layer is formed to connect to the extending portion of the gate electrode through a contact window opened in the interlayer insulating film, and a wiring layer is formed below the contact window. A semiconductor device, wherein the impurity region constituting the diode is formed on the surface of the semiconductor substrate in the element isolation region. 3. A step of forming a field oxide film on a semiconductor substrate of a first conductivity type to form an element isolation region for isolating element regions; and forming a field oxide film on a surface of the semiconductor substrate in the element isolation region. After forming an impurity region and forming a diode composed of the semiconductor substrate and the impurity region, and forming a gate insulating film on the semiconductor substrate in the element region, the field oxide film, the impurity region and depositing a polysilicon layer on the gate insulating film, etching the polysilicon layer into a predetermined shape to form a gate electrode on the gate insulating film, and connecting the gate electrode to the impurity region. forming an extended portion of the gate electrode and an ion implantation method using the gate electrode and the extended portion of the gate electrode as a mask to form source and drain regions of a second conductivity type on the surface of the semiconductor substrate in the element region. 1. A method of manufacturing a semiconductor device, comprising a step of forming the semiconductor device facing each other. 4. The method of manufacturing a semiconductor device according to claim 3, further comprising the step of depositing an interlayer insulating film over the entire surface after the step of forming the source and drain regions, and depositing an interlayer insulating film over the impurity region constituting the diode. A method for manufacturing a semiconductor device, comprising the steps of: opening a contact window in the interlayer insulating film, and then forming a wiring layer connected to an extended portion of the gate electrode through the contact window. 5. The method of manufacturing a semiconductor device according to claim 3, wherein before the step of depositing a polysilicon layer on the field oxide film, the impurity region, and the gate insulating film, a polysilicon layer on the impurity region is deposited. A method for manufacturing a semiconductor device, comprising the step of filling an opening with a conductive filler.