JPH04214695A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04214695A
JPH04214695A JP40181490A JP40181490A JPH04214695A JP H04214695 A JPH04214695 A JP H04214695A JP 40181490 A JP40181490 A JP 40181490A JP 40181490 A JP40181490 A JP 40181490A JP H04214695 A JPH04214695 A JP H04214695A
Authority
JP
Japan
Prior art keywords
circuit board
printed circuit
semiconductor device
chip
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP40181490A
Other languages
Japanese (ja)
Inventor
Shinya Kawarabayashi
河原林 眞也
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP40181490A priority Critical patent/JPH04214695A/en
Publication of JPH04214695A publication Critical patent/JPH04214695A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To enhance mounting density of a semiconductor device to be mounted at the surface of a printed circuit board. CONSTITUTION:Pins 12 to 14 for chip select signal are provided at the area of semiconductor device 11 where a pin 2 for signal is not provided. These chip select signal pins 12 to 14 are connected with an operation selection circuit of a semiconductor chip. In this case, the semiconductor device 11 is stacked for the mounting in the plural number on the same area of a printed circuit board 3. Since only the semiconductor device 11 in which a signal is applied to the chip select pins operates, if the semiconductor devices are stacked for the mounting in three dimensions, the other semiconductor devices 11 do not operate irregularly.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明はプリント基板に表面実装
される半導体装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device surface-mounted on a printed circuit board.

【0002】0002

【従来の技術】従来、表面実装型の半導体装置としては
、下方に遍在された先端接続部を有する外部接続用リー
ドが樹脂パッケージの側部に複数本突設されたものがあ
る。この種の従来の半導体装置を図3および図4によっ
て説明する。
2. Description of the Related Art Conventionally, some surface-mounted semiconductor devices have a plurality of external connection leads protruding from the side of a resin package, each having a terminal end connection portion distributed downwardly. A conventional semiconductor device of this type will be explained with reference to FIGS. 3 and 4.

【0003】図3は従来の半導体装置をプリント基板上
に表面実装させた状態を示す側面図、図4は従来の半導
体装置をプリント基板上に表面実装させた状態を示す平
面図である。これらの図において、1は樹脂パッケージ
としてのモールド樹脂で、このモールド樹脂1内に半導
体チップ(図示せず)が封止されている。2は前記モー
ルド樹脂1内の半導体チップに接続されて半導体チップ
と外部配線とを電気的に接続する外部接続用リードとし
ての従来公知の信号用ピンである。この信号用ピン2は
、モールド樹脂1の2側部に複数本、それぞれ側方へ向
けて突設されており、その突出端部にはモールド樹脂1
の下面側に遍在された半田付け部2aが形成されている
FIG. 3 is a side view showing a conventional semiconductor device surface-mounted on a printed circuit board, and FIG. 4 is a plan view showing a conventional semiconductor device surface-mounted on a printed circuit board. In these figures, reference numeral 1 denotes a mold resin serving as a resin package, and a semiconductor chip (not shown) is sealed within this mold resin 1. Reference numeral 2 denotes a conventionally known signal pin as an external connection lead connected to the semiconductor chip in the molded resin 1 to electrically connect the semiconductor chip and external wiring. A plurality of signal pins 2 are provided on two sides of the molded resin 1, each protruding laterally, and each of the signal pins 2 is provided with a molded resin 1 at the protruding end.
Soldering portions 2a are formed ubiquitously on the lower surface side.

【0004】3はプリント基板で、このプリント基板3
上には前記信号用ピン2が半田付けされる半田付け用パ
ッド(図示せず)が形成されている。なお、この半田付
け用パッドは、プリント基板上に回路を構成する配線パ
ターン(図示せず)に接続されている。
3 is a printed circuit board, and this printed circuit board 3
A soldering pad (not shown) to which the signal pin 2 is soldered is formed on the top. Note that this soldering pad is connected to a wiring pattern (not shown) that constitutes a circuit on the printed circuit board.

【0005】このように構成された従来の半導体装置は
、プリント基板3上にモールド樹脂1を載置させるよう
にして表面実装される。その際には信号用ピン2の半田
付け部2aがプリント基板3上の半田付け用パッドに半
田付けされる。そして、図4に示すように、従来の半導
体装置は一つのプリント基板3上に平面的に複数個並べ
て実装されていた。
The conventional semiconductor device constructed as described above is surface mounted by placing the mold resin 1 on the printed circuit board 3. At that time, the soldering portion 2a of the signal pin 2 is soldered to the soldering pad on the printed circuit board 3. As shown in FIG. 4, a plurality of conventional semiconductor devices are mounted on one printed circuit board 3 in a two-dimensional array.

【0006】[0006]

【発明が解決しようとする課題】しかるに、このように
半導体装置をプリント基板上に平面的に並べて実装した
のでは、一つのプリント基板3上に多くの半導体装置を
実装させるにも限度がある。すなわち、従来の半導体装
置ではそれ以上に実装密度を高めることができない。
However, if the semiconductor devices are arranged and mounted on a printed circuit board in this way, there is a limit to how many semiconductor devices can be mounted on one printed circuit board 3. That is, in conventional semiconductor devices, it is not possible to further increase the packaging density.

【0007】[0007]

【課題を解決するための手段】本発明に係る半導体装置
は、樹脂パッケージの側部におけるリードが設けられて
いない部分に、プリント基板と半導体チップの動作選択
回路とを接続しかつ外部信号により半導体チップを選択
的に動作させるチップ選択用リードを突設してなり、前
記外部接続用リードの突出寸法およびチップ選択用リー
ドの上下方向への長さと、チップ選択用リードの配設位
置とを上下位置に応じて変えると共に、上下の半導体装
置どうしの外部接続用リードをプリント基板の同一パッ
ドに接続させて上下に複数個重ねてプリント基板に実装
したものである。
[Means for Solving the Problems] A semiconductor device according to the present invention connects a printed circuit board and an operation selection circuit of a semiconductor chip to a side portion of a resin package where no leads are provided, and uses an external signal to A chip selection lead is provided to selectively operate the chip, and the protrusion dimension of the external connection lead, the length of the chip selection lead in the vertical direction, and the arrangement position of the chip selection lead are adjusted vertically. The external connection leads of the upper and lower semiconductor devices are connected to the same pad on the printed circuit board, and a plurality of semiconductor devices are stacked one above the other and mounted on the printed circuit board.

【0008】[0008]

【作用】チップ選択用リードに信号が送られた半導体装
置のみが動作するから、半導体装置を複数個重ねてプリ
ント基板に実装することができ、プリント基板に対する
半導体装置の占有面積が小さくなる。
[Operation] Since only the semiconductor device to which a signal is sent to the chip selection lead operates, a plurality of semiconductor devices can be stacked and mounted on a printed circuit board, and the area occupied by the semiconductor devices on the printed circuit board is reduced.

【0009】[0009]

【実施例】以下、本発明の一実施例を図1および図2に
よって詳細に説明する。
Embodiment An embodiment of the present invention will be explained in detail below with reference to FIGS. 1 and 2.

【0010】図1は本発明に係る半導体装置をプリント
基板上に表面実装させた状態を示す側面図、図2は本発
明に係る半導体装置をプリント基板上に表面実装させた
状態を示す平面図である。これらの図において前記図3
および図4で説明したものと同一もしくは同等部材につ
いては、同一符号を付し詳細な説明は省略する。これら
の図において、11は本発明に係る半導体装置で、この
半導体装置11は、プリント基板3上の同一位置に複数
個(本実施例では3個)重ねるようにして実装されてい
る。各半導体装置11の信号用ピン2は、図2に示すよ
うに上から見てプリント基板3の同一位置に半田付けさ
れ、モールド樹脂側方への突出寸法および上下方向の長
さはそれぞれの半導体装置11の上下位置に応じた寸法
に設定されている。
FIG. 1 is a side view showing a semiconductor device according to the present invention surface-mounted on a printed circuit board, and FIG. 2 is a plan view showing a semiconductor device according to the present invention surface-mounted on a printed circuit board. It is. In these figures, the above figure 3
Components that are the same or equivalent to those explained in FIG. In these figures, reference numeral 11 denotes a semiconductor device according to the present invention, and a plurality of semiconductor devices 11 (three in this embodiment) are mounted on the same position on the printed circuit board 3 so as to be stacked. The signal pins 2 of each semiconductor device 11 are soldered to the same position on the printed circuit board 3 when viewed from above, as shown in FIG. The dimensions are set according to the vertical position of the device 11.

【0011】12,13,14はチップ選択用リードと
してのチップセレクト信号用ピンで、これらのチップセ
レクト信号用ピン12〜14はモールド樹脂1における
信号用ピン2が設けられていない部分に突設されている
。また、各チップセレクト信号用ピン12,13,14
は、一端が半導体チップの動作選択回路に接続され、他
端(モールド樹脂1からの突出端)はモールド樹脂1の
下方へ遍在されてプリント基板3のチップセレクト回路
(図示せず)に半田付けによって接続されている。さら
に、これらのチップセレクト信号用ピン12,13,1
4は上下の半導体装置11では上から見て異なる位置に
配設され、その上下方向の長さは半導体装置11の上下
位置に応じた寸法に設定されている。すなわち、最も下
に位置する半導体装置11のチップセレクト信号用ピン
12が最も短く、最も上に位置する半導体装置11のチ
ップセレクト信号用ピン14が最も長く形成されている
Reference numerals 12, 13, and 14 are chip select signal pins as chip selection leads, and these chip select signal pins 12 to 14 are provided protrudingly in a portion of the molded resin 1 where the signal pin 2 is not provided. has been done. In addition, each chip select signal pin 12, 13, 14
One end is connected to the operation selection circuit of the semiconductor chip, and the other end (the end protruding from the molding resin 1) is placed below the molding resin 1 and soldered to the chip selection circuit (not shown) of the printed circuit board 3. Connected by attachment. Furthermore, these chip select signal pins 12, 13, 1
4 are disposed at different positions in the upper and lower semiconductor devices 11 when viewed from above, and their lengths in the vertical direction are set to dimensions corresponding to the vertical positions of the semiconductor devices 11. That is, the chip select signal pin 12 of the semiconductor device 11 located at the bottom is the shortest, and the chip select signal pin 14 of the semiconductor device 11 located at the top is the longest.

【0012】このように構成された本発明に係る半導体
装置11は、信号用ピン2およびチップセレクト信号用
ピン12〜14をプリント基板3上の所定位置に半田付
けしてプリント基板3上に複数個重ねて実装される。そ
して、例えば最も下に位置する半導体装置11を動作さ
せるには、その半導体装置11のチップセレクト信号用
ピン12にチップセレクト信号を送って半導体チップの
動作選択回路を動作させて行う。なお、前記チップセレ
クト信号は外部回路よりプリント基板3のチップセレク
ト回路を介してチップセレクト信号用ピン12に伝えら
れる。すなわち、本実施例で示すように半導体チップ1
1をプリント基板3の同一箇所に3個重ねて実装させて
も、3個の半導体装置11のそれぞれのチップセレクト
信号用ピン12〜14に選択的にチップセレクト信号を
送ることで、いずれか1つの半導体装置11を選んで動
作させることができる。
The semiconductor device 11 according to the present invention configured as described above has a plurality of signal pins 2 and chip select signal pins 12 to 14 soldered to predetermined positions on the printed circuit board 3. Implemented one after the other. For example, to operate the semiconductor device 11 located at the bottom, a chip select signal is sent to the chip select signal pin 12 of the semiconductor device 11 to operate the operation selection circuit of the semiconductor chip. The chip select signal is transmitted from an external circuit to the chip select signal pin 12 via the chip select circuit of the printed circuit board 3. That is, as shown in this embodiment, the semiconductor chip 1
Even if three semiconductor devices 1 are stacked and mounted on the same location on the printed circuit board 3, by selectively sending a chip select signal to the chip select signal pins 12 to 14 of each of the three semiconductor devices 11, any one of the semiconductor devices 11 can be mounted. One semiconductor device 11 can be selected and operated.

【0013】したがって、チップセレクト信号用ピンに
信号が送られた半導体装置11のみが動作するから、半
導体装置11を複数個重ねてプリント基板3に実装する
ことができ、プリント基板3に対する半導体装置11の
占有面積が小さくなる。
Therefore, since only the semiconductor device 11 to which a signal is sent to the chip select signal pin operates, it is possible to stack a plurality of semiconductor devices 11 and mount them on the printed circuit board 3. occupies a smaller area.

【0014】[0014]

【発明の効果】以上説明したように本発明に係る半導体
装置は、樹脂パッケージの側部におけるリードが設けら
れていない部分に、プリント基板と半導体チップの動作
選択回路とを接続しかつ外部信号により半導体チップを
選択的に動作させるチップ選択用リードを突設してなり
、前記外部接続用リードの突出寸法およびチップ選択用
リードの上下方向への長さと、チップ選択用リードの配
設位置とを上下位置に応じて変えると共に、上下の半導
体装置どうしの外部接続用リードをプリント基板の同一
パッドに接続させて上下に複数個重ねてプリント基板に
実装したものであるため、チップ選択用リードに信号が
送られた半導体装置のみが動作するから、半導体装置を
複数個重ねてプリント基板に立体的に実装することがで
きる。したがって、プリント基板に対する半導体装置の
占有面積が小さくなるから、実装密度を高めることがで
きる。
Effects of the Invention As explained above, the semiconductor device according to the present invention connects the printed circuit board and the operation selection circuit of the semiconductor chip to the side portion of the resin package where no leads are provided, and connects the operation selection circuit of the semiconductor chip to the side portion of the resin package. A chip selection lead for selectively operating a semiconductor chip is provided in a protruding manner, and the protrusion dimension of the external connection lead, the vertical length of the chip selection lead, and the arrangement position of the chip selection lead are determined. The external connection leads of the upper and lower semiconductor devices are connected to the same pad on the printed circuit board, and multiple semiconductor devices are stacked one above the other and mounted on the printed circuit board, so the signal is sent to the chip selection lead. Since only the semiconductor devices that are sent operate, a plurality of semiconductor devices can be stacked and mounted three-dimensionally on a printed circuit board. Therefore, since the area occupied by the semiconductor device on the printed circuit board is reduced, the packaging density can be increased.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明に係る半導体装置をプリント基板上に表
面実装させた状態を示す側面図である。
FIG. 1 is a side view showing a state in which a semiconductor device according to the present invention is surface-mounted on a printed circuit board.

【図2】本発明に係る半導体装置をプリント基板上に表
面実装させた状態を示す平面図である。
FIG. 2 is a plan view showing a semiconductor device according to the present invention surface-mounted on a printed circuit board.

【図3】従来の半導体装置をプリント基板上に表面実装
させた状態を示す側面図である。
FIG. 3 is a side view showing a conventional semiconductor device surface-mounted on a printed circuit board.

【図4】従来の半導体装置をプリント基板上に表面実装
させた状態を示す平面図である。
FIG. 4 is a plan view showing a conventional semiconductor device surface-mounted on a printed circuit board.

【符号の説明】[Explanation of symbols]

1  モールド樹脂 2  信号用ピン 3  プリント基板 11  半導体装置 1 Mold resin 2 Signal pin 3 Printed circuit board 11 Semiconductor device

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  下方に遍在された先端接続部を有する
外部接続用リードが樹脂パッケージの側部に複数本突設
され、プリント基板に表面実装される半導体装置におい
て、前記樹脂パッケージの側部における前記リードが設
けられていない部分に、前記プリント基板と半導体チッ
プの動作選択回路とを接続しかつ外部信号により半導体
チップを選択的に動作させるチップ選択用リードを突設
してなり、前記外部接続用リードの突出寸法およびチッ
プ選択用リードの上下方向への長さと、チップ選択用リ
ードの配設位置とを上下位置に応じて変えると共に、上
下の半導体装置どうしの外部接続用リードをプリント基
板の同一パッドに接続させて上下に複数個重ねてプリン
ト基板に実装したことを特徴とする半導体装置。
1. In a semiconductor device surface-mounted on a printed circuit board, in which a plurality of external connection leads having tip connection portions distributed downwardly are protruded from the side of a resin package, the semiconductor device is surface-mounted on a printed circuit board. A chip selection lead for connecting the printed circuit board and the operation selection circuit of the semiconductor chip and selectively operating the semiconductor chip by an external signal is provided protrudingly in a portion where the lead is not provided, and the external The protruding dimensions of the connection leads, the vertical length of the chip selection leads, and the arrangement position of the chip selection leads are changed depending on the vertical position, and the external connection leads between the upper and lower semiconductor devices are connected to the printed circuit board. A semiconductor device characterized in that a plurality of semiconductor devices are connected to the same pad and mounted on a printed circuit board in a stacked manner.
JP40181490A 1990-12-13 1990-12-13 Semiconductor device Pending JPH04214695A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP40181490A JPH04214695A (en) 1990-12-13 1990-12-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP40181490A JPH04214695A (en) 1990-12-13 1990-12-13 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04214695A true JPH04214695A (en) 1992-08-05

Family

ID=18511642

Family Applications (1)

Application Number Title Priority Date Filing Date
JP40181490A Pending JPH04214695A (en) 1990-12-13 1990-12-13 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04214695A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5420756A (en) * 1992-06-19 1995-05-30 Kabushiki Kaisha Toshiba Memory card including stacked semiconductor memory elements located on a printed circuit board having a straight wiring pattern
US5490041A (en) * 1993-11-15 1996-02-06 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit module and a semiconductor integrated circuit device stacking the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5420756A (en) * 1992-06-19 1995-05-30 Kabushiki Kaisha Toshiba Memory card including stacked semiconductor memory elements located on a printed circuit board having a straight wiring pattern
US5490041A (en) * 1993-11-15 1996-02-06 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit module and a semiconductor integrated circuit device stacking the same

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