JPH04212535A - Method of initial synchronization for spread spectrum communication system - Google Patents

Abstract

PURPOSE:To achieve initial synchronization by devising a method for transmitting information signals while paying attention to the point of spreading spectrum while loading the information signals to the offset of a self-traveling frequency. CONSTITUTION:For achieving the initial synchronization of a received PN signal at the delay lock loop(DLL) of a receiver, as a training data for a prescribed period before modulating the clock rate of the voltage controlled oscillator(VCO) of a transmitter by the information signal, a signal having a prescribed amplitude value is transmitted, frequency offset is applied to a clock and sliding correlation is executed at the DLL of the receiver so as to achieve the synchronization.

Description

[Detailed description of the invention]

0001

[Technical field] The present invention relates to spread spectrum
The present invention relates to a spread spectrum (SS) communication system, and more specifically, to a method for acquiring initial synchronization of a spread signal in a receiver for clock rate modulation spread spectrum communication in which information is transmitted by frequency modulating the clock rate of the spread signal. For example, it is applied to wireless communication and confidential communication.

0002

[Prior Art] Publicly known documents describing the prior art related to the present invention include, for example, DIXON, “SpreadSpe.
John Wiley
& Sons, pp. 116-117 and pp. 18
1-183 (1977). According to this document, as a clock rate modulation method, a system is described that realizes spread spectrum communication by frequency-modulating the clock of a pseudo-noise signal with an information signal and transmitting it. In order to acquire initial synchronization with the noise signal, the receiver's delay-locked loop (
By offsetting the free-running frequency of the voltage-controlled oscillator (VCO) used in the delay-locked loop (DLL),
A method is described in which synchronization is acquired by sliding the phase of the reference pseudo-noise signal ( ) and detecting the phase where the correlation value is maximum.

[0003] A receiver for clock rate modulation spread spectrum communication uses a phase synchronization circuit called a delay locked loop (DLL) to achieve phase synchronization with a received spread signal. The output range is narrow, and on the other hand, a delay-locked loop (DLL) voltage-controlled oscillator (VCO) is required for synchronous tracking.
) and the free-running frequency of the voltage controlled oscillator (VCO) of the transmitter are set to be equal, so an operation to acquire synchronization, so-called initial synchronization acquisition, is required. The simplest method for acquiring initial synchronization is called sliding correlation. For example, the free-running frequency of the receiver's voltage-controlled oscillator (VCO) is given a slight offset, and the correlation between the reference PN signal and the received PN signal is When the correlation value exceeds a certain threshold, it is assumed that synchronization has been achieved, and the offset of the free-running frequency of the voltage controlled oscillator (VCO) is set to 0 to perform synchronization tracking operation. It is.

However, when this method is applied to a clock rate modulation spread spectrum communication system, the circuits for acquiring initial synchronization such as a correlator, a comparator, and a voltage controlled oscillator (
This method requires a bias voltage changeover switch for the VCO (VCO), which complicates the circuitry and impairs the simplicity of the constituent circuitry, which is a feature of the clock rate modulation spread spectrum communication method.

[0005]

[Purpose] The present invention was made in view of the above-mentioned circumstances, and focuses on performing spectrum spreading by putting an information signal on the offset of the free-running frequency, and devises a way to send the information signal to achieve initial synchronization. In order to perform the acquisition, it is possible to acquire initial synchronization without complicating the circuit, and to use a signal in which the frequency offset at the start of training is set to 0 and the frequency offset increases in proportion to time for a certain period. The purpose of this study is to provide a method for acquiring initial synchronization in a spread spectrum communication system that eliminates system instability at the start of a training period.

[0006]

[Structure] In order to achieve the above objects, the present invention provides (1)
In a spread spectrum communication system that uses a pseudo-noise (PN) signal as a spread signal and frequency-modulates the clock rate of the spread signal with an information signal, initial synchronization of the received pseudo-noise signal in the delay-locked loop (DLL) of the receiver is performed. To obtain this, a signal with a predetermined amplitude value is transmitted as training data for a predetermined period before modulating the clock rate of the voltage controlled oscillator (VCO) of the transmitter with an information signal to impart a frequency offset to the clock. , performing a sliding correlation in the delay lock loop of the receiver to obtain synchronization; and (2) the signal having a predetermined amplitude value as the training data is a DC signal, a sawtooth signal, a triangular waveform, etc. (3) As the training data, the maximum amplitude ΔVt is taken at the start of transmission of the training data, and thereafter, ΔVt/Tt is taken in proportion to time.
transmitting a signal whose amplitude decreases at a rate of (Tt: training data transmission period) to give a frequency offset to the clock, and performing sliding correlation in a delay locked loop (DLL) of the receiver to obtain synchronization;
Furthermore, (4) as the training data, the amplitude ΔVt is 0 at the start of training data transmission, and after that,
In proportion to the time Tp during the training period, △Vt/T
The amplitude increases at a rate of p, and after Tp time from the start of training data transmission, ΔVt/(Tt-Tp
) (Tt: training data transmission period) to give a frequency offset to the clock by transmitting a signal whose amplitude decreases at a rate of Furthermore, (5) as the training data, the amplitude ΔVt is 0 at the start of training data transmission, and thereafter the amplitude increases at a rate of ΔVt/T1 in proportion to time;
From T1 time to T2 time, △Vt is maintained, and after T2 time, △Vt/(T3-T2
) to give the clock a frequency offset by transmitting a signal whose amplitude decreases at the rate of D
This method is characterized in that synchronization is obtained by performing sliding correlation in LL). Hereinafter, the present invention will be explained based on examples.

First, FIG. 2 is a block diagram for explaining an embodiment of a transmitter/receiver using a clock rate modulation spread spectrum communication system according to the present invention.
is the receiver. In the figure, 1 and 10 are adders, 2 and 11 are voltage controlled oscillators (VCO), and 3 and 9 are pseudo noise (PN).
A signal generator, 4 and 7 a frequency conversion section, 5 a power amplification section,
6 is an amplification section, 8 is a correlation network, 8a is a loop filter, and 12 is a delay locked loop (DLL). A voltage controlled oscillator 2 is modulated with the information signal S(t), and a PN signal subjected to clock rate modulation is transmitted via a PN signal generator 3, a frequency converter 4, and a power amplifier 5, and is amplified on the receiving side. 6 and a frequency converter 7, the correlation of the receiving side PN code is extracted as a demodulated signal using a delay locked loop (DLL) including a correlator network 8 and a loop filter 8a.

FIG. 3 is a diagram showing the configuration of a sliding correlator, in which 13 is a correlator, 14 is an absolute value circuit, and 15 is a correlator.
is a comparator, 16 is a switch, 17 is an adder, 18
is a voltage controlled oscillator (VCO), 19 is a pseudo noise (PN)
A signal generator, 20 a correlation network, and 20a a loop filter. This sliding correlator (sli
The ding correlator is the simplest implementation of correlation techniques, and its name comes from the synchronization process in which the receiving system's code sequence generator operates at a different speed than that of the transmitter. The relative phases between the transmitting and receiving code sequences shift, and when observed simultaneously (on an oscilloscope, for example), they shift past each other, and only come to rest when synchronization is achieved.

The advantage of the sliding correlator is its simplicity, requiring nothing more than some means of changing the receiver's code clock on command. The disadvantage of using a simple sliding correlator for synchronization is that if the instability is large, trying out all sign relationships is time consuming and impractical. To terminate the sliding or search process, it is necessary to identify that synchronization has been reached, the response time of which is limited by the bandwidth of the system's post-correlation receiver. Therefore, the speed of searching or sliding for all code phase offset positions is also limited by this bandwidth.

[0010] Typically, a voltage controlled oscillator (VCO) in a transmitter/receiver
) 18 is determined by the bias voltages Vtx and Vrx of the voltage controlled oscillator (VCO), and is set so that Vtx=Vrx. Therefore, at the receiver, PN
In order to obtain signal synchronization, the range within which the delay locked loop (DLL) of the receiver can track the PN signal, that is,
It is necessary to adjust the phase of either the transmitted or received signal so that the phase difference between the transmitted and received PN signals falls within the range of the delay discrimination characteristic. Establishing synchronization of the delay locked loop (DLL) by adjusting the phase in this manner is called initial synchronization acquisition. The simplest method is to apply an offset voltage △V to the voltage controlled oscillator (VCO) 18 of the receiver and give it an offset frequency △f.
The correlation with the received PN signal is taken by the correlator 13 while shifting the phase of the signal, and the signal is input to the comparator 15 via the absolute value circuit 14. When the correlation value in the comparator 15 reaches the maximum or a certain threshold value Vth The voltage controlled oscillator (VCO) outputs a synchronization acquisition signal when the
The applied voltage of 18 is switched by the switch 16 to return it to Vrx, and the tracking state is switched to a delay lock loop (DLL).

Clock rate modulation spread spectrum (SS)
) communication method differs from the normal direct spread method in that the control voltage of the voltage controlled oscillator (VCO) fluctuates according to the information signal;
They are the same in that initial synchronization acquisition is required to bring L) into a synchronous tracking state. However, even if the simplest sliding correlator is used, the circuit configuration becomes complicated, and the simplicity of the circuit configuration, which is a characteristic of the clock rate modulation spread spectrum (SS) communication system, is lost.

FIG. 1 is a diagram showing a transmission signal for explaining an initial synchronization acquisition method in a spread spectrum communication system according to the present invention. Period Tt for transmitting training data to obtain initial synchronization before transmitting data
will be established. As training data, a voltage ΔVt required to shift the free-running frequency fst of a transmission voltage controlled oscillator (VCO) by Δfst is transmitted. For this reason, T
During t, the free-running frequency of the voltage-controlled oscillator (VCO) of the transmitter is (fst+Δfst), which also differs from the free-running frequency of the voltage-controlled oscillator (VCO) of the receiver by Δfst.

As a result, it happens that at the start of training data transmission, the phase difference between the transmitted and received PN signals falls within the range of the delay discrimination characteristic of the delay locked loop (DLL) (for example, 2△
-2△<error time<2△, △ is the chip length of the PN signal), and unless synchronization is established,
The phase difference between the transmitted and received PN signals shifts over time,
This results in a so-called sliding correlation state. Then, due to the periodicity of the PN signal, the phase difference between the transmitted and received PN signals decreases after a certain period of time, and when the phase difference falls within the delay discrimination characteristic of the delay locked loop (DLL), the delay locked loop (DLL) enters a synchronous tracking state.

[0014] The condition for the size of △fst is |△fst|
<|DLL pull-in range|. The pull-in range of the delay-locked loop (DLL) is smaller than the lock range, so even if it is pulled in after training data transmission, synchronization is established, and training data transmission continues, the frequency offset △fst will be delayed-locked. Since it is within the lock range of the loop (DLL), the synchronized state is maintained. The training data transmission period Tt may be set to ensure that the phase slide occurs for one cycle of the PN signal with the lower chip rate. for example,
When Δfst is positive, Tt may be N·(1/Δfst).

[0015] When Δfst is small, Tt becomes long and it takes time to obtain initial synchronization. Therefore, Δfst is set to be as large as possible within the pull-in range. Ts is △fst-- after sending the training data
->0 (△Vt--->0) is the time to absorb the transient response of the delay-locked loop (DLL) caused by a step change in frequency, and is the closed-loop transfer function of the delay-locked loop (DLL). Depending on the frequency step response characteristic of , Ts may be set for only the time necessary until the loop can be considered to be in a steady state after Δfst--->0. This period also serves as a break between training data and actual data.

FIG. 4 is a diagram showing an embodiment of a circuit configuration for generating the training data and actual data in FIG. 1. In the figure, 21 is a counter, 22 is a clock signal source,
3 is a Ts time delay circuit, 24 is a data signal output section, 25
, 26 are switches. Simultaneously with the start of communication, a trigger signal is sent to the counter circuit and the counter 21 is reset. Further, the same signal turns on switch A in order to send out a DC signal ΔVt corresponding to training data. The counter 21 counts clock pulses for a time corresponding to the training period Tt, and generates a pulse when the counting is finished. This pulse signal turns off switch A and turns on switch B for sending out a data signal. Further, this signal passes through a delay circuit 23 that causes a delay of Ts time, and becomes an actual data transmission start signal to the data signal output section 24. Therefore, after the switch A is turned off, transmission of actual data is started after the time Ts has elapsed.

The above-mentioned method focuses on the fact that spread spectrum (SS) communication is performed by carrying an information signal on the offset of the free-running frequency, and the circuit is designed to acquire initial synchronization by devising a way to send the information signal. As a method for acquiring initial synchronization without complicating things, a DC signal of an appropriate size ΔVt is transmitted as training data for a certain appropriate period Tt after the start of communication, and the PN signal is transmitted only during Tt.
This is a method of obtaining synchronization by applying a frequency offset to the signal clock to perform sliding correlation in the delay locked loop (DLL) of the receiver.

However, in this method, the clock frequency changes in a step manner when the training data transmission ends.
The phase tracking operation of the receiver's delay-locked loop (DLL) is based on a frequency step change (frequency change △fs corresponding to △V).
t). To speed up synchronization acquisition, △fst is a delay-locked loop (DL
It is desirable to give as much as possible below the pull-in range of L), but at the same time, this also increases the overshoot of the phase error in the phase tracking operation of the delay locked loop (DLL) at the end of the training period, causing a delay before actual data transmission. The synchronization system of the lock loop (DLL) becomes unstable, or it takes a long time to settle down to a steady value.
It takes time from the start of communication to the start of actual data transmission.

From this point of view, by using a waveform signal as the training data signal, which takes the maximum amplitude ΔVt at the start of training, becomes 0 at the end of the training period, and whose amplitude decreases in proportion to time, There is also a method of stabilizing the system after initial synchronization is acquired until actual data transmission, and further shortening the time from the start of communication to the start of actual data transmission. However, with this method, if there is almost no phase difference between the reference PN signals of the delay-locked loop (DLL) at the start of the training period, a frequency offset equivalent to △Vt is instantaneously added at the start of the training period. The system becomes unstable due to the transient response of the synchronization system (DLL), and there is a possibility of failing to acquire synchronization, making it difficult to set the training period Tt. Such a case can be solved by other embodiments of the present invention as described below.

In FIG. 1, the training data transmission period Tt may be set to ensure that the phase slide occurs for one cycle of the PN signal (N chips). Therefore, T
As mentioned above, it is sufficient that t is N·(1/Δfst). If Δfst is small, Tt will be long, and it will take time to acquire initial synchronization. Therefore, Δfst is set to be as large as possible within the pull-in range. A receiver for transmission data as shown in Fig. 1 (Fig. 2(b)
The phase control signal (demodulation signal) S'(t) of the delay locked loop (DLL) after synchronization acquisition in ) is, for example, as shown in FIG.
become that way.

[0021] Ts is △fs after sending the training data
The delay locked loop (DL
L) is the time to absorb the transient response (Figure 5),
depends on the frequency step response characteristics and phase step response characteristics of the closed-loop transfer function of the delay-locked loop (DLL),
Ts may be set only for the time required until the loop can be considered to be in a steady state after Δfst--->0. This period also serves as a break between training data and actual data. However, if you try to increase the initial synchronization acquisition speed by increasing △fst, the delay-locked loop (DL
The overshoot of the control signal S'(t) of the system L) becomes large, and the system becomes unstable, so that it takes time for the system to reach a steady state, and Ts must be made longer. Therefore, it takes time from the start of communication to the start of actual data transmission.

FIG. 6 is a diagram showing other transmission data S(t) using training data, using a sawtooth signal whose amplitude decreases in proportion to time. In this case, the amplitude value △Vt of the training data signal at the start of the training data period is determined by the frequency offset △fst (△fst=K・△V
t, K: Sensitivity of voltage controlled oscillator (VCO) (Hz/V)
) must be less than or equal to the pull-in range of the delay-locked loop (DLL). Frequency offset △ due to training data signal t seconds after the start of the training period
fsc is; △fsc=(1-t/Tt)・△f
st, so the number of chips n that slides during the training period is;

[0023]

[Math 1]

Therefore, Tt is; Tt>(2N/△fst) Set to meet.

FIG. 8 is a block diagram for realizing the transmission of transmission data according to the present invention. In the figure, 51 is a counter A, 52 is a clock signal generation source, 53 is a data signal output section, 4 is a counter B, 55 is a D/A converter, 56 is a low pass filter (LPF), 57 is a variable gain amplifier, and 58 is a switch.

Counter A and counter B start simultaneously with the start of communication. The counter is the training period Tt
The counter B is a counter that provides a digital input signal in order to generate a pulse signal train of training data as shown in FIG. 9 from the D/A converter 55. The variable gain amplifier 57 is for setting the amplitude of training data. By appropriately selecting the clock frequency and the number of bits of the D/A converter 55 and adjusting the gain of the amplifier 57, a training data signal that decreases from ΔVt to 0 during the training period Tt is output as shown in FIG. can. Counter A is the time Tt
When the measurement is completed, a signal to start transmitting actual data is sent to the data output section, and a signal is also sent to the switch at the same time, so that the switch is switched from the training data generation side to the data signal output side. By this, Figure 6
The data signal of the present invention as shown in FIG.

Compared to the case where a rectangular signal as shown in FIG. It will double. However, in the method of the present invention, even if Δfs is set to the full pull-in range of the delay-locked loop (DLL), there is no transient phase fluctuation at the end of the training data period, and actual data transmission can be started immediately as shown in FIG. On the other hand, in the conventional method using a rectangular signal, the transient phase fluctuation becomes large as the signal is taken to the full pull-in range, and the time required for the system to reach a steady state becomes longer. The no-signal period Ts required before starting data transmission becomes long. Therefore, depending on the settings of each constant of the delay locked loop (DLL), Tt+Ts in FIG. 1 may be longer than Tt in FIG. 5. Furthermore, in the present invention, since there is no transient phase fluctuation due to frequency step response, actual data transmission can be started while maintaining a stable system state after initial synchronization is acquired.

However, as shown in FIG. 6, the training data takes the maximum amplitude ΔVt at the start of training data transmission and is instantaneously given a large frequency offset. If the phase of the received PN signal almost matches that of the received PN signal, and the synchronization system is about to be acquired, the synchronization system will become unstable due to the transient response of the system, and synchronization may be lost. have shortcomings.

FIG. 10 is a diagram showing still other transmission data S(t) using training data according to the present invention.
From 0 at the start of training until time Tp (△Vt/Tp
) and then decreases at a rate of (ΔVt(Tt-Tp)). Due to this,
Since there is no sudden frequency offset change not only at the end of the training period but also at the beginning of the training period, there is no possibility of failing to acquire synchronization when transmitting training data.

The time Tp during the training period is Tt>
It can be arbitrarily selected within the range of Tp>0. In addition, △Vt is the frequency offset △fst (△fst=K・△Vt, K: sensitivity (Hz/V) of the voltage controlled oscillator (VCO)) corresponding to △Vt, as in the methods of FIGS. 1 and 6. ) must be less than or equal to the pull-in range of the delay-locked loop (DLL). The frequency offset Δfsc due to the training data signal after t seconds from the start of the training period is;

0031
]

[Math 2]

Therefore, the number n of chips to slide during the training period is;

[0033]

[Math 3]

Therefore, Tt may be set to satisfy the following: Tt>(2N/Δfst). This condition is the same as in the case of FIG.

FIG. 11 is a diagram showing an embodiment of a circuit for realizing transmission data generation according to the present invention. In the figure, 31 is a counter, 32, 33, and 34 are flip-flops, 35 is a switch, and 36 is a clock signal. 37 is a frequency divider, 38 is an up/down counter, 39 is a D/A converter, 40 is a low pass filter (LPF), 41 is an amplifier, 42 is a data output circuit, and 43 is a switch.

Simultaneously with the start of transmission, the first switch 43 is set to training mode, and the counter 31 and up/down counter 38 start counting the reference clock signal. Here, the second switch 35 is turned on to the reference clock signal terminal when the output of the flip-flop (b) 34 is high, and is connected to a signal obtained by dividing the reference clock signal by N when it is low. Also, up-down counter 38 is set to function as an up-counter at the start of transmission. The counter 31 is for measuring the training periods Tp and Tt, and the up/down counter 38 is a counter for providing a digital input signal for generating a pulse train of training data as shown in FIG. 12 from the DA converter 39. be. The variable gain amplifier 41 is for setting the amplitude of training data.

The counter 31 is set at the beginning of the training period.
For the Tp time, the reference clock signal is counted for a period corresponding to Tp (count number NA=M). When I counted M,
A signal is sent from the counter 31 to the second switch 35, and the clock used for time measurement is switched from the reference clock to the N-divided clock. At the same time, a signal is sent to the up/down input of up/down counter 38, and counter 31 switches to a down counter. After time Tp, the counter 31 and the down counter will count using a clock signal with a frequency of 1/N of the reference clock, so for example, when N=2, 3Tp=Tt, as shown in FIG. A pulse train is obtained from the DA converter 39.

The pulse train as shown in FIG. 12 is applied to a low pass filter (LPF) 40 and transmitted as training data in the form of a triangular wave as shown in FIG. counter 31
sends a signal after 2M counts corresponding to time Tt,
The first switch 43 is switched to the data output mode, and at the same time, the data output circuit is turned on and communication of actual data is started. By selecting the frequency of the reference clock, the frequency division ratio N, and the count number M of the counter 31, arbitrary Tp and Tt can be set.

When a sawtooth signal as shown in FIG. 6 is used,
When using triangular wave signals, the minimum condition value of the training data transmission time is the same for each, but in the present invention, a sudden offset signal is not added at the start of training data transmission, so sliding correlation is performed gradually, so that the training period When acquiring synchronization of the received PN signal at the start of the process, an advantage is obtained that the delay locked loop (DLL) is less likely to fail to acquire synchronization.

The method described above is a method of removing instability of the system at the start of the training period by setting the frequency offset to 0 at the start of the training period and using a signal whose frequency offset increases in proportion to time for a certain period. It is. However, when using these triangular wave signals, the required training period is longer than when using rectangular wave signals. In such cases, by applying a frequency offset using a trapezoidal signal,
It is possible to make the training period shorter than when using a triangular wave signal, and to maintain the stability of the system after acquiring initial synchronization.

FIG. 13 is a diagram showing still another transmission data S(t) using training data according to the present invention.
0 at the start of training until time T1 (△Vt/T1
) increases in proportion to time, and then △V until T2
t, and from T2 to T3 △Vt/(T3-T2
). T1 and T2 are 0<T1<T2<
It can be arbitrarily selected within the range of T3. Similar to the other three examples, ΔVt must be set so that the frequency offset caused by ΔVt is less than or equal to the pull-in range of the delay locked loop (DLL).

[0042] Since the frequency offset is 0 at the end of the training period, the system that has acquired synchronization does not become unstable, and the same effect as when using a triangular wave signal is obtained. The frequency offset Δfsc due to the training data signal after t seconds from the start of the training period is;

0043
]

[Math 4]

Therefore, the number n of chips to slide during the training period is;

[0045]

[Math 5]

Since n must be greater than or equal to the period N of the PN signal, the conditions for the training period Tt (=T3) are;

[0047]

[Math 6]

[0048] Therefore, by setting T1, the time required for training can be made shorter by (T2-T1) than when using a triangular wave signal.

FIG. 14 is a diagram showing an embodiment of a circuit for realizing transmission data generation according to the present invention. In the figure, 61 is a counter, 62, 63, 64, and 65 are flip-flops, and 66 is an up/down counter. , 67 is a D/A converter, 68 is a low pass filter (LPF), 69 is an amplifier, 70 is a data output circuit, and 71 is a reference clock generator. At the same time as the transmission starts, the counter 61 and up/down counter 6
6 is reset and counting of the reference clock signal is started. At this time, the up/down counter 66 is set to an up-counting state. At the same time, the circuit output becomes the training signal output mode. The counter 61 is for measuring the training period Tt (=T3) and T1, T2, and outputs when the count number Kc=K1, K2, K3 corresponding to the time T1, T2, T3 is obtained. The up/down counter 66 is a counter for providing a digital input signal for generating a pulse train of training data as shown in FIG. 15 from the D/A converter 67. The linear variable gain amplifier 69 is for adjusting the amplitude of training data.

When the counter 61 counts K1 after starting training, it sends a signal to the enable input of the up/down counter 66 .
stops counting. Therefore, the D/A converter 67
The output value of is held. At this time, up and down
A signal is also sent to the up/down input of counter 66, causing up/down counter 66 to be switched from an up-counting state to a down-counting state. The counter 61 continues to count the reference clock signal and sends out the signal again when the count reaches K2. This signal returns the up-down counter 66 to the enabled state, and the up-down counter 66 now counts down.

Therefore, the output of the D/A converter 67, which was held until time T2, decreases as shown in FIG. The pulse signal train from the D/A converter 67 is LP
F68 and is transmitted as a trapezoidal training signal as shown in FIG. When the count number reaches K3, the counter 61 sends out a signal, and this signal turns off the reference clock signal output.At the same time, the output is switched from the training mode to the data output mode, and data signal transmission is started. By using a trapezoidal signal like the one used in the present invention, the frequency offset at the start and end of the training period can be set to 0, similar to the triangular waveform signal, making it possible to obtain initial synchronization while maintaining system stability. Instead, there is an advantage that the training period can be set shorter than when using a triangular wave signal.

[0052]

[Effects] As is clear from the above description, the present invention has the following effects. (1) When acquiring initial synchronization of a received PN signal in a clock rate modulation spread spectrum communication system, a signal that gives an appropriate frequency offset to a transmitted voltage controlled oscillator (VCO) is input as training data over a certain period of time to the transmitted signal. Therefore, the receive delay locked loop (D
By sliding the phase of the reference PN signal of LL),
Synchronization can be acquired, no special circuit is required, and the initial synchronization of the received PN signal can be achieved while maintaining the simplicity of the configuration, which is a feature of the clock rate modulation spread spectrum communication system. (2) When acquiring initial synchronization of the received PN signal in the clock rate modulation spread spectrum communication system, the amplitude of the transmitted signal is 0 at the start of the training data transmission as training data over a certain period Tt, and then,
The amplitude increases at a rate of △Vt/Tp over time Tp, and after time Tp, △Vt increases in proportion to time.
By using a signal that decreases at the rate of /(Tt-Tp), a frequency offset is given to the transmit voltage controlled oscillator (VCO), and the phase of the reference PN signal of the receive delay locked loop (DLL) is slid and synchronized. It is possible to obtain the initial synchronization of the received PN signal without requiring any special circuit, and while maintaining the simplicity of the configuration that is a feature of the clock rate modulation spread spectrum communication system. (3) When acquiring the initial synchronization of the received PN signal in the clock rate modulation spread spectrum communication system, the transmitted signal is used as training data over a certain time Tt.
The amplitude is 0 at the start of training data transmission, and then
The amplitude increases at a rate of △Vt/T1 in proportion to time, and T
△Vt is maintained from 1 hour to T2 hours, and after T2 hours, △Vt/(T3-T2) is proportional to time until T3 hours.
It is possible to acquire synchronization by transmitting a signal whose amplitude decreases at a rate of Therefore, it is possible to obtain initial synchronization of the received PN signal without requiring any special circuit and while maintaining the simplicity of the configuration that is a feature of the clock rate modulation spread spectrum communication system. (4) Frequency offset is 0 at the end of the training period
, the receiver is placed in a delay-locked loop (DLL).
) is kept in a steady state and can start transmitting real data immediately, but also after the start of the training period, the frequency offset gradually increases from 0, so it is not possible to give a sudden frequency offset change. This makes it possible to more reliably acquire initial synchronization within the set training period, while also making the training period shorter than before. (5) The present invention is particularly effective for obtaining initial synchronization when communicating using a stable transmission path where synchronization is unlikely to occur or when transmitting data in packet form.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a transmission signal for explaining an initial synchronization acquisition method in a spread spectrum communication system according to the present invention.

FIG. 2 is a configuration diagram of a transceiver using a clock rate modulation spread spectrum communication system.

FIG. 3 is a configuration diagram of a sliding correlator.

FIG. 4 is a diagram showing a circuit configuration for generating training data and actual data in FIG. 3;

FIG. 5 is a diagram showing a phase error signal due to a frequency offset in a training section.

FIG. 6 is a diagram showing other transmission data using training data.

7 is a diagram showing a phase error signal when using the transmission data shown in FIG. 6. FIG.

FIG. 8 is a diagram showing a circuit configuration for realizing generation of transmission data.

FIG. 9 is a diagram showing a pulse train of training data.

FIG. 10 is a diagram showing still other transmission data using training data.

FIG. 11 is a diagram showing another circuit configuration for realizing generation of transmission data.

FIG. 12 is a diagram showing another pulse train of training data.

FIG. 13 is a diagram showing still other transmission data using training data.

FIG. 14 is a diagram showing still another circuit configuration for realizing generation of transmission data.

FIG. 15 is a diagram showing still another pulse train of training data.

[Explanation of symbols]

1, 10... Adder, 2, 11... Voltage controlled oscillator (VCO
), 3, 9... Pseudo noise (PN) signal generator, 4, 7... Frequency converter, 5... Power amplifier, 6... Amplifier, 8... Correlation network, 8a... Loop filter, 12... Delay lock loop ( DLL).

Claims (5)

[Claims] Claim 1. In a spread spectrum communication system in which a pseudo noise (PN) signal is used as a spread signal and the clock rate of the spread signal is frequency modulated with an information signal, reception pseudo To obtain initial synchronization of the noise signal, a signal with a predetermined amplitude value is transmitted as training data for a predetermined period before modulating the clock rate of the voltage-controlled oscillator (VCO) of the transmitter with an information signal. A method for obtaining initial synchronization in a spread spectrum communication system, characterized in that a frequency offset is applied to the receiver, and synchronization is obtained by performing sliding correlation in a delay lock loop of the receiver. 2. The spread spectrum method according to claim 1, wherein the signal having a predetermined amplitude value as the training data is one of a DC signal, a sawtooth signal, a triangular wave signal, and a trapezoidal signal. Initial synchronization acquisition method in communication system. 3. The training data is a signal that takes a maximum amplitude ΔVt at the start of training data transmission and thereafter decreases in amplitude at a rate of ΔVt/Tt (Tt: training data transmission period) in proportion to time. Claim 1, characterized in that the clock is transmitted to give a frequency offset to the clock, and a sliding correlation is performed in a delay locked loop (DLL) of the receiver to obtain synchronization.
An initial synchronization acquisition method in the described spread spectrum communication method. 4. As the training data, the amplitude ΔVt is 0 at the start of training data transmission, and thereafter, the amplitude ΔVt/
The amplitude increases at a rate of Tp, and after Tp time from the start of training data transmission, ΔVt/(Tt-T
p) Transmit a signal whose amplitude decreases at the rate of (Tt: training data transmission period) to give a frequency offset to the clock, and perform sliding correlation in the delay lock loop (DLL) of the receiver to obtain synchronization. 2. The initial synchronization acquisition method in a spread spectrum communication system according to claim 1. 5. As the training data, the amplitude ΔVt is 0 at the start of transmission of the training data, and thereafter the amplitude increases at a rate of ΔVt/T1 in proportion to time,
From T1 time to T2 time, △Vt is maintained, and after T2 time, △Vt/(T3-T2
) to give the clock a frequency offset by transmitting a signal whose amplitude decreases at the rate of D
2. The initial synchronization acquisition method in a spread spectrum communication system according to claim 1, wherein synchronization is acquired by performing sliding correlation in LL).