JPH04212439A - Electronic circuit device - Google Patents
Electronic circuit deviceInfo
- Publication number
- JPH04212439A JPH04212439A JP6286991A JP6286991A JPH04212439A JP H04212439 A JPH04212439 A JP H04212439A JP 6286991 A JP6286991 A JP 6286991A JP 6286991 A JP6286991 A JP 6286991A JP H04212439 A JPH04212439 A JP H04212439A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- electronic circuit
- substrate
- circuit device
- strain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910000679 solder Inorganic materials 0.000 claims abstract description 76
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 238000007789 sealing Methods 0.000 claims abstract description 42
- 238000006073 displacement reaction Methods 0.000 claims description 2
- 239000000919 ceramic Substances 0.000 abstract description 33
- 238000010586 diagram Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 238000001465 metallisation Methods 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- 238000005219 brazing Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 230000004907 flux Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 239000011149 active material Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Landscapes
- Mounting Of Printed Circuit Boards And The Like (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、ＬＳＩなどを実装した
多層基板を封止した電子回路装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic circuit device in which a multilayer substrate on which LSIs and the like are mounted is sealed.
【０００２】0002
【従来の技術】電子回路装置を封止する目的は、１）多
層配線基板上のＬＳＩ、配線等を外部雰囲気と遮断し、
腐食、異物混入等を防ぐこと、
２）気密封止を行ない、内部を熱伝導性の良い不活性ガ
スで置換し、ＬＳＩからの発熱を外部へ伝達し、チップ
の冷却を図ることにある。[Prior Art] The purpose of sealing an electronic circuit device is to 1) isolate LSIs, wiring, etc. on a multilayer wiring board from the external atmosphere;
2) The purpose is to perform airtight sealing, replace the interior with an inert gas with good thermal conductivity, transmit heat from the LSI to the outside, and cool the chip.
【０００３】また、封止寿命としては、その電子回路装
置を使用した製品寿命以上が必要である。図２にＬＳＩ
を搭載した従来の封止構造の電子回路装置断面図を示す
。[0003] Furthermore, the sealing life must be longer than the life of the product using the electronic circuit device. Figure 2 shows the LSI
1 shows a cross-sectional view of an electronic circuit device with a conventional sealed structure equipped with the electronic circuit device.
【０００４】１は、セラミックス基板で、Ｗ，Ｍｏなど
の導体で配線層が形成されている多層基板である。４は
ＬＳＩチップでワイヤボンド、テープキャリア、ＣＣＢ
などの方法でセラミックス基板１の配線と接続されてい
る。３はセラミックス基板１にはんだ、ろう接続された
入出力ピンである。５は封止用の金属性キャップで、通
常４２Ａｌｌｏｙ（Ｆｅ−Ｎｉ４２％合金），コバール
などの材料が用いられている。このキャップ５はセラミ
ックス基板１の表面の周囲に施されたメタライズ２の上
に、ＡｕＳｎ、銀ろうなどによりろう付けされている。
また、同様な封止構造としては、ＮＩＫＫＥＩ ＥＬＥ
ＣＴＲＯＮＩＣＳ １９８４．３．２６ 第１７８頁か
ら１８４頁において論じられている。Reference numeral 1 denotes a ceramic substrate, which is a multilayer substrate on which wiring layers are formed of conductors such as W and Mo. 4 is an LSI chip with wire bond, tape carrier, and CCB.
It is connected to the wiring of the ceramic substrate 1 by the following methods. 3 is an input/output pin connected to the ceramic substrate 1 by soldering. Reference numeral 5 denotes a metal cap for sealing, which is usually made of a material such as 42Alloy (42% Fe-Ni alloy) or Kovar. This cap 5 is soldered onto the metallization 2 applied around the surface of the ceramic substrate 1 using AuSn, silver solder, or the like. Also, as a similar sealing structure, NIKKEI ELE
Discussed in CTRONICS 1984.3.26 pp. 178-184.
【０００５】[0005]
【発明が解決しようとする課題】上記従来技術には以下
のような問題点がある。封止部の接続寿命は、（１）Ｌ
ＳＩの消費電力、セラミックス基板上へのＬＳＩ搭載数
で決まる発熱量と、セラミックス基板、キャップ材、ろ
う材の各熱膨張係数αとセラミックス基板の大きさ等か
ら決まる。すなわち、ＬＳＩの発熱によりセラミックス
基板の温度がＴ１からＴ２に上昇すると、セラミックス
基板の熱膨張によりもとの長さｌに比べて図３に示すよ
うにΔｌ（Δｌ＝Δα・ΔＴ・ｌ）だけ膨張する。その
結果、金属性キャップ５の４２Ａｌｌｏｙより軟らかい
材質のろう材６及びキャップ５の主にコーナ部７に大き
な応力、ひずみを発生させる。そして、ＬＳＩのＯＮ／
ＯＦＦ動作により、この発生する応力、ひずみは繰り返
され、熱疲労寿命によりやがては、封止部に亀裂が入り
、その機能は失われる。すなわち、図２におけるセラミ
ックス基板が大きくなるほど、封止部への発生応力、ひ
ずみも大きくなり封止部の長寿命保証が出来なくなるの
である。[Problems to be Solved by the Invention] The above-mentioned prior art has the following problems. The connection life of the sealing part is (1)L
It is determined by the power consumption of the SI, the amount of heat generated by the number of LSIs mounted on the ceramic substrate, the coefficient of thermal expansion α of the ceramic substrate, the cap material, the brazing material, the size of the ceramic substrate, etc. In other words, when the temperature of the ceramic substrate rises from T1 to T2 due to the heat generated by the LSI, the thermal expansion of the ceramic substrate increases the length by Δl (Δl=Δα・ΔT・l) compared to the original length l, as shown in FIG. Expand. As a result, large stress and strain are generated mainly in the corner portion 7 of the cap 5 and the brazing filler metal 6, which is a softer material than the 42Alloy of the metal cap 5. Then, LSI ON/
Due to the OFF operation, the generated stress and strain are repeated, and due to thermal fatigue life, the sealing portion eventually cracks and loses its function. That is, as the ceramic substrate shown in FIG. 2 becomes larger, the stress and strain generated on the sealing section also increases, making it impossible to guarantee a long life of the sealing section.
【０００６】（２）キャップとセラミックス基板をはん
だ材で接続する際にフラックス（表面活性材）等を使用
するため、はんだ接続部断面形状が平型の場合にはフラ
ックスがはんだ外に逃げずらく、且つ一旦取り込まれる
と図４に示すようにはんだ内にボイド８が発生し易くな
り、このボイドが封止部の熱疲労寿命を低減させる。(2) Since flux (surface-active material) is used when connecting the cap and the ceramic substrate with a solder material, if the cross-sectional shape of the solder joint is flat, it is difficult for the flux to escape to the outside of the solder. , and once incorporated, voids 8 are likely to occur in the solder as shown in FIG. 4, and these voids reduce the thermal fatigue life of the sealing part.
【０００７】本発明の目的は、上記した従来技術の問題
点をなくし、多層基板を封止した電子回路装置の封止寿
命を十分に得られる装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide an apparatus which eliminates the problems of the prior art described above and which can provide a sufficient sealing life of an electronic circuit device in which a multilayer substrate is sealed.
【０００８】[0008]
【課題を解決するための手段】上記目的を達成するため
に、封止体を天板と側板に分けた。[Means for Solving the Problems] In order to achieve the above object, the sealed body is divided into a top plate and a side plate.
【０００９】また、封止体の端部断面形状を凸または、
円型とした。[0009] Also, the cross-sectional shape of the end of the sealing body may be convex or
It was circular.
【００１０】また、側板のはんだ接続部にメタライズを
施し、天板と側板、側板と多層配線基板間におけるはん
だ接続部において、天板、側板及び多層配線基板のいず
れかの四角より多層配線基板の辺長に対して約１５％以
上のところに支柱を設け、一定のはんだ接続高さにした
。[0010] Furthermore, metallization is applied to the solder joints on the side plates, and at the solder joints between the top plate and the side plates, and between the side plates and the multilayer wiring board, the multilayer wiring board is Supports were provided at approximately 15% or more of the side length to provide a constant solder connection height.
【００１１】[0011]
【作用】封止体を天板側と側板側に分けることにより、
封止体に複数のはんだ接続部を設けることが出来るので
、セラミックス基板の熱膨張により発生した応力、ひず
みの集中を複数のはんだ接続部でそれぞれ分散させるこ
とが出来る。[Operation] By dividing the sealing body into the top plate side and the side plate side,
Since the sealing body can be provided with a plurality of solder joints, the concentration of stress and strain caused by thermal expansion of the ceramic substrate can be dispersed at the plurality of solder joints.
【００１２】封止体の端部を凸状にすることにより、は
んだ接続部に発生するひずみを平型の端部より小さくす
ることが出来る。また、封止体の端部を凸状にすること
により、はんだ接続時にはんだ接続部に発生したボイド
を外部に排出することが出来る。By making the end portion of the sealing body convex, the strain generated in the solder connection portion can be made smaller than that at the flat end portion. Further, by making the end portion of the sealing body convex, voids generated in the solder connection portion during solder connection can be discharged to the outside.
【００１３】はんだ接続部に通常以上の高さを設けるこ
とにより、側板の支点位置をはんだ接続部の内部に移動
させることが出来、はんだ接続部での局部的な応力、ひ
ずみの発生を防ぐことが出来る。[0013] By providing the solder joint with a height higher than normal, the fulcrum position of the side plate can be moved inside the solder joint, thereby preventing the occurrence of local stress and strain at the solder joint. I can do it.
【００１４】また、はんだ接続部の高さを得るための支
柱を最大ひずみが発生する四角から避けることによって
、はんだ接続部の接続寿命を大幅に伸ばすことが出来る
。[0014] Furthermore, by avoiding the support for obtaining the height of the solder joint from the square where the maximum strain occurs, the connection life of the solder joint can be greatly extended.
【００１５】[0015]
【実施例】図１は本発明の一実施例に係る電子回路装置
の断面図である。図１において、１はセラミックス基板
、３は入出力ピン、４はＬＳＩ、９は封止用天板、１０
は封止用側板、６は天板９と側板１０及び側板１０とセ
ラミックス基板１を接続するためのはんだろう材、２は
はんだろう材接続を行なうためのメタライズ、１２はは
んだ接続高さを維持するための柱である。なお、柱１２
の接続位置は、セラミックス基板１の四角を除いたとこ
ろであればどこでも良い。また、図１３から図２１まで
は、はんだ接続高さを維持するための支柱を除いた場合
の封止用天板９、側板１０、セラミックス基板１、はん
だ６、メタライズ２の各部分より構成した封止部の一断
面形状を表した実施例である。図１３は、側板１０にお
けるはんだ接続部断面形状が上部が凸、下部が円型、図
１４は、側板１０におけるはんだ接続部断面形状が上部
が円型、下部が凸、図１５は、側板１０におけるはんだ
接続部断面形状が上部が円型、下部が円型、図１６は、
側板１０におけるはんだ接続部断面形状が上部が凸、下
部が平型、図１７は、側板１０におけるはんだ接続部断
面形状が上部が円型、下部が平型、図１８は、側板１０
におけるはんだ接続部断面形状が上部が平型、下部が凸
、図１９は、側板１０におけるはんだ接続部断面形状が
上部が平型、下部が円型、図２０は、側板１０における
はんだ接続部断面形状が上部が円型、下部が円型であり
、また、図２０は円型断面のうちはんだ接続部となる一
部分にメタライズ２を施した場合、図２１は、円型断面
の側面全体にメタライズ２を施し、はんだ６で側板１０
全体を覆ったような接続例である。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view of an electronic circuit device according to an embodiment of the present invention. In FIG. 1, 1 is a ceramic substrate, 3 is an input/output pin, 4 is an LSI, 9 is a sealing top plate, and 10
1 is a side plate for sealing, 6 is a soldering material for connecting the top plate 9 and the side plate 10, and the side plate 10 and the ceramic substrate 1, 2 is a metallization for connecting the soldering material, and 12 is for maintaining the solder connection height. It is a pillar for doing. In addition, pillar 12
The connection position may be anywhere other than the squares of the ceramic substrate 1. In addition, from FIG. 13 to FIG. 21, the sealing top plate 9, the side plate 10, the ceramic substrate 1, the solder 6, and the metallization 2 are shown when the support for maintaining the solder connection height is excluded. This is an example showing a cross-sectional shape of a sealing part. 13 shows that the cross-sectional shape of the solder joint on the side plate 10 is convex at the top and circular at the bottom. FIG. 14 shows that the cross-sectional shape of the solder joint on the side plate 10 is circular at the top and convex at the bottom. The cross-sectional shape of the solder connection part in FIG. 16 is circular at the top and circular at the bottom.
The cross-sectional shape of the solder joint on the side plate 10 is convex at the upper part and flat at the lower part. FIG.
The cross-sectional shape of the solder connection in the side plate 10 is flat at the top and convex at the bottom. FIG. The shape is circular at the top and circular at the bottom, and Fig. 20 shows a case where metallization 2 is applied to a part of the circular cross section that will become the solder connection part, and Fig. 21 shows metallization on the entire side of the circular cross section. 2 and solder 6 to the side plate 10.
This is an example of a connection that covers the entire area.
【００１６】以上述べた装置の動作説明について説明す
る。まず、ＬＳＩ４の動作による発熱がセラミックス基
板１に伝達され、セラミックス基板１に熱膨張が発生す
る。この際に発生した応力、ひずみは、はんだ６、側板
１０、天板９へ加わるが、はんだ接続部をセラミックス
基板１−側板１０、側板１０−天板９の２ヵ所に分割し
てあるので、各はんだ接続部に発生する応力、ひずみを
各はんだ接続部に分散させることが出来る。また、セラ
ミックス基板１−側板１０、側板１０−天板９間を接続
するはんだ６で、一定の接続高さを設けることによって
各々のはんだ６の内部で発生する応力、ひずみを低減す
ることが出来る。つまり、側板１０とセラミックス基板
１及び天板９と側板１０におけるはんだ接続高さ（隙間
）がないと、図６に示すようにセラミックス基板１の熱
膨張に対し、側板１０の底部１１が支点となるため、は
んだ６に対して局部的に大きな応力、ひずみを発生させ
る。そこで、図５に示すように側板１０のはんだ接続部
にメタライズ２を施し、接続用はんだ６で一定の接続高
さｈを維持することによって、セラミックス基板１の熱
膨張に対する、側板１０の支点位置をはんだ内部まで移
動させ局部的な応力、ひずみの発生を防ぐことが出来る
。なお、天板９と側板１０のはんだ接続部に対しても接
続高さｈを設けることにより同様の作用が働く。また、
通常の状態では、はんだ接続高さは天板９、側板１０の
自重により、数μｍ程度になるので、スペーサー、支柱
１２等の支持体をはんだ接続内部に設けることによって
、一定の接続高さｈを取る必要がある。ｈを求めるには
、はんだ内のせん断ひずみをγ、セラミックス基板１の
変位をΔｌとすると近似的にγ＝Δｌ／ｈの関係式が成
立ち、γとはんだ破断寿命の関係は実験結果より図７の
様に示され、γ＝１％付近に破断寿命の変曲点が存在す
ることが分かっている。よって、Δｌ／ｈ＝γ≦１％を
満足するようなｈを求めれば良い。また、セラミックス
基板１のコーナから支持体の取付け位置までの距離をｍ
とし、ｍとセラミックス基板１の辺長に対する比率をＰ
とした場合、Ｐとはんだ破断寿命の関係は、実験的に図
８の様に示され、Ｐ＝１５％付近にはんだ破断寿命の変
曲点があり、支持体取付け位置ｍは、セラミックス基板
１の辺長をｌとするとｍ≧０．１５・ｌの関係になけれ
ばならない。The operation of the apparatus described above will now be explained. First, heat generated by the operation of the LSI 4 is transmitted to the ceramic substrate 1, causing thermal expansion in the ceramic substrate 1. The stress and strain generated at this time are applied to the solder 6, side plate 10, and top plate 9, but since the solder connection part is divided into two parts: ceramic substrate 1 - side plate 10, and side plate 10 - top plate 9, Stress and strain generated in each solder connection can be dispersed to each solder connection. Furthermore, by providing a certain connection height for the solder 6 that connects the ceramic substrate 1 to the side plate 10 and the side plate 10 to the top plate 9, stress and strain generated inside each solder 6 can be reduced. . In other words, if there is no solder connection height (gap) between the side plate 10 and the ceramic substrate 1 and between the top plate 9 and the side plate 10, the bottom 11 of the side plate 10 will act as a fulcrum for thermal expansion of the ceramic substrate 1, as shown in FIG. Therefore, large stress and strain are generated locally in the solder 6. Therefore, as shown in FIG. 5, by applying metallization 2 to the solder connection part of the side plate 10 and maintaining a constant connection height h with the connecting solder 6, the fulcrum position of the side plate 10 with respect to the thermal expansion of the ceramic substrate 1 is can be moved inside the solder to prevent localized stress and strain from occurring. Incidentally, by providing the connection height h to the solder connection portion between the top plate 9 and the side plate 10, a similar effect is exerted. Also,
Under normal conditions, the solder connection height is approximately several micrometers due to the weight of the top plate 9 and side plate 10, so by providing supports such as spacers and pillars 12 inside the solder connection, a certain connection height h can be maintained. need to take. To find h, if the shear strain in the solder is γ and the displacement of the ceramic substrate 1 is Δl, the relational expression γ = Δl/h is approximately established, and the relationship between γ and solder rupture life is shown in the figure from the experimental results. 7, and it is known that there is an inflection point in the rupture life around γ=1%. Therefore, it is sufficient to find h that satisfies Δl/h=γ≦1%. Also, the distance from the corner of the ceramic substrate 1 to the mounting position of the support body is m.
and the ratio of m to the side length of the ceramic substrate 1 is P
In this case, the relationship between P and solder rupture life is experimentally shown as shown in FIG. Let the side length of be l, then there must be a relationship of m≧0.15·l.
【００１７】また、側板１０のはんだ接続部の上下もし
くは一方の断面形状を凸または円型にすることによって
、はんだ内でのボイド発生量及び発生ひずみ量を低減さ
せることが出来る。これは、図１０に示すように、側板
１０のはんだ接続部断面形状を凸−平型とし、３次元熱
弾塑性解析を行ない、両接続部はんだ内で発生するひず
みをシミュレーションした結果、凸形状の方が平型に比
べ発生する相当ひずみが小さくなるからである。シミュ
レーションに使用した温度データを図１１に示すが、温
度範囲を−２５〜１５０℃として解析した。また図１１
は１５０℃における両接続箇所のはんだ断面において発
生する相当ひずみについて解析した分布図である。はん
だの熱疲労寿命を検討するパラメータの１つに最大相当
ひずみ値が有り、図１２（ａ）の凸形状では最大相当ひ
ずみが３．６％、（ｂ）の平型形状では最大相当ひずみ
が４．６％となり、接続形状がはんだ内発生ひずみに与
える効果として約２２％（（４．６−３．６）／４．６
）の低減がなされることが分かった。なお、シミュレー
ションに使用した各構成材料は、図１０において天板９
と多層基板１をセラミックス、側板１０を４２Ａｌｌｏ
ｙ、はんだ６をＳｎ−３７Ｐｂとして計算した。Furthermore, by making the cross-sectional shape of the upper and lower sides or one side of the solder connection portion of the side plate 10 convex or circular, the amount of voids and strain generated in the solder can be reduced. As shown in FIG. 10, the cross-sectional shape of the solder connection part of the side plate 10 is made into a convex-flat shape, and a three-dimensional thermoelastic-plastic analysis is performed to simulate the strain occurring in the solder of both connections. This is because the equivalent strain that occurs is smaller when compared to the flat type. The temperature data used in the simulation is shown in FIG. 11, and the temperature range was -25 to 150°C. Also, Figure 11
is a distribution diagram showing an analysis of the equivalent strain occurring in the solder cross section of both connection points at 150°C. One of the parameters for examining the thermal fatigue life of solder is the maximum equivalent strain value, and the maximum equivalent strain is 3.6% for the convex shape shown in Fig. 12 (a), and the maximum equivalent strain is 3.6% for the flat shape shown in Fig. 12 (b). The effect of the connection shape on the strain generated in the solder is approximately 22% ((4.6-3.6)/4.6
) was found to be reduced. In addition, each component material used in the simulation is the top plate 9 in FIG.
The multilayer substrate 1 is made of ceramic, and the side plate 10 is made of 42Allo.
y, calculated assuming that solder 6 is Sn-37Pb.
【００１８】また、接続用はんだ内部に発生するボイド
の低減方法としては、図９（ａ），（ｂ）に示す様に側
板１０のはんだ接続部の断面形状を凸１２（（ａ）図）
または円型（（ｂ）図）にすることによって、はんだ接
続時に発生したボイド８を外部に排出することが出来る
ものである。In addition, as a method for reducing voids generated inside the solder for connection, as shown in FIGS.
Alternatively, by making it circular (see figure (b)), voids 8 generated during solder connection can be discharged to the outside.
【００１９】以上述べたように、本実施例によれば、キ
ャップ構造の変更、はんだの上下２段接続、はんだ接続
高さの制御を行なうことによって、セラミックス基板の
熱膨張により発生した応力、ひずみを分散させ、また、
はんだ内ボイド発生量を低減でき、熱疲労による封止寿
命を大幅に伸ばすことが出来る。As described above, according to this embodiment, the stress and strain caused by thermal expansion of the ceramic substrate can be reduced by changing the cap structure, connecting the upper and lower solder layers, and controlling the solder connection height. and also,
The amount of voids generated in the solder can be reduced, and the life of the seal due to thermal fatigue can be significantly extended.
【００２０】[0020]
【発明の効果】本発明によれば、セラミックス基板の熱
膨張によるはんだ部、封止キャップへの発生応力、ひず
みを分散、減少させることが出来、また、はんだ内ボイ
ド発生量を低減させることにより、はんだ接続部におけ
る封止信頼性を向上させ、封止寿命を大幅に伸ばすこと
が出来る。[Effects of the Invention] According to the present invention, it is possible to disperse and reduce the stress and strain generated on the solder portion and the sealing cap due to thermal expansion of the ceramic substrate, and also by reducing the amount of voids generated in the solder. , it is possible to improve the sealing reliability at solder joints and significantly extend the sealing life.
【図１】本発明を適用した電子回路装置の断面図である
。FIG. 1 is a sectional view of an electronic circuit device to which the present invention is applied.
【図２】従来の電子回路装置の断面図である。FIG. 2 is a cross-sectional view of a conventional electronic circuit device.
【図３】ＬＳＩチップの発熱によりセラミックス基板が
Δｌだけ膨張した状態を示す断面図である。FIG. 3 is a cross-sectional view showing a state in which the ceramic substrate is expanded by Δl due to heat generated by the LSI chip.
【図４】はんだ接続部に発生したボイドを示す図である
。FIG. 4 is a diagram showing voids generated in a solder connection.
【図５】はんだ接続高さを設けた電子回路装置の断面図
である。FIG. 5 is a sectional view of an electronic circuit device with solder connection heights;
【図６】封止体に応力、ひずみが発生した場合の変形図
である。FIG. 6 is a deformation diagram when stress and strain occur in the sealed body.
【図７】せん断ひずみとはんだ破断寿命の関係図である
。FIG. 7 is a diagram showing the relationship between shear strain and solder rupture life.
【図８】支持体取付け位置とはんだ破断寿命の関係図で
ある。FIG. 8 is a diagram showing the relationship between support mounting position and solder breakage life.
【図９】ボイドの排出状態を示す図である。FIG. 9 is a diagram showing a void discharge state.
【図１０】シミュレーションに使用した電子回路装置の
一部分の断面図である。FIG. 10 is a cross-sectional view of a portion of the electronic circuit device used in the simulation.
【図１１】シミュレーションに使用した温度データ図で
ある。FIG. 11 is a diagram of temperature data used in simulation.
【図１２】相当ひずみ分布図である。FIG. 12 is an equivalent strain distribution diagram.
【図１３】本発明の一実施例に係る封止構造からなる電
子回路装置の断面図である。FIG. 13 is a sectional view of an electronic circuit device having a sealing structure according to an embodiment of the present invention.
【図１４】本発明の一実施例に係る封止構造からなる電
子回路装置の断面図である。FIG. 14 is a sectional view of an electronic circuit device having a sealing structure according to an embodiment of the present invention.
【図１５】本発明の一実施例に係る封止構造からなる電
子回路装置の断面図である。FIG. 15 is a sectional view of an electronic circuit device having a sealing structure according to an embodiment of the present invention.
【図１６】本発明の一実施例に係る封止構造からなる電
子回路装置の断面図である。FIG. 16 is a sectional view of an electronic circuit device having a sealing structure according to an embodiment of the present invention.
【図１７】本発明の一実施例に係る封止構造からなる電
子回路装置の断面図である。FIG. 17 is a sectional view of an electronic circuit device having a sealing structure according to an embodiment of the present invention.
【図１８】本発明の一実施例に係る封止構造からなる電
子回路装置の断面図である。FIG. 18 is a sectional view of an electronic circuit device having a sealing structure according to an embodiment of the present invention.
【図１９】本発明の一実施例に係る封止構造からなる電
子回路装置の断面図である。FIG. 19 is a sectional view of an electronic circuit device having a sealing structure according to an embodiment of the present invention.
【図２０】本発明の一実施例に係る封止構造からなる電
子回路装置の断面図である。FIG. 20 is a sectional view of an electronic circuit device having a sealing structure according to an embodiment of the present invention.
【図２１】本発明の一実施例に係る封止構造からなる電
子回路装置の断面図である。FIG. 21 is a sectional view of an electronic circuit device having a sealing structure according to an embodiment of the present invention.
１…セラミックス基板、２…メタライズ、４…ＬＳＩ、
６…はんだ、ろう材、９…天板、１０…側板、１２…支
柱。1... Ceramic substrate, 2... Metallization, 4... LSI,
6... Solder, brazing metal, 9... Top plate, 10... Side plate, 12... Support.
Claims (4)
と、該電子回路部品を該基板上に封止するための封止体
とを有する電子回路装置において、第１のはんだ接続部
を介して該基板に接続される枠状の第１の封止体と、第
２のはんだ接続部を介して該第１の封止体に蓋をするよ
うに該第１の封止体に接続される第２の封止体とから上
記封止体がなることを特徴とする電子回路装置。1. An electronic circuit device comprising a substrate, an electronic circuit component mounted on the substrate, and a sealing body for sealing the electronic circuit component on the substrate, wherein a first solder connection portion is provided. a frame-shaped first sealing body connected to the substrate via a second solder connection portion; An electronic circuit device characterized in that the sealed body is made up of a second sealed body to be connected.
と、該電子回路部品を該基板上に封止するための封止体
とを有する電子回路装置において、該封止体の端部が凸
状であることを特徴とする電子回路装置。2. An electronic circuit device comprising a substrate, an electronic circuit component mounted on the substrate, and a sealing body for sealing the electronic circuit component on the substrate, wherein an edge of the sealing body is provided. An electronic circuit device characterized by having a convex portion.
が凸状であることを特徴とする請求項１記載の電子回路
装置。3. The electronic circuit device according to claim 1, wherein at least one end of said first sealing body is convex.
みをγ、該基板の変位をΔｌとすると、Δｌ／ｈ＝γ≦
１％を満たし、この高さｈを維持するための支持手段を
設けると共に、該支持手段を該基板上、第１、第２の封
止体のいずれかの四角より該基板の辺長に対して１５％
以上のところに有することを特徴とする請求項１または
２記載の電子回路装置。4. The height h of the solder joint is defined as Δl/h=γ≦, where γ is the shear strain and Δl is the displacement of the substrate.
1%, and provide support means to maintain this height h, and also install the support means from any square of the first or second sealing body on the substrate with respect to the side length of the substrate. 15%
The electronic circuit device according to claim 1 or 2, characterized in that it has the above features.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3062869A JP3033221B2 (en) | 1990-03-30 | 1991-03-27 | Electronic circuit device |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2-80712 | 1990-03-30 | ||
| JP8071290 | 1990-03-30 | ||
| JP3062869A JP3033221B2 (en) | 1990-03-30 | 1991-03-27 | Electronic circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04212439A true JPH04212439A (en) | 1992-08-04 |
| JP3033221B2 JP3033221B2 (en) | 2000-04-17 |
Family
ID=26403927
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3062869A Expired - Fee Related JP3033221B2 (en) | 1990-03-30 | 1991-03-27 | Electronic circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3033221B2 (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003017604A (en) * | 2001-06-28 | 2003-01-17 | Kyocera Corp | Package for housing semiconductor element and semiconductor device |
| JP2008016471A (en) * | 2006-07-03 | 2008-01-24 | Sony Corp | Function element, module and electronic equipment equipped therewith, and electronic device |
| JP2008235531A (en) * | 2007-03-20 | 2008-10-02 | Mitsubishi Electric Corp | Package for hermetic sealing, and connection structure |
| JP2009193986A (en) * | 2008-02-12 | 2009-08-27 | Sony Corp | Semiconductor device and method for manufacturing the same |
| JP2010129726A (en) * | 2008-11-27 | 2010-06-10 | Kyocera Corp | Electronic component housing package, electronic apparatus, and method of manufacturing the same |
| JP2011228591A (en) * | 2010-04-22 | 2011-11-10 | Kyocera Corp | Element housing package and electronic device equipped with the same |
| US9123928B2 (en) | 2011-05-27 | 2015-09-01 | Nec Corporation | Method for doping and dedoping lithium into and from negative electrode and method for producing negative electrode for lithium secondary battery |
| WO2020149188A1 (en) * | 2019-01-17 | 2020-07-23 | 三菱電機株式会社 | Semiconductor device and method for manufacturing semiconductor device |
-
1991
- 1991-03-27 JP JP3062869A patent/JP3033221B2/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003017604A (en) * | 2001-06-28 | 2003-01-17 | Kyocera Corp | Package for housing semiconductor element and semiconductor device |
| JP2008016471A (en) * | 2006-07-03 | 2008-01-24 | Sony Corp | Function element, module and electronic equipment equipped therewith, and electronic device |
| JP2008235531A (en) * | 2007-03-20 | 2008-10-02 | Mitsubishi Electric Corp | Package for hermetic sealing, and connection structure |
| JP2009193986A (en) * | 2008-02-12 | 2009-08-27 | Sony Corp | Semiconductor device and method for manufacturing the same |
| JP2010129726A (en) * | 2008-11-27 | 2010-06-10 | Kyocera Corp | Electronic component housing package, electronic apparatus, and method of manufacturing the same |
| JP2011228591A (en) * | 2010-04-22 | 2011-11-10 | Kyocera Corp | Element housing package and electronic device equipped with the same |
| US9123928B2 (en) | 2011-05-27 | 2015-09-01 | Nec Corporation | Method for doping and dedoping lithium into and from negative electrode and method for producing negative electrode for lithium secondary battery |
| WO2020149188A1 (en) * | 2019-01-17 | 2020-07-23 | 三菱電機株式会社 | Semiconductor device and method for manufacturing semiconductor device |
| JPWO2020149188A1 (en) * | 2019-01-17 | 2021-09-30 | 三菱電機株式会社 | Semiconductor devices and manufacturing methods for semiconductor devices |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3033221B2 (en) | 2000-04-17 |
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