JPH04211873A - Automatic wiring processing method - Google Patents

Abstract

PURPOSE:To shorten processing time for wiring processing by additionally registering the wiring path pattern and its outer periphery as a wiring prohibition area to a wiring prohibition list every time the wiring processing for one network is finished and using a wiring prohibition list at the next wiring processing. CONSTITUTION:The occupancy of the length of the wiring pattern from the center coordinates to respective up-down and right-left directions based on the wiring width of the network. The wiring pattern is expanded corresponding to each wiring width after the wiring processing to be additionally registered in a wiring prohibition map as the wiring prohibition area. In the next wiring processing, the wiring processing is performed by using the wiring prohibition map corresponding to the wiring width of the network for wiring. That is, when the wiring paths of terminals T5 and T6 are retrieved by using the wiring prohibition map, a wiring path L56 is obtained to complete the wiring processing of the network.

Description

[Detailed description of the invention]

[Object of the invention]

0002

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic wiring processing method for automatically processing wiring of semiconductor devices, printed circuit boards, etc. using a plurality of different wiring widths.

0003

2. Description of the Related Art In recent years, in order to satisfy the demands for higher density and higher speed for semiconductor devices, progress has been made in making the wiring width of wiring patterns smaller in layout design.

However, as the wiring width becomes finer and thinner, the resistance of the wiring increases and the signal propagation delay increases. This makes it difficult to operate at high speeds, which goes against the grain from the viewpoint of speeding up.

[0005] Therefore, in order to maintain high-speed operation, it is conceivable to raise the operating potential. however,
When the operating power is increased, the power consumption increases and the amount of heat generated also increases, which requires cooling to suppress this.

[0006] Therefore, research is being conducted to manipulate and adjust the wiring resistance by partially changing the wiring width without increasing the operating potential.

As described above, the conventional wiring processing method for wiring with multiple wiring widths is to classify nets connecting wiring terminals into groups according to wiring width, and change the wiring width for each group. However, there is a method of processing the wiring in stages for each group.

[0008] In such a method, the wiring order can only be changed within nets classified into the same wiring width, and it is difficult to optimize the wiring order for all nets. there were. Furthermore, since the wiring width is changed for each group classified by each wiring width, it is necessary to change settings such as wiring conditions. However, such processing is complicated and has the disadvantage of increasing processing time.

On the other hand, other conventional wiring processing methods include:
It is disclosed in Japanese Patent Application Laid-Open No. 1-179432, and FIG.
As shown in the process step 8, the wiring prohibited area and the existing wiring pattern are expanded according to the wiring width of the net for which wiring processing is to be performed, and these areas are registered as wiring prohibited areas and wiring processing is performed. In this method, the procedure of canceling the registered wiring prohibited area after processing is repeated for each wiring of each net.

[0010] In such a method, compared to the above-described method, the wiring order can be optimized regardless of the wiring width. However, the wiring prohibited area is registered and canceled for each net to be routed. For this reason,
When the number of existing wiring patterns increases, it takes time to register and cancel wiring prohibited areas.
This increases the overall wiring processing time.

[0011]

[Problem to be solved by the invention] As explained above,
In conventional wiring processing methods that perform wiring processing using different wiring widths, all of the above-mentioned methods have resulted in the problem that the wiring processing time increases.

The present invention has been made in view of the above, and an object thereof is to provide an automatic wiring processing method that reduces the wiring processing time.

[Configuration of the invention]

[0014]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a first method for determining, for each wiring width, an expansion distance corresponding to each wiring width used in wiring processing.
a second process of creating a wiring prohibition list for each wiring width in which wiring prohibition areas are registered; and a second process of creating a wiring prohibition list in which wiring prohibition areas are registered for each wiring width; A third process of registering the area enlarged by the enlarged distance as a wiring prohibition area corresponding to each wiring width in the corresponding wiring prohibition list created in the second process, and selecting a net to be subjected to wiring processing. Then, the wiring prohibition list corresponding to the wiring width of the selected net is added to the third
a fourth process of extracting from the wiring prohibition list created in the process; and a fourth process of extracting a wiring prohibition area that is selected in the fourth process outside the wiring prohibition area registered in the wiring prohibition list extracted in the fourth process. a fifth process for determining a net wiring route pattern; a sixth process for registering the wiring route pattern obtained in the fifth process in an output list; and a wiring route pattern obtained in the fifth process. and a seventh process of additionally registering an area whose outer periphery is expanded by each enlarged distance obtained in the first process as a wiring prohibition area corresponding to each wiring width to a corresponding wiring prohibition list, and a wiring process. and an eighth process in which the fourth to seventh processes are performed on all the nets to be processed.

The present invention also provides a first process of creating a plurality of wiring prohibition lists for each wiring condition in which wiring prohibition areas are registered, and selecting a net to be routed and applying the wiring condition to the selected net. a second process of extracting a corresponding wiring prohibition list from the wiring prohibition list created in the first process; and a second process of extracting a corresponding wiring prohibition list from the wiring prohibition list created in the first process; A third step of searching and determining the wiring route pattern of the net selected in the second process.
a fourth process of extracting a net to search for and determine a wiring route pattern next when there is an unrouted net, and setting the wiring route pattern obtained in the third process as a wiring prohibited area. a fifth process of registering in a wiring prohibition list corresponding to the wiring condition of the net extracted in the fourth process; and a fifth process that uses the wiring route pattern obtained in the third process as a wiring prohibition area. A sixth process starts and executes the process of registering in all the wiring prohibition lists other than the wiring prohibition list registered in the above wiring prohibition list in parallel with the fifth process by multiple processing units, and the sixth process starts and executes the process of registering in all the wiring prohibition lists other than the wiring prohibition list registered in On the other hand, the seventh process includes a seventh process in which the second process to the sixth process are repeatedly performed.

[0016]

[Operation] In the above process, each time the wiring process for one net is completed, the area in which the obtained wiring path pattern and its outer periphery are expanded by the expansion distance determined respectively in accordance with the wiring width, The area is additionally registered as a wiring prohibition area in the wiring prohibition list corresponding to each wiring width, and the next wiring process is performed using the wiring prohibition list corresponding to the wiring width used for that net.

[0017] Further, the present invention provides a process in which, after the wiring route pattern of a net is searched and determined, the wiring route pattern is registered as a wiring prohibited area in the wiring prohibited list corresponding to the net to be routed next. Then, a plurality of processing units perform the process of registering in all wiring prohibition lists other than the above-mentioned wiring prohibition list.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the drawings.

FIG. 1 is a flowchart showing the processing procedure of an automatic wiring processing method according to an embodiment of the present invention. The feature of the embodiment shown in the figure is that, compared to the latter of the conventional examples described above, only the additional registration of wiring prohibition data corresponding to the wiring pattern newly obtained after the wiring processing of one net is performed. Therefore, the processing procedure of this embodiment will be explained below with reference to FIG.

In FIG. 1, first check all the wiring widths used for all the nets to be processed, and for each wiring width, determine how far the wiring pattern is from the center grid of the wiring lattice in the grid wiring, up, down, left and right. It is determined whether there is a length of , and the number of occupied lattices (hereinafter referred to as "expanded lattice number") is determined (step S1).

Next, in the net wiring process, a list (hereinafter referred to as a "routing prohibition map") for registering wiring prohibition data indicating a wiring prohibition area in units of wiring grids is created using all the wiring checked in step S1. It is created for each width (step S2).

Next, the outer periphery of the preset wiring prohibited area within the net wiring area is expanded by the number of expanded grids corresponding to each wiring width determined in step S1 above. Therefore, the number of wiring prohibition areas whose outer periphery is expanded by the number of expanded grids is created in the same number as the types of wiring widths used for wiring processing. Each of the created wiring prohibition areas is registered in the wiring prohibition map corresponding to each wiring width created in step 2 above in grid units as wiring prohibition area data (step S3).

In this way, the preparation for wiring processing is completed through the processing procedure of steps S1 to S3, and the wiring processing for each net is started.

First, a net to be routed is selected from among all the nets (step S4), the wiring width to be used for the wiring processing of the selected net is checked, and a wiring prohibition map corresponding to the checked wiring width is created. Select (step S5)
.

Next, the wiring route of the selected net is searched for using the wiring prohibition map selected in step S5. That is, the net wiring process is performed on the wiring grid, excluding the wiring prohibited area represented by the data registered in the wiring prohibited map (step S6).
.

Next, the wiring pattern of the wiring route obtained in step S6 is registered in the output list (step S6).
7).

Next, the outer periphery of the wiring pattern obtained in step S6 above is expanded by the number of enlarged grids corresponding to the respective wiring widths obtained in step 1 above. therefore,
The same number of wiring patterns as the types of wiring widths to be used are created by enlarging the outer periphery of the wiring pattern obtained in step S6. Each wiring pattern whose outer periphery has been enlarged is registered in the corresponding wiring prohibition map as a wiring prohibition area in grid units (step S8).

Next, it is determined whether or not there is a net that has not been routed (step S9), and if there is, the processing flow returns to step S4, and the net that has not been routed is routed to step S4. - Wiring processing is performed according to the processing procedure of step S8. In this manner, when the wiring processing for all nets is completed, the wiring processing procedure shown in this embodiment is completed.

Next, a specific example of wiring processed according to the processing procedure shown in FIG. 1 will be described with reference to FIGS. 2 to 4.

The terminals T1 to T6 to be wired are
As shown in Fig. 2, the wires are placed on a wiring grid set as shown by dotted lines within the wiring area surrounded by solid lines, and the area shown with diagonal lines is the wiring grid that is set in advance within the wiring area. This is a prohibited area for wiring.

In such arrangement of terminals T1 to T6, terminal T1 and terminal T2 are wired with wiring width W1, and terminal T3 is wired with wiring width W1.
and terminal T4 are wired with wiring width W2, and terminal T5 and terminal T6 are wired with wiring width W2.
It is assumed that grid wiring processing is performed with a wiring width W1, and the wiring is performed in the order described above. For ease of understanding, it is assumed that only one wiring layer is used, and the spacing of the wiring grid is such that the net with the smallest wiring width among the nets handled can be routed without overlapping wiring patterns. Size.

In this arrangement of the terminals T1 to T6, first, the wiring widths used for wiring processing are W1 and W2.
Since there are two types, the distance from the center grid is W
1/2 and W2/2, and the number of lattices occupying the upper, lower, left, and right sides of the central lattice (the number of enlarged lattices) is 0 lattice and 1 lattice, respectively (step S1).

Next, wiring prohibition maps for registering wiring prohibition data for the wiring width W1 and the wiring width W2 are respectively created. At this time, the lattice spacing of the wiring prohibition map corresponding to each wiring width is created in accordance with W1, which is the minimum wiring width. By doing so, the subsequent registration of data in the wiring prohibition map becomes easy (step S2).

Next, the data of the wiring prohibition area set in advance within the wiring area is registered in the wiring prohibition map. At this time, the outer periphery of the wiring prohibited area is enlarged by the number of enlarged grids determined in step S1 and registered. Therefore, the wiring prohibited area shown in FIG. 2 has its outer periphery expanded by 0 grids, that is, it is not enlarged and its own wiring prohibited area is registered in the wiring prohibited map for wiring width W1, and its outer periphery is expanded by 1 grid. The wiring prohibition area enlarged by the width W2 is registered in the wiring prohibition map for the wiring width W2 (step S3).

FIG. 3 is a diagram showing a wiring prohibition map for wiring width 1, and FIG. 4 is a diagram showing a wiring prohibition map for wiring width W2. In both figures, the x marks in the figures indicate that wiring is prohibited, and the center lattice of the wiring pattern of each wiring width cannot pass through the intersection of the lattice marks marked with an x.

Next, the net for wiring the terminals T1 and T2 to be wired first is selected (step S4), and since the wiring width to be used is W1, the net to be used for wiring processing is selected. The prohibition map is based on the wiring width W1 shown in Figure 3.
The one for use is selected (step S5).

Next, a route search is performed on the wiring grid using the wiring prohibition map for the wiring width W1, for example, as shown in FIG.
A wiring path L12 shown by a thick solid line is obtained, and a wiring pattern P12 having a wiring width W1 along this wiring path is obtained as shown in FIG. 6 (step S6).

Next, the obtained wiring pattern P12 is registered in the output list (step S7).

Next, the obtained wiring pattern is additionally registered in the wiring prohibition map. At this time, the area where the outer periphery of the wiring pattern P12 is expanded by 0 grids has a wiring width W1
The wiring prohibition map for the wiring width W1 shown in FIG. 7 is additionally registered in the wiring prohibition map for the wiring width W1 shown in FIG. Furthermore, an area obtained by enlarging the outer periphery of the same wiring pattern P12 by one grid is additionally registered in the wiring prohibition map for wiring width W2, and the wiring prohibition map for wiring width W2 shown in FIG. 8 is created (step S8). .

Next, since there are still unconnected nets, a net for wiring terminals T3 and T4 is selected (step S4), and since the wiring width used is W2, as shown in FIG. A wiring prohibition map for wiring width W2 is selected (step S5).

Next, a wiring route is searched using the selected wiring prohibition map, and, for example, a wiring route L34 shown by a thick solid line in FIG. 9 is obtained, and a wiring width W2 along this wiring route is obtained.
A wiring pattern P34 is obtained as shown in FIG. 10 (step S6).

Next, the obtained wiring pattern P34 is registered in the output list (step S7), and is additionally registered in the wiring prohibition map. At this time, wiring pattern P3
An area obtained by enlarging the outer periphery of 4 by 0 lattice is additionally registered as a wiring prohibition area in the wiring prohibition map for the wiring width W1, and the wiring prohibition map for the wiring width W1 shown in FIG. 11 is created. Furthermore, an area in which the outer periphery of the same wiring pattern P34 is expanded by one grid is additionally registered as a wiring prohibited area in the wiring prohibited map for wiring width W2, and the wiring prohibited map for wiring width W2 shown in FIG. 12 is created ( Step S8).

Next, wiring paths for the terminals T5 and T6 are searched in the same way as for the terminals T1 and T2 using the wiring prohibition map for the wiring width W1 shown in FIG. A wiring route L56 shown by a solid line is obtained, a wiring pattern P56 is obtained as shown in FIG. 14, and the wiring processing for all nets is completed.

In this way, in this implementation, the length that the wiring pattern occupies from the center coordinates is calculated based on the wiring width of the net to be handled, and after the wiring processing is performed, the wiring pattern is are enlarged to correspond to the wiring width of the net, and each is added and registered as a wiring prohibited area in the wiring prohibited map, and in the next wiring process, the wiring is performed using the wiring prohibited map corresponding to the wiring width of the net to be routed. Since this process is performed, the wiring order can be optimized regardless of the wiring width.

Furthermore, in the conventional method, each time a new net is routed, the wiring prohibition data corresponding to all the existing wiring patterns that have been performed up to that point is registered and deleted. However, in the above embodiment, only the wiring prohibition data corresponding to the newly obtained wiring pattern after wiring processing is additionally registered for each wiring width. Since only the following steps are required, processing time can be shortened.

In the above embodiments, the case where there is only one wiring layer is explained, but the present invention can also be applied to multilayer wiring having two or more layers. In that case, it is necessary to create a wiring prohibition map for each wiring layer and a wiring prohibition map for through holes connecting each layer.

[0047] Furthermore, the wiring width is not limited to two types;
Of course, it does not matter if there are three or more types.

Furthermore, in the above embodiment, the grid wiring in which the wiring route is searched on the wiring grid was explained.
It can also be easily applied to gridless wiring that does not use a wiring grid. In that case, instead of the wiring prohibition map, the wiring prohibition area enlarged according to the respective wiring width,
Existing wiring patterns may be registered as actual pattern data for each wiring width and used during wiring processing.

Furthermore, the meaning that a wiring prohibition map is created for registering wiring prohibitions for each wiring width does not necessarily mean that a separate wiring prohibition map is created if there is a net with even a slightly different wiring width. The same wiring prohibition map may be assigned to nets with slightly different wiring widths as long as the influence on other wirings is the same. For example, in the case of grid wiring, if the number of grids occupied is the same, the same wiring prohibition map may be assigned to nets with different wiring widths.

Next, another embodiment of the present invention will be described.

FIGS. 15 and 16 are diagrams showing the processing flow of an automatic wiring processing method according to another embodiment of the present invention. The processing method of the embodiment shown in FIGS. 15 and 16 is characterized in that multiple processors are used to register existing wiring route patterns in wiring prohibition maps created for each different wiring in parallel. It's what I set out to do.

In this example, the case of grid wiring in which the wiring route is searched on a wiring grid will be explained, and in order to simplify the explanation and make it easier to understand, the wiring conditions will be explained. Let the type of wiring width be W, and CPU0
, CPU1, ..., CPUM (M+1) CPUs
Using , W=M×N (N is a natural number), CPU0 registers the net in the wiring prohibition map corresponding to the net to be wired next, and performs wiring processing.
shall only be registered in maps other than the above-mentioned wiring prohibition map.

In FIGS. 15 and 16, first, the wiring width of the net to be handled is checked, and a list (hereinafter referred to as a "routing prohibition map") is created for registering data indicating that wiring is prohibited in grid units.
) is created for each type of wiring width. In addition, the outer periphery of the preset wiring prohibited area is expanded by the number of grids occupied by each wiring width, and the grid is registered as a wiring prohibited area in the wiring prohibited map corresponding to each wiring width ( Step S11).

Next, a net to be subjected to wiring processing is selected (step S12).

Next, the wiring width of the net selected in step S12 is checked, and a wiring prohibition map corresponding to the wiring width is selected (step 13).

Next, using the wiring prohibition map selected in step S13, a search is performed for the wiring route of the net selected in step S12 (step S14).

Next, it is checked whether or not there is a net that has not been wired. If there is, the process proceeds to the next step S16, and if there is not, the wiring process is ended (step S15).

[0058] Then, select the net to be routed next (
Step S16).

Next, the wiring width of the net selected in step S16 is checked, and processing of the wiring prohibition map corresponding to the wiring width is assigned to CPU0 (step S17).

Next, the wiring route obtained in step S14 is converted into wiring prohibition data and additionally registered in the wiring prohibition map assigned to CPU0. To convert and register a wiring route into wiring prohibition data, expand the outer periphery of the wiring route pattern by the number of grids occupied by the wiring width corresponding to the wiring prohibition map, and create a wiring prohibition map on the wiring prohibition map in grid units. This is done by registering (step S1
80).

Next, the CPU 0 performs wiring processing in step S14 using the additionally registered wiring prohibition map, and proceeds to the next step.

As described above, the processing from step S11 to step S180 is performed in CPU0, but step S18 is performed in parallel with the processing from step S180 onward.
1 - S18n are processed by a processor other than CPU0,
It is started in CPU1 to CPUM. CPU1~C
In PUM, the processing of steps S181 to S18n is executed as follows.

First, each processor has step S181.
The wiring prohibition map (MAP (
1) ~MAP (w) [W=M×N]) is allocated in advance. In this embodiment, for CPU1, MAP(1) to MAP(N), for CPU2, MAP(N+1) to MAP(2N), for CPU3, MAP(2N+1) to MAP(3N), ...MAP(M-1)×N+1) to MAP(W) [for CPUM
W=M×N].

[0064] In each processor, step S181
The process of converting the wiring route into wiring prohibition data and registering it in ~S18n is performed the same number of times as the assigned wiring prohibition map (N times in this embodiment). However, the registration in the wiring prohibition map assigned to CPU0 is not performed because the registration is performed in CPU0.

Here, if it is possible for the processing of steps S181 to S18n in CPU1 to CPUUM to be completed just before the next wiring process is completed and the wiring prohibition map is newly allocated to CPU0, The apparent processing time is 1 no matter how many wiring prohibition maps increase.
It is no different from the case of individuals. In other words, even if the number of types of wiring widths increases, the processing time does not increase.

As described above, one processor registers the wiring prohibition data in the wiring prohibition map used for the next net wiring process, and registers it in other wiring prohibition maps. The time required for wiring processing is reduced by assigning the wiring to two processors and performing each processing in parallel. Through such processing, Figure 17
Wiring route patterns R1 to R with different wiring widths as shown in
10 wiring processes can be performed in a short time.

In this embodiment, a case has been described in which a plurality of processors are used to register wiring routes in wiring prohibition maps corresponding to various wiring widths. The process of registering the prohibited area in the wiring prohibited map can also be performed in parallel using the same procedure.

Furthermore, it is not necessary to limit the wiring process in step S14 to a specific processor, and there is also a method in which the wiring process is performed on a processor to which a wiring prohibition map necessary for the next wiring is allocated. With such a method, the time required to transfer each wiring prohibition map data between each processor can be shortened.

Furthermore, when there are a large number of wiring layers, by assigning a wiring prohibition map for each wiring layer to each processor and processing them in parallel, all the wiring prohibition maps can be cleared before the next net is wired. The registration of the wiring route pattern may be terminated.

As mentioned above, in the above embodiment,
Create multiple types of lists for registering wiring prohibition data, depending on the type of net handled and wiring conditions.
By performing wiring using a list corresponding to the net to be routed and registering the obtained wiring route in all lists as routing prohibition data in parallel using multiple processors, it is possible to prevent routing. The processing time required for registration can be reduced. For this reason, it is possible to perform wiring processing without increasing processing time even when the circuits mounted on LS1 become more complex and the wiring layers become multilayered due to high density, and the wiring widths in wiring patterns become more diverse. .

[0071]

As explained above, according to the present invention, each time the wiring process for one net is completed, wiring is prohibited in the area where the obtained wiring route pattern and its outer periphery are expanded by the respective expansion distances. The area is added to the corresponding wiring prohibition list, and the next wiring process is performed using the wiring prohibition list corresponding to the wiring width used for that area, so wiring processing performed using multiple different wiring widths is now possible. processing time can be reduced.

[0072] In addition, the registration in the wiring prohibition list corresponding to the net to be routed next and the registration in all other wiring prohibition lists other than this list by multiple registration processing units are started in parallel. Since it is now possible to perform the registration process for each of the many wiring prohibition lists faster than before, it shortens the processing time for wiring processing performed using multiple different wiring conditions. be able to.

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing a processing procedure of an automatic wiring processing method according to an embodiment of the present invention.

FIG. 2 is a diagram showing a specific wiring example using the processing procedure shown in FIG. 1;

FIG. 3 is a diagram showing a specific wiring example using the processing procedure shown in FIG. 1;

FIG. 4 is a diagram showing a specific wiring example using the processing procedure shown in FIG. 1;

FIG. 5 is a diagram showing a specific wiring example using the processing procedure shown in FIG. 1;

FIG. 6 is a diagram showing a specific wiring example using the processing procedure shown in FIG. 1;

FIG. 7 is a diagram showing a specific wiring example using the processing procedure shown in FIG. 1;

FIG. 8 is a diagram showing a specific wiring example using the processing procedure shown in FIG. 1;

FIG. 9 is a diagram showing a specific wiring example using the processing procedure shown in FIG. 1;

10 is a diagram showing a specific wiring example using the processing procedure shown in FIG. 1. FIG.

FIG. 11 is a diagram showing a specific wiring example using the processing procedure shown in FIG. 1;

FIG. 12 is a diagram showing a specific example of one wiring using the processing procedure shown in FIG. 1;

13 is a diagram showing a specific wiring example using the processing procedure shown in FIG. 1. FIG.

14 is a diagram showing a specific wiring example using the processing procedure shown in FIG. 1. FIG.

FIG. 15 is a flowchart showing a processing procedure of an automatic wiring processing method according to another embodiment of the present invention.

FIG. 16 is a flowchart showing a processing procedure of an automatic wiring processing method according to another embodiment of the present invention.

17 is a diagram showing a specific wiring example using the processing procedure shown in FIGS. 15 and 16. FIG.

FIG. 18 is a flowchart showing the processing procedure of a conventional wiring processing method.

[Explanation of symbols]

S1-S9, S11-S18 Processing steps T1-T
6 Terminals L12, L34, L56 Wiring path

Claims (2)

[Claims] [Claim 1] A first method for determining, for each wiring width, an expansion distance corresponding to each wiring width used in wiring processing.
a second process of creating a wiring prohibition list for each wiring width in which wiring prohibition areas are registered; and a second process of creating a wiring prohibition list in which wiring prohibition areas are registered for each wiring width; A third process of registering the area enlarged by the enlarged distance as a wiring prohibition area corresponding to each wiring width in the corresponding wiring prohibition list created in the second process, and selecting a net to be subjected to wiring processing. Then, the wiring prohibition list corresponding to the wiring width of the selected net is added to the third
a fourth process of extracting from the wiring prohibition list created in the process; and a fourth process of extracting a wiring prohibition area that is selected in the fourth process outside the wiring prohibition area registered in the wiring prohibition list extracted in the fourth process. a fifth process for determining a net wiring route pattern; a sixth process for registering the wiring route pattern obtained in the fifth process in an output list; and a wiring route pattern obtained in the fifth process. and a seventh process of additionally registering an area whose outer periphery is expanded by each enlarged distance obtained in the first process as a wiring prohibition area corresponding to each wiring width to a corresponding wiring prohibition list, and a wiring process. and an eighth process of performing the fourth to seventh processes on all nets to be processed. 2. A first process of creating a plurality of wiring prohibition lists for each wiring condition in which wiring prohibition areas are registered, and selecting a net to be routed and prohibiting wiring corresponding to the wiring condition of the selected net. a second process of extracting a list from the wiring prohibition list created in the first process;
A third process of searching and determining the wiring route pattern of the net selected in the second process outside the wiring prohibition area registered in the wiring prohibition list extracted in the second process, and a fourth process of extracting a net for which a wiring route pattern is then searched and determined if the net exists;
a fifth process of registering the wiring route pattern obtained in the process as a wiring prohibition area in a wiring prohibition list corresponding to the wiring condition of the net extracted in the fourth process;
In parallel with the fifth process, a plurality of processing units perform a process of registering the wiring route pattern obtained in the process as a wiring prohibited area in all wiring prohibition lists other than the wiring prohibition list registered in the fifth process. a sixth process that starts and executes, and a seventh process that repeatedly performs the second to sixth processes for all nets to be routed.
An automatic wiring processing method comprising: