JPH0421136U

JPH0421136U -

Info

Publication number: JPH0421136U
Application number: JP6009990U
Authority: JP
Priority date: 1990-06-06
Filing date: 1990-06-06
Publication date: 1992-02-21

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例による電源保護回路
の概略構成を示したブロツク図、第２図は同回路
の詳細な構成を示した回路図、第３図は従来の電
源保護回路の構成を示した回路図である。１……半導体チツプ、２……電源保護回路、３
……保護対象の回路、４……電源Ｖｃｃ入力端子
、５……接地Ｖｓｓ入力端子、６……信号入力端
子、７……信号出力端子、８……電源Ｖｃｃ出力
端子、９……接地Ｖｓｓ出力端子、１０〜１３…
…ＦＥＴ回路、１０ａ，１１ｂ，１２ａ，１３ｂ
……Ｐチヤネルトランジスタ、１０ｂ，１１ａ，
１２ｂ，１３ａ……Ｎチヤネルトランジスタ。 Figure 1 is a block diagram showing a schematic configuration of a power protection circuit according to an embodiment of the present invention, Figure 2 is a circuit diagram showing a detailed configuration of the same circuit, and Figure 3 is a configuration of a conventional power protection circuit. FIG. 1... Semiconductor chip, 2... Power protection circuit, 3
... Circuit to be protected, 4 ... Power supply Vcc input terminal, 5 ... Ground Vss input terminal, 6 ... Signal input terminal, 7 ... Signal output terminal, 8 ... Power supply Vcc output terminal, 9 ... Ground Vss Output terminals, 10 to 13...
...FET circuit, 10a, 11b, 12a, 13b
...P channel transistor, 10b, 11a,
12b, 13a...N channel transistors.

Claims

[Claims for Utility Model Registration] 1. A power supply input terminal and a ground input terminal are provided on the input side, and a power supply output terminal and a ground output terminal are provided on the output side, and a power supply voltage is applied to the power input terminal and ground is applied to the ground input terminal. a first electrically connecting the power input terminal and the power output terminal so that when a voltage is applied, a power supply voltage is output from the power output terminal and a ground voltage is output from the ground output terminal; and a second connecting means for electrically connecting the ground input terminal and the ground output terminal, wherein a ground voltage is applied to the power input terminal and a power supply voltage is applied to the ground input terminal. Similarly, third connection means electrically connects the power input terminal and the ground output terminal so that the power supply voltage is output from the power output terminal and the ground voltage is output from the ground output terminal. and fourth connecting means for electrically connecting the ground input terminal and the power output terminal. 2. The first to fourth connection means each include a first to fourth FET circuit, and the first FET circuit has a gate connected to the ground input terminal, a source connected to the power supply input terminal, and a drain connected to the ground input terminal. is connected to the power supply output terminal, and an N-channel transistor whose gate is connected to the ground input terminal, whose drain is connected to the power supply output terminal and the drain of the P-channel transistor, and whose source is connected to the ground input terminal. The second FET circuit includes a P-channel transistor whose gate and source are connected to the power input terminal and whose drain is connected to the ground output terminal, and whose gate is connected to the power input terminal and whose drain is connected to the ground output terminal. The output terminal and the drain of the P-channel transistor of this FET circuit include an N-channel transistor whose source is connected to the grounded input terminal, and the third FET circuit has a gate connected to the grounded input terminal and a source connected to the grounded input terminal. an N-channel transistor having a drain connected to the power supply input terminal, a drain connected to the ground output terminal, a gate connected to the ground input terminal, a drain connected to the ground output terminal, and a source connected to the N-channel transistor of the FET circuit; a P-channel transistor connected to the ground input terminal; the fourth FET circuit includes an N-channel transistor whose gate and source are connected to the power supply input terminal, and whose drain is connected to the power supply output terminal; 2. The power supply input terminal includes a P-channel transistor whose drain is connected to the power supply output terminal and the drain of the N-channel transistor of the FET circuit, and whose source is connected to the power supply input terminal. power protection circuit.