JPH04207818A - Data compressor - Google Patents

Abstract

PURPOSE:To obtain a signal processing circuit at low cost by using a shift register which performs the serial/parallel conversion for writing the data into a memory also for compression of data and therefore carrying out the compression concurrently with the conversion of the data. CONSTITUTION:The selectors 24, 25, 30 and 31 select the input A respectively in a normal mode. At the same time, the latches 26 sand 27 hold the higher significant 8 bits out of the PCM data of 16 bits in the timings of the gate signals G1 and G2. Then the selectors 24-31 select the input B respectively in an LP mode. Under such conditions, the latch 26 holds the output of a binary counter 33 equivalent to the higher significant 4 bits of the compression data of 12 bits, a code bit Q0, and the output of an exclusive OR (3 bits) obtained by the EXOR 34, 35 and 36 with use of the signal G1 and in the timing where the higher significant 8 bits (Q0-Q7) of a shift register 23 are all equal to the same code.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applied to a recording and reproducing device such as a digital audio tape recorder (hereinafter referred to as DAT), which has a compressed mode and a non-compressed mode as data recording modes. The present invention relates to a data compression device that can output data in both modes.

2. Description of the Related Art In conventional technical recording and reproducing apparatuses, a method of compressing and recording information has been adopted as one method of increasing the recording density of information. For example, in the case of DAT, 16-bit PCM data is processed and recorded as is in the normal mode, whereas LP (Long Pla...
y: long play) mode.

Here, data compression in LP mode will be explained.

FIG. 3 is a schematic diagram showing the compression/expansion conversion rule between 12-bit compressed data and 16-bit uncompressed data in LP mode. In Figure 3, a 16-bit PC
The most significant bit (15 bits) of the M data is assigned as the sign bit to the most significant bit (11 bits) of the 12-bit compressed data, and the code is set from “°000” to “111” depending on the number of consecutive bits with the same value as the sign bit. '' are assigned to the 1st O bit to the 8th bit. Then, the bits that have a value different from the sign bit are assigned (8 bits (
"ABCDEFGH") is assigned to the 7th bit to the 0th bit. However, if the same value as the sign bit or 8 or more consecutive bits are present, the lower 8 bits are assigned to the 7th to 0th bits. The data is converted into 12-bit compressed data as described above. As shown in FIG. 4, the 12-bit compressed data is word data (Ll.

The upper 8 hit data (Liu, Riu) and the 8 pit data (LRil) which is a combination of both lower 4 hits are written into the memory as 3-byte symbol data for each (Ri: 12 bits). on the other hand,
In normal mode, each word data (16 bits) of the L channel and R channel has a symbol of the upper 8 pit data (L i u, Ri u) and the lower 8 pit data (Li1, R11), totaling 4/1 ite. written to memory as data.

In the conventional DAT, the following processing was performed with a configuration as shown in FIG. Here, signal processing during recording in a conventional DAT will be explained using FIG. In FIG. 5, the PCM data input from the outside is the load signal L
It is loaded into the shift register 1 by Dl and serially output to the interpolation/mute processing unit 2 in order starting from the LSB.

The interpolation/mute processing unit 2 processes the PCM data according to the validity flag (information indicating the validity of the PCM data) input with the PCM data and the soft mute command (level attenuation, muting, etc.) from the system microcontroller. Process. The output from the interpolation/mute processing section 2 is
The data is converted into 16-bit parallel data in the shift register 3.

In the case of normal mode (select signal MODE="0"
”), the 16-bit parallel data is divided into the upper 8 bits and the lower 8 bits, and each is sent to latch 4 and latch 5.
to hold. The high-order 8 bits and low-order 8 bits of the held data are selected by the selector 6 at predetermined timing determined by the select signal 5ELI, and output to the data bus via the selector 7 and written into the memory 8.

On the other hand, in the case of LP mode (MODE="1"), the 16-bit parallel data output from shift register 3 is temporarily transferred to shift register 9 by load signal LD2.
loaded into. This shift register 9 shifts data in the lower direction (from QO to QF), and at that time outputs Q.
By re-inputting O to the serial input S■, the most significant bit MSB loaded into QO is retained and shifted.

Then, among the parallel outputs of the shift register 9, the upper 8 bits (QO-07) are shifted until they have the same sign. Also, at the same time as loading data into the shift register 9, the binary counter 10 is cleared by the clear signal CL.
R is reset, and the number of shifts is counted until the upper eight pits of the shift register 9 reach the same sign. 11. Exclusive OR means (hereinafter referred to as EXOR') uses the count value obtained as described above. 12. 13, the output of the exclusive OR with the sign bit MSB and the sign hit MSB are held in latch 14 (L channel) and latch 15 (R channel). In addition, by holding the lower 8 bits (Q8 to QF) of shift register 9 in latch 16 (L channel) and latch 17 (R channel), 12-bit data processing according to the compression/decompression side of the LP mode described above can be performed. Compressed data is generated. That is, the latch 16 contains the lower 8 of the 12-bit work data Li in FIG.
Similarly, the latch 17 holds the lower eight bits of the 12-pit work data Ri, and further,
12 human work data L for latch 14 and latch 15
The upper 4 bits of i and Ri are each latched. These compressed data are synthesized by the selector 18 with the select signal 5EL2 into 8 bits x 3 bytes of non-pol data in FIG.
output to the data bus via selector 7 in the order of
Written to memory 8.

As mentioned above, in the conventional DAT configuration shown in FIG.
In the P mode, 16-bit serial data is converted from serial to parallel using a shift register, and then compression processing is performed using a dedicated shift register, separate from the normal mode.

Problems to be Solved by the Invention The conventional configuration described above requires a dedicated shift register and its control means for generating 12-bit compressed data in LP mode, and a latch dedicated to LP mode to hold data. The problem has been that the miniaturization and cost reduction of signal processing circuits including compression circuits have not been sufficiently realized.

The present invention solves the above-mentioned conventional problems, and includes a shift register for serial/parallel conversion for outputting recorded and reproduced data to memory, and a shift register for converting 16-bit data into 12-bit compressed data when recording in LP mode. Provides a data compression device that can be used both as a shift register and as a latch for holding data in both normal mode and LP mode, thereby reducing the overall circuit size and cost. The purpose is to

Means for Solving the Problems In order to solve the above problems, the data compression device of the present invention includes:
Convert N-bit parallel data to serial data and convert it to the lowest bit at a bit rate of N times M (Mal).
a first shift register that sequentially outputs the serial data starting from the LSB and holds the most significant bit (MSB) until the next load of parallel data; and a second shift register that converts the serial data into parallel data. , said second
compression means for compressing a part of the data using a count value obtained by counting the number of shifts of data in the shift register; and outputs of the second shift register and the compression means;
a first selector that selects a compressed mode or an uncompressed mode, and an output of the first selector and a second selector;
a latch means for holding the output of the shift register; a flip-flop means for appropriately delaying and outputting the output of the latch means; A second selector is provided to select a compression mode in accordance with the compression mode, and compressed data or uncompressed data is obtained as outputs of the second selector and the latch means.

Effect With the above configuration, N-bit data input from the outside is shifted in the LSB direction at a bit rate of M times N (M>1), and an extra most significant bit, which is a sign bit, is added in advance and the data is serialized. By outputting and processing the PCM data along with an extra sign bit, data compression in LP mode improves the timing of latching data from a shift register that performs serial/parallel conversion to, for example, writing to memory. The serial/parallel data conversion and data compression are performed in the same shift register. Therefore, the conventionally used shift register for serial/parallel conversion for outputting recording/reproducing data to memory and the LP
During mode recording, it is also used as a shift register to convert, for example, 16-bit data to 12-bit compressed data, and a latch for holding data is also used in normal mode and LP mode, so the overall circuit size is reduced. Smaller and lower cost.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a data compression device according to an embodiment in which the present invention is applied to a DAT. In FIG. 1, 21 is a 16-bit shift register;
Convert bit parallel data to serial data
A hit rate of 16 M times (M>1) of 6 bits is output in order from the least significant hit (LSB), and at this time, the most significant hit (MSB) is held until the next parallel data is loaded. That is, the most significant hit, which is a sign bit, is added in advance by the absolute value of (M-1).multidot.N, and the result is serially output. Reference numeral 22 denotes an interpolation/mute processing section, which processes the PCM data according to the validity flag inputted with the PC~1 data and a soft mute command from the system microcomputer. 23 is 16
A bit shift register that converts serial data to parallel data. 24.25 is a selector,
The outputs of the shift register 23 and compression means, which will be described later, are selected depending on the compression mode or non-compression mode. 26
．． 27.28.29 are latches and selectors 24.2
5 and the output of shift register 23 are held.

33 is binary counter, 34.35.36 is EXO
R, binary counter 33 and EXOR 34,3
5 and 36 constitute a compression means, which compresses a part of the data using a count value obtained by counting the number of shifts of data in the shift register 23. 37.38.39 is flip
Flop (D-FF') and latch 26.27.2
8.29 is delayed and output as appropriate. 30.31 is a selector which selects the outputs of the latches 26, 27, 28 and the flip-flops 38, 39 depending on the compression mode or the non-compression mode. 32 is a memory, which obtains compressed data or uncompressed data as outputs of selectors 30, 31 and latch 29, and records this via a data bus.

The operation shown in FIG. 1 will be explained using the timing diagram in the LP mode shown in FIG. 2. In Figures 1 and 2,
First, 16-bit PCM data input from the outside is loaded into the shift register 21 at the timing of the load signal LD, and then shifted downward at a bit rate of 64Fs. At this time, by re-inputting the most significant bit, which is the code bit, to the serial input Sr, the loaded 16 code bits are serially output. Regarding 32-bit PCM data with a sign bit added, the interpolation/mute processing unit 22 performs PCM
The data is processed according to the validity flag input with the data and the soft mute command from the system microcomputer, and the output is output to the shift register 23 in order from the LBS.

Below, the case of normal mode (MODE="0") and L
The operation will be explained separately for the case of P mode (MODE="l").

When in normal mode, selector 24.25.30.3
1 selects input A. At this time, the latches 26 and 27 control the 16-bit PC at the timing of the gate signals Gl and G2 (in this case, the gate signals Gl and G2 are at the same timing).
Holds the upper 8 bits of M data.

Similarly, latches 28,29 are connected to gate signals G3. The lower 8 bits of the 16-bit PCM data are held at the timing of G4 (in this case, the gate signals G3 and G4 are at the same timing). The held data is output to the data bus or written into the memory 32 via the selectors 30 and 31 at predetermined timings.

On the other hand, in the LP mode, selectors 24.25.30.
3) selects input B. At this time, the latch 26 receives a binary signal corresponding to the upper 4 bits of the 12-bit compressed data by the gate signal Gl at the timing when the upper 8 bits (QO-07) of the shift register 23 all have the same sign.
EXOR34 of the output of the counter 33 and the sign bit QO
, 35, 36 and the sign bit QO are held. This data corresponds to the top four hits in FIG. The binary counter 33 is
It is reset by the clear signal CLR at the timing when the first bit (LSB) of the PCM data of each sample is shifted in the shift register 23 and output to the output QF.
The count is increased in synchronization with the shift of CM data in the shift register 23. Furthermore, when the L channel data is shifted in the shift register 23, the latch 27 latches bits QC-QF of the shift register 23 using the gate signal G2 at the timing when the upper 7 pits (QO to Q6) become the same sign. do. Similarly, the latch 29 is
When shifting the R channel data in the soft register 23, the shift register 23 is shifted by the gate signal G4 at the timing when the upper 7 pits (QO-06) have the same sign.
latches the hit QC-QF. The data latched in latches 27 and 29 correspond to the lower four hits of each L/R sample of the 12-bit work data in FIG. 4, respectively. When the data of each L/R channel is shifted in the shift register 23, the latch 28 uses a gate signal G3 to shift bits 08 to QB of the shift register 23 at the timing when the upper 7 pits (QO to Q6) have the same sign. Latch.

This data corresponds to bits 7 to 4 of each L/R channel of the 12-bit work data in FIG. Outputs of the latches 26 and 28 corresponding to the upper 8 bits of the 12-bit compressed data of this held data are delayed by one sample period by a flip-flop 37 and a subsequent flip-flop 38, and then sent to the selector 30. via the data bus and written into the memory 32.

Also, the L of the 12-bit compressed data held in the latch 27
The data corresponding to the lower 4 bits of the channel is delayed by 1/2 sample period by the flip-flop 39 and then sent via the selector 31 to the lower 4 bits of the R channel of the 12-bit compressed data held in the latch 29. It is output along with the data to the data bus and written into the memory 32.

As described above, the 3-byte 8-pit symbol data in FIG. 4 is written into the memory 32 in the order of Liu, LRil, and Riu.

This allows data compression processing and serial/parallel conversion to be performed in the same shift register.

Additionally, the number of latches that hold compressed data and flip-flops used to delay data can be minimized.

Effects of the Invention As described above, according to the present invention, the shift register that performs serial/parallel conversion for writing data into memory can also be used for data compression, and compression can be performed at the same time as the conversion. Since the number of latches that hold data to be written can be kept to a minimum, the overall circuit scale and cost can be further reduced. Therefore, a signal processing circuit capable of supporting both normal mode and LP mode can be constructed at low cost using a data compression circuit with a small circuit scale.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a data compression device according to an embodiment of the present invention applied to a DAT, FIG. 2 is a timing chart showing the circuit operation of FIG. 1 in LP mode, and FIG. 3 is a DAT. Figure 4 is a schematic diagram showing the rules for converting 12-bit work data into 8-bit symbol data in the LP mode, and Figure 5 is a schematic diagram showing the rules for converting 12-bit work data into 8-bit symbol data in the LP mode. FIG. 2 is a block diagram showing the configuration of a data compression device in DAT. 21.23...Shift register, 24.25.30.
31... Selector, 26.27.28.29... Latch, 32... Memory, 33... Binary counter, 34.35.36... EXOR, 37, 38,
39...Flip flop.

Claims (1)

[Claims] 1. Convert N-bit parallel data to serial data and output it sequentially from the least significant bit (LSB) at a bit rate that is M times N (M>1), and at the same time output the most significant bit (MSB). A first shift register that holds until the next parallel data is loaded, a second shift register that converts the serial data into parallel data, and a count value that counts the number of shifts of data in the second shift register. a first selector that selects the output of the second shift register and the compression means according to a compression mode or a non-compression mode; a latch means for holding the output and the output of the second shift register; and a flip-flop for appropriately delaying and outputting the output of the latch means.
flop means, and a second selector for selecting the output of the latch means and the output of the flip-flop means in accordance with the compression mode or the non-compression mode, the outputs of the second selector and the latch means; A data compression device configured to obtain compressed data or uncompressed data.