JPH04207242A - Data transmission equipment - Google Patents

Abstract

PURPOSE:To improve the reliability and to shorten the abnormality detection time by detecting the abnormality of a signal line of a common bus at the time of not transferring data and initializing a digital device in the case of the abnormality and inhibiting data transfer at the time of a failure of recovery of trouble. CONSTITUTION:A clock generator 15 sends a signal line abnormality detection timing pulse to an FF 16 through a trigger line 19 at the time of not using the bus and periodically checks signal lines 10 and 11. If a signal on signal lines 10 and 11 is turned on because of trouble of an I/O or the common bus itself, an OR gate 13 is turned on, and an FF 16 is set by the signal 19 to detect the trouble. All I/Os are reset to the initial state by a reset signal sending circuit 18 before next data transfer is started. Signal lines are checked again after sending of the reset signal; and if the abnormality is detected again, the FF 17 is set to inhibit data transfer. Thus, the reliability is improved, and the time loss to abnormality detection is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a data transmission device that selectively connects a plurality of digital devices via a common bus.

(Prior art) As digital devices become larger and more complex, the number of signal wires increases and signal processing becomes difficult using individual wiring as in the past. This method uses the road as a bus and sends and receives signals from multiple points on the bus.

FIG. 3 is a block diagram showing a conventional general configuration of a data transmission device using a bus method. Data transmission and reception on the common bus 1 is managed by a bus control device 2, and the common bus 1 is connected to an input/output device 4 via an input/output control device 3. Each input/output device 4 sends a signal onto the common bus 1 through the transmission gate 5 of the input/output control device 3, and the signal is received by the reception gate 6 in the bus control device 2.

The impedance of the transmission gate 5 is low impedance when the signal is ON, and high impedance when the signal is OFF.

By the way, in a bus-type transmission device, if the output of the transmission gate 5 of the input/output control device 3 remains at low impedance due to malfunction or failure, data transfer via the common bus 1 is impossible unless the impedance is restored. Therefore, all input/output processing using the common bus 1 is stopped.

(Problem to be solved by the invention) When there is an abnormality in a signal line, it is necessary to detect the abnormality and take prompt action, but in conventional devices, the common bus 1
An abnormality is detected as a result of data being sent and received via the .

Therefore, there is a problem in that the reliability of the system decreases because data is transferred in vain until the abnormality is discovered, and there is a large loss of time until the abnormality is discovered.

An object of the present invention is to provide a data transmission device that improves the reliability of a data transmission system and minimizes the time loss until an abnormality is detected.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention includes a plurality of digital devices and a common bus, each digital device is sequentially and asynchronously connected to the common bus, In a data transmission device that transfers data by exclusive use of the common bus between connected digital devices, an abnormality in the signal line of the common bus is detected when none of the digital devices connected to the common bus is transmitting data. a state setting means for initializing all of the digital devices when an abnormality is detected by the detection means; , and a holding means for holding all of the digital devices in an initialized state when an abnormality is detected.

(Function) An abnormality in the signal line of the common bus is detected at a time when no data is being transferred on the common bus, and if an abnormality is detected, all digital devices are initialized, and then The signal line is checked again for abnormality, and if the failure has not been recovered, data transfer on the common bus is prohibited.

(Embodiment) FIG. 1 is a circuit diagram showing an embodiment of a data transmission device according to the present invention. The circuit shown in FIG. 1 corresponds to the bus control device in FIG. 3, and the circuit shown in FIG.
is composed of a signal line 9 indicating that the input/output device 4 is transferring data, a reset line 12, and data lines 10 and 11. The bus control device also includes OR gates 13, 14 .
Clock generator 15, flip-flop 16. 1
7. It is composed of a reset signal sending circuit 18.

In such a configuration, when the bus control device is powered on and the common bus becomes usable, the clock generator 15
1, when working all the time and not using the bus.
A signal line abnormality detection timing pulse is sent to the flip-flop 17 via the tri-power line 19. flip flop 16
The signals on the signal lines 10 and 11 are inputted through the OR gate 13 and the signal line status display line 20 .

When the signal line 9 is in the OFF state and data transfer is not being performed on the common bus, the flip-flop 16 checks the signal lines 10 and 11 at regular intervals using the signal from the clock generator 15, and the transmission gate Check for malfunctions. At this time, if the signal becomes O due to a failure of the input/output device on signal line 10 or 11 or a failure of the common bus itself.
If it is N, the output of the OR gate 13 is ONL, and the flip-flop 16 is set by the trigger signal 19.

That is, a failure is detected by the flip-flop 16.

In failure conditions, normal data transfer is not guaranteed. Therefore, before the next data transfer is started, all the input/output devices are reset to the initial state by the reset signal sending circuit 18 which performs state setting. After sending the reset signal,
It is checked again whether all the signal lines except the reset line 12, including the signal lines 10, 11 and 9, are turned off.

(A) to (D) in Figure 1 are (A) to (D) shown in Figure 2.
) signal. The output of the gate 13, which is the OR output of the signal lines 10 and 11, and the output of the OR gate 14 with the signal line 9 are input to the flip-flop 17, and the output of the gate 14, which is the OR output of the signal line 10 and 11, is input to the flip-flop 17,
Check the timing.

If an abnormality is detected again here, flip-flop 1
7 is set, and while the flip-flop 17 is also set, a reset signal continues to be output to the reset line 12 as shown by the broken line in FIG. 2(C).

In other words, if no abnormality is detected again in the check after sending the reset signal, the abnormality previously detected in the flip-flop 16 is an abnormality that can be recovered by resetting the input/output device, so the data on the common bus Resume the transfer.

However, if an abnormality is detected again in the check of the flip-flop 17, it is determined that the failure requires maintenance, the input/output devices connected to the common bus are locked, and data transfer on the common bus is prohibited from now on.

While the signal indicating data transfer on the signal line 9 is on, the flip-flop 16 is reset and at the same time the trigger signal output 19 of the clock generation circuit 15 is blocked. It does not affect the transfer at all.

``Effects of the Invention: According to the present invention, failures in the common bus can be detected before data transfer, and the effects of the failure can be confined within the common bus and prevented from spreading to the processing devices that use the common bus, thereby improving system performance. Reliability can be improved and time loss until abnormality detection can be minimized.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a data transmission device according to the present invention, and FIG.
The figure shows a signal timing chart of the circuit diagram shown in FIG.
FIG. 3 is a block diagram of a conventional data transmission device. 9...Signal line 10.11...Data line 12...
...Reset signal line 13.14...
OR gate 15...Clock generator 16
．． 17...Flip-flop18...
...Reset pulse circuit 19...
・Trigger wire 20・・・・・・・・・Signal status line Agent Patent attorney Noriyuki Chika Diagram 2

Claims (1)

[Claims] In a data transmission device comprising a plurality of digital devices and a common bus, each digital device is sequentially and asynchronously connected to the common bus, and the connected digital devices exclusively use the common bus to transfer data. detection means for detecting an abnormality in the signal line of the common bus at a timing when none of the digital devices connected to the bus is transmitting data; and a holding means for maintaining the initialized state for all of the digital devices when the detecting device detects an abnormality in the signal line of the common bus again after the digital devices have been initialized. A data transmission device comprising: