JPH04205474A - Memory access device - Google Patents

Abstract

PURPOSE:To rapidly write picture elements successively outputted from a DDA in a graphic memory and to rapidly execute also data transfer in the graphic memory by providing this memory access device with an FIFO memory means and a control means for controlling the FIFO memory means. CONSTITUTION:In the case of writing picture elements successively outputted from the DDA 1a, a selection instructing signal is supplied from a control circuit 5a to a selection circuit 2 to select data supplied through a plotting access bus 1 and a write enabling signal and a page mode operation control signal (a page address/row address strobing signal, a column address strobing signal, etc.) are supplied from the control circuit 5a to the graphic memory 4. In a period requiring no page changing processing, the control circuit 5a supplies an I/O enabling signal to the FIFO memory 3. Consequently data transfer in the graphic memory 4 can be also rapidly executed in addition to the data writing of data successively generated from the DDA in the graphic memory 4.

Description

[Detailed Description of the Invention] Industrial Application Field> The present invention relates to a memory access device, and more specifically, the present invention relates to a memory access device, and more specifically, to a memory access device for writing output data from a host processor or a linear generator into a memory for display or for graphics display. The present invention relates to a device for transferring data within a processing memory.

<Prior art> Graphics display devices have traditionally used high resolution,
There is a strong demand for simultaneous multi-color display, and in order to satisfy these demands while reducing the overall size and cost of the graphics display device, memory for graphics display processing (hereinafter referred to as "graphics memory") has been developed. Dynamic Random Access Memory (hereinafter referred to as D)
The video RAM (hereinafter referred to as VRAM) writes pixel data using random access and reads out multiple pixels simultaneously using sequential access.

Then, a linear generator (hereinafter referred to as
As shown in FIG. 3, as a configuration for writing pixels sequentially generated by DDA) into a display memory,
The pixels sequentially output from D D A (61) are transferred to a data buffer y (Ha) (8
2b) (82c) (62d) is written to one of the brains, and in parallel with this writing, each memory device ( 63a)
(83b) (133e) A configuration for writing to (Bad) is adopted. Although not shown, a selector, a buffer for holding read pixels, and a bidirectional buffer are provided between the data buffer (62) and the graphics memory (68) as necessary.

If such a configuration is adopted, the data buffer (62
) by setting the capacity of each brane appropriately.
The pixel generation speed by DDA (61) is
to the graphics memory (63), even if it is significantly faster than the pixel write speed to the memory (63).
The writing speed converted per pixel is D D A (
D D
A (81) Graphics without interruption of operation
Pixel writing to memory (63) can be achieved.

<Problems to be Solved by the Invention> When attempting to perform scroll processing, window movement processing in multi-window display, etc. by employing the above configuration, as shown in FIG. When moving pixel data in a rectangular area (destination rectangular area, source rectangular area) within (63), the pixel data must be moved with the data buffer (62) interposed. For this reason, there is an inconvenience that the pixel data movement process cannot be accelerated. More specifically, the data in the data buffer (62a) is transferred to the data buffer (62a) and the data in the data buffer (62b) is transferred to the data buffer (62b) according to the address of the rectangular area.
In addition to transferring data to the same data buffer as in the respective transfer cases, the data buffer (
B2a) data to data buffer (82b),
It is also required to transfer data to different data buffers, such as transferring data from data buffer (62b) to data buffer (82a), respectively. Therefore, to deal with each of these cases, data buffers (62a) (62b) (62c) <62
d) assignment must be changed. However, (62a) (62b) (82c) of the data buffer
Since the allocation change in (62d) cannot be easily achieved because the buffer memory itself has a fairly large number of input/output bins, the data transfer to the data buffer including the allocation change process is not easy. This takes a considerable amount of time, and as a result, data transfer within the graphics memory (63) cannot be achieved at high speed.

Furthermore, if the graphics memory has a look-up table (hereinafter abbreviated as LUT) for specifying display colors, it may be necessary to change the contents of the LUT; Since there is a possibility that the LUT is being referred to while the display is being performed by the device, the contents of the LUT are not changed during the vertical blanking period of the CRT display device in order to prevent the display from being changed inadvertently. Changes are made. Specifically, the vertical blanking period is detected in the upper processor,
After that, new display color specification data must be written to the LUT. Therefore, there is a problem that the speed at which the contents of the LUT can be changed cannot be increased very much.

<Object of the invention> This invention was made in view of the above problems,
Not only can the pixels sequentially output from the DDA be written into the graphics memory at high speed, but also data transfer within the graphics memory can be performed at high speed. L
It is an object of the present invention to provide a novel memory access device that can quickly change the contents of a UT.

Means for Solving the Problems> To achieve the above object, the memory access device of the first invention has a drawing access bus for supplying output data from a linear generator and a graphics display processing bus. A FIFO memory means interposed between the memory means and the data supplied through the drawing access bus when accessed by the linear generator is temporarily held and supplied to the memory means for graphics display processing, and the data is supplied to the memory means for graphics display processing. Controlling FIFO memory means for temporarily holding data read from the memory means for graphics display processing and supplying it again to the memory means for graphics display processing when data is transferred within the memory means for processing. and control means for controlling.

In the memory access device of the second invention, the memory means for graphic display processing further includes look-up table means for specifying display colors, and supplies display color specifying data output from the host processor. C.P.
The controller further includes a U access bus, and the control means causes the FIFO memory means to temporarily hold the display color designation data on condition that updating of the contents of the lookup table means is instructed, and the vertical block. It further has the function of controlling the FIFO memory means to cause the FIFO memory means to supply display color specification data to the look up table means during the ranking period.

The memory access device of the third invention further includes a CPU access bus that supplies output data output from the host processor, and the control means directs data transfer based on the direct memory access function. Temporarily transfer the data to FI based on the condition that
It further has a function of controlling the FIFO memory means so as to cause the FIFO memory means to hold the data and then access the memory means for graphics display processing to send out the held data.

Effect> With the memory access device of the first invention, when performing drawing processing based on output data from the linear generator,
Since the FIFO memory means is interposed, the difference between the pixel generation speed by the linear generator and the access speed in the memory means for graphics display processing can be absorbed by the FIFO memory means, and the difference in the pixel generation speed by the linear generator and the access speed in the memory means for graphics display processing can be absorbed by the FIFO memory means, resulting in interruption of the operation of the linear generator. It is possible to achieve high-speed pixel writing with no distortion. Also, when transferring data into the graphics memory during scroll processing, window movement processing, etc., the data reception destination of the intervening FIFO memory means is set to the input destination and data destination. These setting processes can be easily accomplished, and data transfer can be speeded up.

In the memory fist access device of the second invention, the look
When changing the contents of the up-table means, the control means causes the FIFO memory means to temporarily hold the display color designation data output from the host processor at an arbitrary timing, detects the vertical blanking period, and then stores the display color designation data output from the FIFO memory means at an arbitrary timing.
Display color specification data can be supplied from the memory means to the look-up table means, and the look-up table means can supply display color specification data to the look-up table means.
Changes to table contents can be accomplished quickly.

In the memory access device of the third invention, when data transfer based on direct memory access is instructed, the control means causes the FIFO memory means to temporarily hold the data to be transferred, and then , the memory means for graphics display processing can be accessed and stored data can be sent out, data transfer based on direct memory access can be achieved at high speed, and
It is possible to increase the usage efficiency of the CPU access bus.

<Example> Hereinafter, embodiments will be described in detail with reference to the accompanying drawings showing examples.

FIG. 1 is a block diagram showing an embodiment of the memory access device of the present invention, in which data supplied from DDA (1a) through a drawing access bus (1) is supplied to a select circuit (2). , the data selected by the select circuit (2) is supplied to the FIFO memory (3),
-Time held. The data held in the FIFO memory (3) is supplied to the graphics memory (4). Further, data read from the graphics memory (4) is supplied to the select circuit (2). still,
(5a) supplies a select instruction signal to the select circuit (2), an input/output permission signal to the FIFO memory (3), and a page/output permission signal as well as a write permission signal and a read permission signal to the graphics memory (4). This is a control circuit that supplies mode operation control signals.

The operation of the memory access device having the above configuration is as follows.

When writing the pixels sequentially output from DDA (1a) to the graphics memory (4), the control circuit (5a) selects the data supplied through the drawing access bus (1). A select instruction signal is supplied to the circuit (2), and a write enable signal and page mode operation control signals (page address, row address strobe signal, column address strobe signal, etc.) are supplied to the graphics memory (4). ) and supplies an input/output permission signal to the FIFO memory (3) during a period when page change processing is not required.However,
When page change processing is required, various signals for page change processing are supplied to the graphics memory (4), and only an input permission signal is supplied to the FIFO memory (3).

Therefore, pixel data sequentially output from the DDA (1a) can be written at high speed through the FIFO memory (3) to the graphics memory (4) operating in page mode.

In addition, when data is transferred within the graphics memory (4) for scroll processing, window movement processing, etc., the selection circuit (2) is provided with data read from the graphics memory (4). At the same time, it supplies a select instruction signal instructing that the selected data should be selected, and also alternately supplies a read permission signal and a write permission signal to the graphics memory (4). It is sufficient to supply data indicating the corresponding areas in correspondence with each other.

In this case, first read the data of the corresponding area in scan line units from the graphics memory (4) and store it in the FIFO memory (3), and then
The data held in the IFO memory (3) is written to the graphics memory (4) in units of scan lines, and the above operation is repeated for all applicable scan lines, thereby writing the data to the graphics memory (4). (4) Data transfer between corresponding areas can be performed.

Incidentally, even if multiple FIFO memories (3) are provided, and for example, they are allocated corresponding to even-numbered scan lines and odd-numbered scan lines, this allocation can be changed easily and quickly. Therefore, the above data transfer can be achieved at high speed.

<Embodiment 2> FIG. 2 is a block diagram showing another embodiment of the memory access device of the present invention. The difference from the embodiment of FIG. 1 is that the CPU access bus (
6) The data supplied through the bidirectional buffer (7)
, the graphics memory (4) includes an LUT memory (4a), and in addition to the signal from the control circuit (5a), the LUT
A control circuit (5b) detects a vertical blanking period of a CRT display device (not shown) and also supplies an output permission signal to the FIFO memory (3) when an update of the memory (4a) is instructed. It is only a point that has been set.

Therefore, in this embodiment, the LUT memory (4
When update of a) is required, the LUT data supplied through the CPLI access bus (6) is held in the FIFO memory (3) regardless of the vertical blanking period, and is updated by the control circuit (5b). When a vertical blanking period is detected, an output enable signal is supplied to the FIFO memory (3), and the LUT memory (4a)
It is possible to perform updates.

In this case, a write permission signal is supplied to the graphics memory (4), and the LUT
By supplying the corresponding row address and column address to the memory (4a), only the contents of the LUT memory (4a) can be updated without affecting other areas.

Also, when performing direct memory access to the graphics memory (4) through the CPU bus (6), data is temporarily held in the FIFO memory (3) and then output to the FIFO memory (3). High-speed access can be achieved by supplying a write enable signal and corresponding row and column addresses to the graphics memory (4) as well as supplying the enable signal. And in this case -danFIF
After storing data in O memory (3), the CPU access bus (6) can be used freely.
The CPU access bus can be used more efficiently.

<Effects of the Invention> As described above, the first invention has the unique effect of speeding up not only the writing of data sequentially generated by the DDA but also the data transfer within the graphics memory.

In the second invention, when it is necessary to update the contents of the LUT memory means, the data to be updated is held in the FIFO memory means without considering the vertical blanking period at all, and the data to be updated is stored in the FIFO memory means during the vertical blanking period. The unique effect is that data can be written from the memory means to the LUT memory means at high speed.

In the third invention, when direct memory access to the memory means for graphics display processing is instructed, after data is held in the FIFO memory means, the
The unique advantage is that the PU access bus can be used freely and the efficiency of use of the CPU access bus can be increased without sacrificing high-speed access to the memory means.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the memory access device of the invention, FIG. 2 is a block diagram showing another embodiment of the memory access device of the invention, and FIG. 3 is a block diagram showing another embodiment of the memory access device of the invention. A schematic block diagram showing a conventional example. FIG. 4 is a schematic diagram illustrating data transfer within a graphics memory. (1)...Drawing access bus, (1a)...DD
A. (3)...FIFO memory, (4)...Graphics memory, (4a)...
LUT memory, (5a) (5b)...control circuit, (6)...CP
U Access Nox, (6a)...Upper processor patent applicant Daikin Industries, Ltd.

Claims (1)

[Scope of Claims] 1. A memory access device having a drawing access bus (1) for supplying output data from a linear generator (1a) and a memory means (4) for graphics display processing, comprising: FIFO interposed between the access bus (1) and the memory means (4) for processing graphics display
memory means (3) and data supplied through the drawing access bus (1) when accessed by the linear generator (1a) are temporarily held and supplied to the memory means (4) for graphics display processing; Memory means (4) for graphics display processing; memory means (4) for temporarily holding data read out from the memory means (4) for graphics display processing during internal data transfer; A memory access device characterized in that it comprises control means (5a) for controlling the FIFO memory means (3) to be supplied to the FIFO memory means (3). 2. The memory means (4) for graphic display processing further includes look-up table means (4a) for designating display colors, and supplies display color designation data output from the host processor (6a). The controller further includes a CPU access bus (6), and the control means (5b) inputs the display color specification data to FI on condition that updating of the contents of the lookup table means (4a) is instructed.
The look data is temporarily stored in the FO memory means (3) and the look data is stored temporarily in the FIFO memory means (3) during the vertical blanking period.
2. A memory access device according to claim 1, further comprising a function of controlling the FIFO memory means (3) to cause the up table means (4a) to supply display color specification data. 3. It further includes a CPU access bus (6) for supplying output data output from the host processor (6a), and the control means (5b) is configured to instruct data transfer based on the direct memory access function. The data to be transferred is temporarily stored in FIFO memory means (
3), and then controls the FIFO memory means (3) so as to access the memory means (4) for graphics display processing and send out the retained data. The memory access device according to scope 1.