JPH0420083A - Picture processing unit - Google Patents

Abstract

PURPOSE:To obtain a desired still picture from a moving picture with a simple operation by designating an interval of storing an input moving picture to a memory capable of storing plural pictures and designating an outputted picture among the pictures stored in the memory. CONSTITUTION:The picture processing unit is provided with a moving picture / still picture conversion circuit 10, a moving picture input device 12 for a television / camera, a monitor 14 such as a CRT, and a printer 16, and interfaces 18,20,22, a control circuit 26, a memory 28 provided with memories 28-1-28-4 and a memory control circuit 30 of the moving picture / still picture conversion circuit 10 are interconnected by a data bus 32, a system bus 34 and an address bus 36. Then an interval of storing an input moving picture to the memory capable of storing plural pictures is designated and a picture to be outputted among the stored pictures stored in the memory is designated. Thus, a desired still picture is obtained from an input moving picture with a simple operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device that outputs a moving image input from a television camera, VTR, etc. as a still image to a CRT, printer, etc.

[Prior Art] In the past, image signals applied to printers and the like were mainly input from still image input devices such as image scanners, but in recent years, image signals applied to printers and the like have been input from still image input devices such as television cameras, video cameras, VTRs, etc. A wide variety of video equipment has come into use. Furthermore, there is a desire to print images of high-definition television signals such as HDTV using printers and printing devices.

[Problems to be Solved by the Invention] However, when extracting one scene (screen) of a moving image such as an output signal from a television camera as a still image, there are still many problems in obtaining a good still image. For example, when an object to be photographed is moving, considerable skill is required to extract a favorite or necessary scene from the moving image signal.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an image processing device that can obtain a desired still image from a moving image with a simple operation.

[Means for Solving the Problems] An image processing apparatus according to the present invention includes a memory means capable of freely storing a plurality of images, an interval at which input moving images are stored in the memory means, and an image processing apparatus that specifies an interval at which input moving images are stored in the memory means. Of the images,
The present invention is characterized by comprising a specifying means for specifying an image to be output.

[Operation] With the above means, a desired still image can be obtained from an input moving image with a simple operation.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of the present invention and its peripheral equipment. Reference numeral 10 designates a moving image/still image conversion device which is an embodiment of the present invention, 12 a moving image input device such as a television camera, 14 a monitor such as a CRT, and 16 a printer such as a laser beam printer. In the tenth embodiment, 18, 20, and 22 are the moving image input devices 12, respectively.
, a monitor 14, and an interface with the printer 16; 24 is an operating device operated by the operator; 26 is the device 1;
A control circuit for controlling the sequence of 0, 28 is four frame memories 28-1.28-2.28-3.28-4
30 is a memory control circuit that controls the memory device 28.

The interfaces 18, 20, 22, control circuit 26, memory device 28 and memory control circuit 30 are connected to a data bus 32.
, a system bus 34 and an address bus 36.

FIG. 2 shows a configuration block diagram of main circuit parts related to the operation of inputting (freezing) images from the moving image input device 12 to the memory device 28. Of course, the same components as in FIG. 1 are given the same reference numerals.

The interface 18 includes a gate circuit 40 that turns on and off the input of a moving image signal from the moving image input device 12, a DIP switch (a set of eight in this embodiment) 41 and a latch circuit 42 that control the gate circuit 40. , the interface 20 includes a gate circuit 44 that turns on and off image data output from the device 10 to the monitor 14, a DIP switch 45 and a latch circuit 46 that control the gate circuit 44. Further, in the control circuit 26, 48
is a ROM that stores sequence programs, etc.

49 is a work RAM, 50 is a CPU, 51 is an internal data bus, 52 is an internal address bus, and 53 is an I that performs input/output with the system bus 84 and the address bus 36.
O boat 54 is an IO that performs input/output with the operating device 24
It's a boat.

In the memory control circuit 30, 56 is a counter that designates a valid image area, 57 is a logic circuit, and 58 is a counter that generates an address for the memory device 28. memory 28
-1, 60.61 is a latch circuit, 62.63 is a DIP switch, 64 is a logic circuit, 65 is a translator that performs input/output with the data bus 32, 66 is a logic circuit, and 67 is a frame memory for images. It is. The other memories 28-2 to 28-4 are also turned on and off using the DIP switches 62 and 63.
It has the same circuit configuration as the memory 28-1 except for the off setting.

The system bus 34 includes a frame synchronization signal (FRSYN).
C) 34-1, bus input enable signal (BSIENB) that gives the right to input data from the data bus 32 34-
2. Bus output enable signal (BSOENB) that provides the data output product to the data bus 32 34-3. Freeze request signal (FZREQ) that requests freeze operation 34
-4, freeze busy signal (FZB) indicating that image data is being written to any of the memories 28-1 to 28-4
SY) There are 34-5 signal lines. Of course, there are other signal lines on system bus 34 as well.

The freeze operation will be explained with reference to FIG. In order to simplify the explanation, the logic of each signal is expressed as positive logic (
The high state is active logic). First, freeze conditions (the number of screens to be stored, their interval, etc.) are set in the control circuit 26 from the operating device 24. For example, a case will be explained in which three screens are frozen at an interval of two frames. The control circuit 26 receives the freeze condition from the operating device 24 via the 10 port 54 and stores the information in the RAM 49. Specifically, a memory counter MRCNT formed by software is set to 3, and a frame counter FRCNT is set to 2.

The control circuit 26 from the operating device 24 also includes a memory 28-
Specify the freezing order from 1 to 4. Within the control circuit 26, information in the designated order is stored in the RAM 49, and the information is stored in the RAM 49.
BSIENB34-2 and BSO via O boat 53
Outputs the initial state to ENB34-3.

Here, it is assumed that the memories 28-1.28-2.28-3 are frozen in this order. The storage table of the RAM 49 at this time is shown in FIG.
FIG. 5 shows the bit assignment of EMB34-3. According to this bit assignment, only b4 of the DTP switch 41 of the interface 18 is on, and D of the interface 20 is on.
Only the IP switch 45 is on, and the memory 28-1.
28-2.28-3.28-4 DIP switch 62.
63, only bo, bl, b3, and b8 are on in this order, and all others are off.

In this initial state, no writing is performed to the memories 28-1 to 28-4, and the previous image is held.

Furthermore, moving images from the moving image input device 12 are supplied to the monitor 14 via an interface 18, a data bus 32, and an interface 20.

When a request signal to start freezing is supplied from the operating device 24 to the control circuit 26, inside the control circuit 26, the CPU 5
0 enables interrupts by FRSYNC34-1. After that, in synchronization with the rise of FR5YNC34-1, the 10 port 53 outputs one pulse to FRREQ34-4, the CPU 50 initiates an interrupt, and decreases FRCNT by 1 (from 2 to 1 at this stage).
Make it. ), it is checked whether FRCNT is 0 or not, and if it is not 0, the interrupt processing is terminated.

At this time, the access rights (input rights and output rights) of the data bus 32 are B50ENB34-2.6<21H, so the interface 2o and the memory device 28 have input rights, and since BSOEMB34-3 is loH, The interface 18 has output authority. In the interface 18, the latch circuit 42 latches B50ENB34-3 from the rising edge of FRSYNC34-1, and DI
The gate circuit 40 is placed in a passing state via the P switch 41. As a result, from the moving image input device 12 to the data bus 3
Image data is input to 2. In addition, in the interface 2o, the latch circuit 46 latches the BS IENB34-2 when the FRSYNC34-1 voltage rises, and the DI
The gate circuit 44 is placed in a passing state via the P switch 45. As a result, the image data on the data bus 32 is output to the monitor 14.

In memory device W2B, latch circuits 60 and 61 are FR5Y.
NC34-117) Rising edge each B50EN
Latch B34-2 and B50ENB34-3 and set DI
Activating the output of P switch 62 and deactivating the output of DIP switch 63 causes logic circuit 64 to configure translator 65 to enable input from data bus 32 . This allows the data
Image data on bus 32 is applied to frame memory 67 via translator 65. However, at this point, writing to the frame memory 67 is not yet performed. In the memories 28-2 to 28-4, the portion corresponding to the translator 65 is inactive, so the data bus 32 cannot be accessed.

In the memory control circuit 30, the counter 56
34-1, outputs a signal indicating the effective screen area within one frame to the logic circuit 57 according to the horizontal synchronization signal HSYNC and the video clock VDCLK, and the logic circuit 57
The output is made inactive at the rising edge of SYNC34-1, and the output of the counter 56 is passed at the falling edge of FZREQ34-4. The output of the logic circuit 57 is FZBSY3
4-5 and an enable terminal of a counter 58, and the counter 58 increments a held value in response to the video clock VDCLK and outputs the incremented value to the address bus 36.

Note that the counter 58 is initialized by the fall of FR5YNC34-1. As a result of the above, FZBSY34-5
Since only the valid screen area is active, it becomes a comb-shaped waveform.

When FZBSY34-5 becomes active, memory 28
-1 logic circuit 66 selects FZBSY34-5 to the chip select terminal CS of the frame memory 67 and FZBSY34-5 to the read/write terminal according to the output of the DIP switch 62 (active) and the output of the DIP switch 63 (non-active). 5 is applied. As a result, image data is written into the frame memory 67 at the address indicated by the address bus 36 while the FZBSY 34-5 is active.

After writing one frame, FRSYNC is executed again.
When 34-1 rises, counters 56 and 58 and logic circuit 57 in the memory control circuit 3 are initialized again, and F
ZBSY34-5 becomes non-active. Also FRS
The rise of YNC34-1 causes an interrupt to the CPU 50, and the CPL150 interrupts the FRCNT by the interrupt processing.
is decreased by 1, and at this stage it goes from 1 to 0. F.R.
Since CNT has become O, MRYCNT is decreased by 1 (from 3 to 2), and the set value (2 in this case) stored in the RAM 49 is set again in FRCNT. RAM49
Read the values lOH and 22H advanced by one set from the table in the table, and read them from the IO port 53 respectively B50EN 34-3
and output to B50ENB34-2, FZREQ34-
However, FZREQ34-5 does not become active until the next rise of FRSYNC34-1. )
, ends interrupt processing.

Therefore, in this frame (second frame), the image data is not written to any of the memories 28-1 to 28-4 and is output only to the monitor 14, and is then displayed on the FRSYNC3.
4-1 at the start (3rd frame) grinning, IO hole
) 53 jlZREQ34-54. : One pulse is output, and the interface 18 obtains the output product to the data bus 32 according to the values of BSIENB34-2 and BSOEMB34-3 (22H, 10H), and the interface 20 and memory 28-2 obtain the output product from the data bus 32. acquire the right. Thereafter, just as the first frame was frozen in the memory 28-1, the third frame is frozen in the memory 28-2.

Like the second frame, the fourth frame is displayed on the monitor 14 without being frozen. CPU50 is FR
Reset CNT, decrease MRYCNT by 1, and
SOEM8.94-3 and BSIENB34-21.
Set the m-th value (IOH, 22H) and call FZREQ3
Set port 10 to prepare to activate 4-5.

The fifth frame, like the first and third frames, is frozen in the memory 28-3.

At the sixth frame, the interrupt processing of the CPU 50, FRCNT and MRYCNT, both turn to o, and the CP
U50 determines that the series of freezes has ended, and performs the following processing. That is, FRCNT and MRYCNT
Reset to 2 and 3 respectively, and BSOEMB34-3
and BSIENB34-2 respectively IOH and 21H
1: Reset, set the signal that makes FZREQ34-4 inactive to the IO port 53, return the contents of RAM49 to the state before the freeze start request, and FRSYN
Disable interrupts of CPLI50 by C34-1.

In the manner described above, it is possible to selectively execute various freeze operations in which the number of freeze images, freeze interval, and freeze destination are specified. In the initial state (default old state) where freeze operation is not specified, for example, the number of frozen images is 1.
, the freeze interval is 1, and the freeze destination is set to the memory 28-1.

Next, the operation of selecting a plurality of frozen frames of images and displaying them on the monitor 14 will be described with reference to FIG. In the normal state, images input by the moving image input device [12] are displayed on the monitor 14. When a request to display an image stored in the memory device 28 is input from the operating device 24 to the control circuit 26, the control circuit 26 performs the AND of the value of BSIENB34-2 (21H in this case) and θFH, and outputs the result (01H in this case). WoIO Horde 53 Kara B50ENB
34-31. : Output, BSIENB34-21:20
FZREQ34-5 outputs FRSYNC
Set 10 ports so that they become active in synchronization with the rising edge of 34-1.

At this point, as in the normal state, the FRS to the CPU 50 is
Interrupts by YNC34-1 are prohibited.

FRSYNC34- immediately after a request to display a stored image is made
At the rising edge of 1, the output product to the data bus 32 is
8-1, the input right from the data bus 32 is given to the interface 2o, FZREQ34-4 becomes active (one pulse is generated), and FZBSY34-
5 and address bus 36, image data is outputted from frame memory 67 of memory 28-1 to data bus 32 and applied to monitor 14 via interface 20.

Until a memory switching request specifying another memory 28-2 to 28-4 is input from the operating device 24, the FRSYNC34
-1, the stored image in the memory 28-1 is displayed on the monitor 14.
are displayed continuously.

When there is a memory switching request, the control circuit 26 outputs B50.
Updated ENB34-3 value (0 from Kokoteha, olH)
4Ht: update) and outputs the same value (20H here) as BSIENB34-2. Therefore, at the rising edge of PRSYNC34-1 immediately after the memory switching request, the output product to the data bus 32 is given to the memory 28-3, the input right from the data bus 32 is given to the interface 20, and the memory 28-3 is stored. Images are displayed continuously on the monitor 14. Similarly, any memory 28-1 to 28-4 can be specified.

When there is a request to display an input image from the moving image input device 12 on the monitor 14, that is, a video camera display request, the state is returned to the state before the input of the storage image display request. That is, B.S.O.
Set EM834-3 to IOH and BS IENB34-2
is set to 21H, the output product to the data bus 32 is given to the interface 18, the input right from the data bus 32 is given to the interface and memory 28-1, and the input image from the moving image input device 12 is displayed on the monitor 14. Furthermore, since the IO port 53 is set to make the FZREQ 34-4 inactive, no access (write) to the memory 28-1 occurs at this stage.

Next, with reference to FIGS. 8 and 9, memories 28-1 to
The operation of outputting the stored image No. 4 to the printer 16 will be explained. In FIG. 8, 70 is a counter, 71 is a logic circuit,
72 is a counter, and 74 is a logic circuit. These operate in the same way as the circuits 56, 57, 58°66, but the reference signals are different. The system bus 34 also includes a printer vertical synchronization signal PR3YNC 34-6, a print request signal PRREQ 34-7, and a print busy signal PRBSY 34-8.

When a print request is input from the operating device 24 to the control circuit 26, the control circuit 26 outputs data from 0ENB34-3 to 02H
Output. It also outputs 40H to B50ENB 34-2, provides the output product from data bus 32 to interface 22, and sets 10 port 53 to activate PRREQ 34-7. PRREQ3 is output at the rising edge of PRSYNC34-6 immediately after a print request.
4-7, and the input right and output product of the data bus 32 are determined.

The PRREQ 34-7 outputs a print start request to the printer 16 via the interface 22, and the printer 16
, the vertical synchronization signal PR5YNC34-6, the horizontal synchronization signal PRH5YNC, and the printer pixel clock PRC.
System bus 34 via LK or interface 22
is output to. Counter 70 is PRSYNCPRHS
According to YNC<PRCLK, a signal PRBSY34-8 indicating a valid image for printing is output, an address is generated from the counter 52 within the valid image, and is output to the address bus 36. Memory 28-2 is connected to address bus 36 and PRB.
The SY34-8 sequentially reads image data from a frame memory corresponding to the frame memory 67 and outputs it to the data bus 32. Image data on data bus 32 is applied to printer 16 via interface 22;
Printer 16 forms an image based on the image data.

When the printer 16 finishes forming an image, PRSYNC becomes inactive, and the control circuit 26 connects the B50ENB34-3 and B50ENB342 via the IO port 26.
is the state before the print request occurs (i.e. 10H121H
) and complete the print operation.

FIG. 10 shows a block diagram of another embodiment of the present invention. Reference numeral 80 denotes a data bus access right designation circuit which includes the above-described frame counter FRCNT and memory counter MRYCNT and designates the access right to the data bus 32 during fleece operation, monitor switching, and printer operation. The data bus access right specifying circuit 8 transmits changing access rights from the operating device 24 via the control circuit 26.
0 in advance, and the data bus access right specifying circuit 80 switches the data bus access right when executing a freeze operation or the like. Other operations are the same as in the previous embodiment.

[Effects of the Invention] As can be easily understood from the above explanation, according to the present invention, images of specified frames of a series of moving images can be stored as still images in a plurality of memory means with a very simple operation. Furthermore, selection between printer output and monitor output can be easily made.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the structure of an embodiment of the present invention, Fig. 2 is a block diagram of the structure of parts related to freeze operation, Fig. 3 is a flow chart of freeze operation, Fig. 4 is a table of freeze types, and Fig. 5 is a block diagram of the structure of an embodiment of the present invention. Figure 6 shows the bit assignment of the bus input/output enable signal, Figure 6 shows the relationship between the effective screen and blanking, and Figure 7 shows the relationship between the valid screen and blanking.
8 is a block diagram of the structure of the print operation-related portion, FIG. 9 is a timing chart of the print operation, and FIG. 10 is a block diagram of the structure of another embodiment. 10: Video/still image conversion device 12: Video image input device
14: Monitor 16: Printer 18, 20. 22: Interface 24: Operating device 26/control circuit 28
: Memory device 30: Memory control circuit 32: Data bus 34 System bus 36: Address bus (1) BSOENB34-3 MSB b7b6 5b4 l SB (2) BSIENB34-2 MSBb7b6b5b4b3b2b1b. SB Figure R3YNC

Claims (1)

[Claims] The present invention includes a memory means capable of storing a plurality of images, and a specifying means for specifying an interval at which input moving images are stored in the memory means and specifying an image to be output from among the images stored in the memory means. An image processing device characterized by: