JPH04199566A - Integrated circuit - Google Patents
Integrated circuitInfo
- Publication number
- JPH04199566A JPH04199566A JP33539190A JP33539190A JPH04199566A JP H04199566 A JPH04199566 A JP H04199566A JP 33539190 A JP33539190 A JP 33539190A JP 33539190 A JP33539190 A JP 33539190A JP H04199566 A JPH04199566 A JP H04199566A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- chips
- package
- input
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 40
- 238000012856 packing Methods 0.000 abstract 2
- 230000010354 integration Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 235000012771 pancakes Nutrition 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
Landscapes
- Dram (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体集積回路の、特に集積度の向上に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor integrated circuits, particularly to improving the degree of integration.
第3図、第4図は従来の半導体集積回路をジグザグイン
ラインパッケージにした半導体装置の平面図および断面
図である。図において、(])は表面に集積回路を作り
込んだ半導体チップ、(2)は外部との信号の伝達を行
う入出力端子、(3)は半導体チップ(1)上に設けら
れた入出力用パッド、(4)は入出力用パット(3)と
入出力端子(2)を接続するワイヤー、(5)は全体を
保護するパッケージである。FIGS. 3 and 4 are a plan view and a sectional view of a semiconductor device in which a conventional semiconductor integrated circuit is packaged in a zigzag in-line package. In the figure, (]) is a semiconductor chip with an integrated circuit built into its surface, (2) is an input/output terminal that transmits signals to the outside, and (3) is an input/output terminal provided on the semiconductor chip (1). (4) is a wire that connects the input/output pad (3) and the input/output terminal (2), and (5) is a package that protects the entire device.
次に動作について説明する。半導体集積回路をを動作さ
せる場合、入出力端子(2)に外部より電源電圧、制御
信号、アドレス入力、データ入力信号を印加することに
より、それらの情報はワイヤー(4)を伝って、半導体
チップ(1)上のパッド(3)に伝達される。この制御
信号によって、半導体チップ(11上に設けられた半導
体集積回路が動作する。Next, the operation will be explained. When operating a semiconductor integrated circuit, by applying external power supply voltage, control signals, address input, and data input signals to the input/output terminals (2), the information is transmitted through the wires (4) to the semiconductor chip. (1) is transmitted to the upper pad (3). This control signal causes the semiconductor integrated circuit provided on the semiconductor chip (11) to operate.
従来の半導体集積回路は以上のように構成されていたの
で、1つのパンケージ内には一つの集積回路しかなく、
そのため、1つのパッケージで記憶容量を上げるには記
憶容量を上げる分だけ集積回路自体を小さく作ることか
必要で、プロセス的に大いに制約を受けるという問題点
かあった。又、集積回路自体はそのままで、記憶容量を
上げるには半導体装置自体の数を増加する必要かあり、
この場合、集積度は悪くなるという問題点もあった。Conventional semiconductor integrated circuits were configured as described above, so there was only one integrated circuit in one pancake.
Therefore, in order to increase the storage capacity in a single package, it is necessary to make the integrated circuit itself smaller to accommodate the increased storage capacity, which poses the problem of being subject to significant process constraints. In addition, it is necessary to increase the number of semiconductor devices to increase the storage capacity without changing the integrated circuit itself.
In this case, there was also the problem that the degree of integration was poor.
この発明は上記のような問題点を解消するためになされ
たもので、1つのパッケージ内に、複数の半導体チップ
を設け、外部からはあたかも大きな記憶容量のチップか
入っている半導体装置と同様に使用にてきる半導体集積
回路を得ることを目的とする。This invention was made in order to solve the above-mentioned problems, and by providing a plurality of semiconductor chips in one package, it can be viewed from the outside as if it were a semiconductor device containing a chip with a large memory capacity. The aim is to obtain semiconductor integrated circuits that can be used.
この発明に係る半導体装置は、チップ上に複数チップセ
レクト用のパッドを設け、同一パッケージ内に複数のチ
ップを入れる場合、特定のアドレスの入力信号を各々異
なるチップセレクト用パッドに接続することにより、入
力されたアドレスによりチップを選択、非選択にするよ
うにしたものである。In the semiconductor device according to the present invention, when a plurality of chip selection pads are provided on a chip and a plurality of chips are placed in the same package, input signals of specific addresses are connected to different chip selection pads. Chips are selected or unselected depending on the input address.
〔作用〕
この発明における半導体集積回路は、チップセレクト用
のパッドをチップ上に設けることにより、1つのパッケ
ージ内に複数のチップを同時にアセンブリして、使用す
る場合にアドレスの情報によりチップの選択、非選択を
決めることができるようにしたので、半導体装置として
の記憶容量が同時にアセンブリされるチップ倍数となる
。[Function] The semiconductor integrated circuit according to the present invention allows a plurality of chips to be simultaneously assembled in one package by providing chip selection pads on the chip, and when used, it is possible to select and select chips based on address information. Since non-selection can be determined, the storage capacity of the semiconductor device is multiplied by the number of chips that can be assembled at the same time.
以下、この発明の一実施例を図について説明する。第1
図、第2図において、(1)はその表面に集積回路を作
り込んた半導体チップ、(2)は外部との信号の伝達を
行う入出力端子、(3)は半導体チップ(1)上に設け
られた入出力用パッド、(4)は入出力用バット(3)
と入出力端子(2)を接続するワイヤー、(5)は全体
を保護するパンケージ、(6)は半導体チップ(1)上
に設けられ、ワイヤー(4)により入出力端子(2)と
接続することにより、入力されtニアトレスによってチ
ップ(1>を選択、非選択にするチップセレクト用バッ
トである。An embodiment of the present invention will be described below with reference to the drawings. 1st
In Figure 2, (1) is a semiconductor chip with an integrated circuit built into its surface, (2) is an input/output terminal for transmitting signals to the outside, and (3) is a semiconductor chip on the semiconductor chip (1). The input/output pad provided (4) is the input/output bat (3)
and the wire connecting the input/output terminal (2), (5) is the pan cage that protects the whole, (6) is provided on the semiconductor chip (1), and is connected to the input/output terminal (2) by the wire (4). This is a chip selection bat that selects or deselects the chip (1>) according to the input t near trace.
次に動作について説明する。Next, the operation will be explained.
外部的には従来の半導体装置の場合とまったく同して、
入出力端子(2)に外部より電源電圧、制御信号、アド
レス入力、データ人ツノ信号を印加することにより、そ
れらの情報はワイヤー(4)を伝って半導体チップ(1
)上のパッド(3)に伝達される。Externally, it is exactly the same as in the case of conventional semiconductor devices,
By applying a power supply voltage, control signal, address input, and data signal to the input/output terminal (2) from the outside, the information is transmitted through the wire (4) to the semiconductor chip (1).
) is transmitted to the pad (3) above.
この制御信号によって、半導体チップ(1)上に設けら
れた半導体集積回路が動作することになるのは同一であ
るが、本実施例の半導体集積回路は1つのパッケージ内
に複数のチップをアセンブリしており、各チップの選択
、非選択は半導体チップ(1)上に設けられたチップセ
レクト用パッド(6)を選択的にボンディングすること
により、外部信号(通常は最上位アドレス)によって決
定し得る。This control signal causes the semiconductor integrated circuit provided on the semiconductor chip (1) to operate, but the semiconductor integrated circuit of this embodiment has multiple chips assembled in one package. The selection or non-selection of each chip can be determined by an external signal (usually the highest address) by selectively bonding the chip select pad (6) provided on the semiconductor chip (1). .
本実施例における半導体集積回路は以上のように、外部
的には従来の半導体装置とまったく同じように制御する
ことがてき、集積度(記憶と容jl)は次世代の半導体
装置と同様の半導体装置を得ることができる。As described above, the semiconductor integrated circuit in this embodiment can be controlled externally in exactly the same way as conventional semiconductor devices, and the degree of integration (memory and capacity) is similar to that of next-generation semiconductor devices. You can get the equipment.
なお、上記実施例ではワイヤー(4)によって入出力信
号端子(2)とチップセレクト用バット(6)を接続し
た場合を示したが、接続はワイヤー(4)でなくてもよ
く、例えばバンブ等によりポリシリコンあるいはポリソ
リサイド等による接続を行った場合てもよく、上記実施
例と同様の効果を奏する。In addition, although the above embodiment shows the case where the input/output signal terminal (2) and the chip select bat (6) are connected by the wire (4), the connection may not be made by the wire (4), for example, by using a bump or the like. The connection may be made using polysilicon, polysolicide, or the like, and the same effect as in the above embodiment can be obtained.
又、チップセレクト用バット(6)を設けず、直接内部
の配線と入出力信号端子を接続するようにしても同様で
、この発明に含まれることは言うまでもない。Further, it goes without saying that the same effect can be achieved even if the chip selection bat (6) is not provided and the internal wiring is directly connected to the input/output signal terminal, and this is of course included in the present invention.
以上のようにこの発明によれば、1つの半導体装置を複
数の同一チップを1つのパッケージにアセンブリする構
成にしたので、集積度の高い半導体集積回路が安価にて
きるとともに、また、開発期間も短いものが得られると
いう効果がある。As described above, according to the present invention, one semiconductor device is constructed in such a way that a plurality of identical chips are assembled into one package, so that highly integrated semiconductor integrated circuits can be produced at low cost, and the development period can be shortened. This has the effect of allowing you to obtain something shorter.
第1図および第2図はこの発明の一実施例である半導体
集積回路の平面図及び断面図、第3図および第4図は従
来の半導体集積回路平面図および断面図である。
図において、(])は半導体チップ、(2)は入出力端
子、(3)は入出力用パッド、(4)はワイヤー(配線
)、(5)はパッケージ、(6)はチップセレクト用バ
ットを示す。
なお、図中、同一符号は同一、又は相当部分を示す。1 and 2 are a plan view and a sectional view of a semiconductor integrated circuit according to an embodiment of the present invention, and FIGS. 3 and 4 are a plan view and a sectional view of a conventional semiconductor integrated circuit. In the figure, (]) is a semiconductor chip, (2) is an input/output terminal, (3) is an input/output pad, (4) is a wire (wiring), (5) is a package, and (6) is a bat for chip selection. shows. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
体集積回路を設けた半導体チップを複数同一パッケージ
に収め、アドレスを入力する外部端子を、それぞれの前
記チップの異なる前記チップセレクト用パッドに接続し
、最上位アドレスによってパッケージ内の前記チップを
任意に選択することができるようにしたことを特徴とす
る半導体集積回路。A plurality of semiconductor chips each having a semiconductor integrated circuit having a plurality of chip select pads on the chip are housed in the same package, and an external terminal for inputting an address is connected to a different chip select pad of each chip. A semiconductor integrated circuit characterized in that the chip within the package can be arbitrarily selected based on an upper address.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33539190A JPH04199566A (en) | 1990-11-28 | 1990-11-28 | Integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33539190A JPH04199566A (en) | 1990-11-28 | 1990-11-28 | Integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04199566A true JPH04199566A (en) | 1992-07-20 |
Family
ID=18288021
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP33539190A Pending JPH04199566A (en) | 1990-11-28 | 1990-11-28 | Integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04199566A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6538331B2 (en) | 2000-01-31 | 2003-03-25 | Hitachi, Ltd. | Semiconductor device and a method of manufacturing the same |
JP2007019415A (en) * | 2005-07-11 | 2007-01-25 | Renesas Technology Corp | Semiconductor device and its manufacturing method |
JP2008515203A (en) * | 2004-09-27 | 2008-05-08 | フォームファクター, インコーポレイテッド | Stacked die module |
JP2014523601A (en) * | 2011-07-05 | 2014-09-11 | インテル・コーポレーション | Self-disable chip enable input |
JP2017050450A (en) * | 2015-09-03 | 2017-03-09 | 株式会社東芝 | Semiconductor device |
-
1990
- 1990-11-28 JP JP33539190A patent/JPH04199566A/en active Pending
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8067251B2 (en) | 2000-01-31 | 2011-11-29 | Elpida Memory, Inc. | Semiconductor device and a method of manufacturing the same |
US7633146B2 (en) | 2000-01-31 | 2009-12-15 | Elpida Memory Inc. | Semiconductor device and a method of manufacturing the same |
US7061105B2 (en) | 2000-01-31 | 2006-06-13 | Hitachi, Ltd. | Semiconductor device and a method of manufacturing the same |
US8853864B2 (en) | 2000-01-31 | 2014-10-07 | Ps4 Luxco S.A.R.L. | Semiconductor device and a method of manufacturing the same |
US6538331B2 (en) | 2000-01-31 | 2003-03-25 | Hitachi, Ltd. | Semiconductor device and a method of manufacturing the same |
US8502395B2 (en) | 2000-01-31 | 2013-08-06 | Elpida Memory, Inc. | Semiconductor device and a method of manufacturing the same |
US6686663B2 (en) | 2000-01-31 | 2004-02-03 | Hitachi, Ltd. | Semiconductor device and a method of manufacturing the same |
US7879647B2 (en) | 2000-01-31 | 2011-02-01 | Elpida Memory, Inc. | Semiconductor device and a method of manufacturing the same |
US7348668B2 (en) | 2000-01-31 | 2008-03-25 | Elpida Memory, Inc. | Semiconductor device and method of manufacturing the same |
US8159062B2 (en) | 2000-01-31 | 2012-04-17 | Elpida Memory, Inc. | Semiconductor and a method of manufacturing the same |
US8324725B2 (en) | 2004-09-27 | 2012-12-04 | Formfactor, Inc. | Stacked die module |
JP2008515203A (en) * | 2004-09-27 | 2008-05-08 | フォームファクター, インコーポレイテッド | Stacked die module |
JP2007019415A (en) * | 2005-07-11 | 2007-01-25 | Renesas Technology Corp | Semiconductor device and its manufacturing method |
JP2014523601A (en) * | 2011-07-05 | 2014-09-11 | インテル・コーポレーション | Self-disable chip enable input |
JP2017050450A (en) * | 2015-09-03 | 2017-03-09 | 株式会社東芝 | Semiconductor device |
US10262962B2 (en) | 2015-09-03 | 2019-04-16 | Toshiba Memory Corporation | Semiconductor device |
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