KR19990008726A - Memory-Shared Multichip Package - Google Patents

Abstract

The present invention relates to a memory-sharing multi-chip package, in the present invention comprises a memory chip is divided into a cell region, by allowing a plurality of microchips to share each cell region of the memory chip, The overall size can be reduced, and secondly, the overall cost of the product can be reduced.

Description

Memory-Shared Multichip Package

The present invention relates to a multi-chip package, and more particularly, to a multi-chip package that allows a plurality of microchips to share a memory chip.

With the recent development of digital signal processing (Digital Signal Processing) technology, the signal processing method of logic elements used in an audio system, a video system, or a communication system is also changing from the conventional analog signal processing method to a digital signal processing method. .

As a result, a logic element such as a microchip and a memory chip capable of storing and reproducing information are mounted on one silicon substrate, and the logic element and the memory chip are electrically connected to each other by a circuit pattern formed inside the silicon substrate. Connected multi-chip packages are also accelerating their development.

1 is a block diagram schematically illustrating a configuration of a conventional multi-chip package for performing such a function.

As shown, a conventional multi-chip package interfaces with a substrate 1, microchips 2 disposed on the substrate 1 to control the operation of the entire apparatus and interface with these microchips 2; Consisting of memory chips 3.

At this time, each of the memory chips 3 interfaces with the individual microchips 2 in charge thereof to store and reproduce data required by each microchip 2, and read or write such data.

For example, the first memory chip 3a interfaces with the first microchip 2a in charge of the first memory chip 3a to read or write data required by the first microchip 2a or to store and reproduce the data.

In addition, the second memory chip 3b interfaces with the second microchip 2b in charge thereof to read or write data required by the second microchip 2b or to store and reproduce the data.

As described above, the first microchip 2a and the second microchip 2b derive the data required by the first microchip 2a and the second microchip 2b from the first memory chip 3a and the second memory chip 3b through the above-described interface process. Therefore, it is possible to appropriately perform various control operations required for itself.

However, there are some significant problems with conventional multichip packages that perform this function.

First, as advanced electronic devices such as notebook PCs, cellular phones, and hand phones have been developed recently, a thinner multi-chip package is required. However, as described above, in the conventional multi-chip package, each individual microchip is used. By having memory chips individually responsible for this, the size of the entire product is increased, and as a result, there is a problem in that it cannot adequately meet the aforementioned thinning requirements.

Secondly, as described above, each of the microchips must have memory chips that are responsible for this, thereby increasing the overall cost of the product.

Accordingly, an object of the present invention is to provide a memory chip in which a cell region is divided, and to allow a plurality of microchips to share each cell region of the memory chip, thereby reducing the number of memory chips in a package, thereby providing a product. To provide a memory-sharing multi-chip package that allows the overall size of the thinner.

Another object of the present invention is to provide a memory-sharing multi-chip package capable of reducing the overall cost of a product by reducing the number of memory chips in a package as described above.

1 is a block diagram schematically showing the configuration of a conventional multi-chip package.

Figure 2 is a block diagram schematically showing the configuration of a multi-chip package according to the present invention.

3 is a conceptual diagram schematically illustrating a cell area of a memory unit according to the present invention;

The present invention for achieving the above object is a memory unit having a first cell region and a second cell region; A first address sending unit which sends an address signal for accessing data stored in the first cell area; And a second address sending unit for sending an address signal for accessing data stored in the second cell area.

Preferably, the first address sending unit and the second address sending unit divide and send a column address strobe signal to the first cell area and the second cell area, respectively.

Preferably, the first address sending unit and the second address sending unit may be configured to send a row address strobe signal integrated in the first cell area and the second cell area.

Accordingly, in the present invention, the memory chip can be shared by the microchip.

Hereinafter, a memory sharing multi-chip package according to the present invention will be described in more detail with reference to the accompanying drawings.

2 is a block diagram schematically illustrating a configuration of a memory sharing multi-chip package according to the present invention, and FIG. 3 is a conceptual diagram schematically showing a cell area of a memory unit according to the present invention.

As shown, the present invention provides a main body 1, a memory unit 10 formed on the main body 1, having a first cell region 11 and a second cell region 12, and a main body 1; A first address sending unit 20 formed on the main body 1 to send an address signal for accessing data stored in the first cell region 11 and stored in the second cell region 12 formed on the main body 1; And a second address sending section 30 for sending an address signal for accessing data.

Here, as the first address sending unit 20 and the second address sending unit 30, the above-described non-memory element microchip may be used.

Hereinafter, the operation of the present invention having such a configuration will be described in detail.

First, the first address sending unit 20 and the second address sending unit 30 transmit a WE (Write Enable) signal to the first cell area 11 of the memory unit 10 to obtain data necessary for its operation. The input is common to the second cell region 12.

Subsequently, the first address sending unit 20 and the second address sending unit 30 use the OE (Out Enable) signal to obtain the data necessary for their operation, similarly to the above-described WE signal. The input is common to the cell region 11 and the second cell region 12.

Accordingly, the memory unit 10 can read and write data.

Subsequently, the first address sending unit 20 and the second address sending unit 30 transmit a row address strobe (RAS) signal to the first cell region (not shown) of the memory unit 10. 11) and the second cell area 12 in common.

Accordingly, in the memory unit 10, rows of output cells capable of outputting data are commonly designated.

Thereafter, the first address sending unit 20 and the second address sending unit 30 transmit a column address strobe (CAS) signal (CAS) signal to the first cell area of the memory unit 10 ( 11) and the second cell area 12 are divided and input.

Accordingly, in the memory unit 10, a column of output cells capable of outputting data is divided and designated.

In other words, the first address sending unit 20 and the second address sending unit 30 input the above-described RAS signal to the first cell region 11 and the second cell region 12 in common, and contrast CAS. The signal is divided and input into the first cell region 11 and the second cell region 12. At this time, since the signal directly contributing to the memory sharing of the present invention is a CAS signal, the first address sending unit 20 and the second address sending unit 30 separate and input such a CAS signal for each cell area. The data necessary for the operation of A is appropriately divided from each cell area to be accessed.

This will be described in more detail with reference to FIG. 3.

First, as described above, the RAS signal is commonly input to each cell area of the memory unit 10 by the first address sending unit 20 and the second address sending unit 30.

Accordingly, a plurality of cells formed in the first cell area 11 and the second cell area 12 commonly designate rows necessary for the operation of the first address sending unit 20 and the second address sending unit 30. Receive.

Subsequently, the above-described CAS signal is divided into a first cell region 11 and a second cell region 12 of the memory unit 10 by the first address sending unit 20 and the second address sending unit 30, respectively. Is entered.

In this case, the CAS signal input to the first cell region 11 is, for example, an upper CAS signal, and the CAS signal input to the second cell region 12 is, for example, a lower CAS signal. Accordingly, the plurality of cells formed in the first cell region 11 are appropriately designated a column necessary for the operation of the first address sending unit 20, and the plurality of cells formed in the second cell region 12 are assigned the second address. The heat necessary for the operation of the sending unit 30 is appropriately designated.

At this time, as described above, the row of each cell is commonly designated through the RAS signal, and the CAS signal input following the RAS signal is designated as an appropriate column in the predetermined row, thereby outputting data to be in charge of data output. Determine the cell.

For example, a row of data output cells is commonly designated as a third row throughout the first cell region 11 and the second cell region 12 through the above-described RAS signal, and the data output cell through the above-described CAS signal. When the column of is specified as the second column and the seventh column for each of the first cell region 11 and the second cell region 12, the data and the second cell 12a stored in the corresponding first cell 11a The data stored in the parentheses) is divided into the first address sending unit 20 and the second address sending unit 30, and are output and accessed.

As a result, the first address sending unit 20 and the second address sending unit 30 are appropriately accessed with data necessary for their operation.

As described above, in the present invention, one memory is divided into two cell regions, and data stored in each of the divided cell regions is allocated to an appropriate microchip through the above-described CAS signal to access the memory. Allow microchips to share. As a result, the number of memories arranged in the apparatus is significantly reduced, and the apparatus is thinned.

Moreover, in the present invention, the cost of the device can be appropriately lowered by reducing the number of memories.

This invention exhibits useful effects throughout all varieties of multichip packages with various capacity memory chips.

And while certain embodiments of the invention have been described and illustrated, it will be apparent that the invention may be embodied in various modifications by those skilled in the art.

Such modified embodiments should not be understood individually from the technical spirit or point of view of the present invention and such modified embodiments should fall within the scope of the appended claims of the present invention.

As described in detail above, in the memory-sharing multi-chip package according to the present invention, a memory chip having a divided cell region is provided, and a plurality of microchips can share each cell region of the memory chip. It can reduce the overall size of, and secondly, reduce the overall cost of the product.

Claims (3)

A memory unit having a first cell region and a second cell region; A first address sending unit which sends an address signal for accessing data stored in the first cell area; And a second address sending unit configured to send an address signal for accessing data stored in the second cell area. The memory sharing type multi-chip of claim 1, wherein the first address sending unit and the second address sending unit divide and send a column address strobe signal to the first cell area and the second cell area, respectively. package. The memory sharing multi-chip package according to claim 1, wherein the first address sending unit and the second address sending unit integrate and send a row address strobe signal to the first cell area and the second cell area. .