JPH04196580A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04196580A JPH04196580A JP33531790A JP33531790A JPH04196580A JP H04196580 A JPH04196580 A JP H04196580A JP 33531790 A JP33531790 A JP 33531790A JP 33531790 A JP33531790 A JP 33531790A JP H04196580 A JPH04196580 A JP H04196580A
- Authority
- JP
- Japan
- Prior art keywords
- main case
- case
- leads
- substrate
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000004020 conductor Substances 0.000 claims abstract description 15
- 229910000679 solder Inorganic materials 0.000 abstract description 15
- 239000006071 cream Substances 0.000 abstract description 12
- 239000007767 bonding agent Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 241000220317 Rosa Species 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置に係り、特に電力用モジュール
の外装に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the exterior of a power module.
第６図（ａ）〜（ｅ）は従来の電力用モジュールの組立
図を示すものである。第６図（ａｌにおいて、１は底板
として使用される金属性の放熱板であり、この放熱板１
上には絶縁基板（もしくは絶縁膜）２が装着され、さら
にその上に導体配線３がなされている。第６図（ｂ）に
おいて、前記絶縁基板２上の導体配ｓ３のバラ１：上に
クリーム半田４を塗布後、半導体素子５が搭載される。FIGS. 6(a) to 6(e) show assembly diagrams of conventional power modules. In Figure 6 (al), 1 is a metal heat sink used as a bottom plate, and this heat sink 1
An insulating substrate (or insulating film) 2 is mounted on top, and conductor wiring 3 is further formed on it. In FIG. 6(b), cream solder 4 is applied onto the rose 1 of the conductor arrangement s3 on the insulating substrate 2, and then the semiconductor element 5 is mounted.
また、導体配！３と半導体素子５もしくは導体配線３同
士での電気的接続を必要とするものはワイヤ６等で接続
がなされる。第６図（ｃ）において、外部との電気的接
続を行うためのリード７は各リードことに半田付けを行
い搭載される。第６図（ｄ）において、半導体素子５お
よびリード６の搭載の完了した絶縁基板２に対し無底の
箱体状のケース８を接着させる。第６図（ｅ）において
、半導体素子５の保護のためのゲル状充填物９が注入さ
れ、さらに、その上に樹脂１０が注入されて密封される
（例えば、実開昭６３−１８７３５４号公報参照）。Also, conductor arrangement! 3 and the semiconductor element 5 or the conductive wiring 3 that requires electrical connection with each other, the connection is made with a wire 6 or the like. In FIG. 6(c), leads 7 for electrical connection with the outside are mounted on each lead by soldering. In FIG. 6(d), a bottomless box-shaped case 8 is adhered to the insulating substrate 2 on which the semiconductor element 5 and leads 6 have been mounted. In FIG. 6(e), a gel-like filler 9 is injected to protect the semiconductor element 5, and a resin 10 is further injected thereon to seal it (for example, see Utility Model Application Publication No. 187354/1983). reference).
ところで、上記のような製造フローにおいて、リード７
と導体配線３との半田の接続を半導体部品搭載時に同時
に行うには、リード７の不安定性および治工具の使用等
から組立上複雑、かつ困難であり、また、端子の寸法精
度が得られず、り一ド７の出力方向を変更する場合には
、ケースの変更等を必要とするという問題が生じていた
。By the way, in the above manufacturing flow, lead 7
Simultaneously connecting the terminals and the conductor wiring 3 with solder when mounting the semiconductor components is complicated and difficult to assemble due to the instability of the leads 7 and the use of jigs and tools, and the dimensional accuracy of the terminals cannot be obtained. However, when changing the output direction of the lead 7, a problem arises in that the case must be changed.
この発明は、上記のような従来の問題点を解消するため
になされたもので、複数のリードを配設したリードブロ
ックを着脱自在に装着できるとともに、各リードの出力
方向を変更することができる半導体装置を得ることを目
的とするものである。This invention was made to solve the above-mentioned conventional problems, and it is possible to detachably attach a lead block with a plurality of leads, and also to change the output direction of each lead. The purpose is to obtain a semiconductor device.
この発明に係る半導体装置は、無底の箱体状のケースと
、このケースの底板を構成するように前記ケースの下部
に接着された放熱板と、この放熱板上に接着された導体
配線がなされた絶縁基板と、この絶縁基板上に搭載され
た半導体素子およびリードとを有する半導体装置におい
て、ケースを半導体素子を囲む主ケースと、この主ケー
ス内に装着可能としたフレーム構成の複数のリードを配
設したリードプロ・ツクとに分割して構成したものであ
る。A semiconductor device according to the present invention includes a bottomless box-shaped case, a heat sink bonded to a lower part of the case to constitute a bottom plate of the case, and a conductor wiring bonded on the heat sink. In a semiconductor device having an insulating substrate, a semiconductor element and a lead mounted on the insulating substrate, there is provided a main case surrounding the semiconductor element, and a plurality of leads having a frame structure that can be mounted inside the main case. It is divided into a lead pro and a lead pro.
この発明においては、半導体素子を取り囲む主ケースと
、この主ケースに接続される複数のリードが配置された
フレーム構成のリードブロックとに分割して構成したこ
とから、リードの出力方向を変更する場合でも、主ケー
スを変更することなく、容易に実現できる。In this invention, since the structure is divided into a main case surrounding the semiconductor element and a lead block having a frame structure in which a plurality of leads connected to the main case are arranged, it is possible to change the output direction of the leads. However, it can be easily realized without changing the main case.
以下、この発明の一実施例を図面について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図（ａｔ〜（ｆ）ζよこの発明の一実施例を示す半
導体装置の組立工程を示す図である。FIG. 1 (at to (f) ζ) is a diagram showing an assembly process of a semiconductor device showing an embodiment of the present invention.
まず、第１図（ａ）に示すように、第２図（ａ）と同様
に放熱板１上に絶縁基板（もしくは絶縁膜）２が接着さ
れ、その上に導体配線３がなされろ。First, as shown in FIG. 1(a), an insulating substrate (or insulating film) 2 is adhered onto a heat sink 1 in the same manner as in FIG. 2(a), and a conductor wiring 3 is formed thereon.
次に、第１図（ｂ）に示すように、絶縁基板２上の導体
配線３のパッド上にクリーム半田４を塗布後、半導体素
子５が搭載される０、また、導体配線３と半導体素子５
もしくは導体配線３同士での電気的接続を必要とするも
のは、ワイヤ６等で接続がなされる。次に、第１図（Ｃ
）に示すように、リードと導体配ｓ３との接続のため、
クリーム半田（前記クリーム半田４て使用する使用半田
温度以下の半田）１１を塗布し、絶縁基板２と、主ケー
スとを接続する接着剤１２を塗布する。次いて、第１図
（ｄ）に示すように、主ケース１３とこの主ケース７３
内に装着可能とした７レーム構成のリードブロック１４
をあらかじめ接続した上で絶縁基板２と主ケース１３と
の接着を行う（なお、主ケース１３とリードブロック１
４の取付法は主ケース１３に対しリードブロック１４は
上からでも下からのどちらでもかまわない）。また、半
導体素子５搭載のクリーム半田４の塗布を高温半田にて
実施した場合、す〜ド搭載のクリーム半田１１の塗布は
低温半田もしくは中温半田にて実施することになる。半
導体素子搭載のクリーム半田が中温半田の場合、リード
搭載のクリーム半田は低温半田にて実施することになる
、。Next, as shown in FIG. 1(b), after applying cream solder 4 on the pads of the conductor wiring 3 on the insulating substrate 2, the conductor wiring 3 and the semiconductor element 0 on which the semiconductor element 5 is mounted are applied. 5
Alternatively, if electrical connection between the conductor wirings 3 is required, the connection is made using wires 6 or the like. Next, Figure 1 (C
), for the connection between the lead and the conductor arrangement s3,
Cream solder (solder whose temperature is lower than that used for the cream solder 4) 11 is applied, and an adhesive 12 for connecting the insulating substrate 2 and the main case is applied. Next, as shown in FIG. 1(d), the main case 13 and the main case 73 are
A lead block 14 with a 7-frame configuration that can be installed inside the
are connected in advance, and then the insulating substrate 2 and the main case 13 are bonded together (the main case 13 and the lead block 1
4, the lead block 14 can be attached to the main case 13 either from above or from below). Furthermore, if the cream solder 4 on the semiconductor element 5 is applied using high-temperature solder, the cream solder 11 on the semiconductor element 5 is applied using low-temperature solder or medium-temperature solder. If cream soldering on semiconductor elements is medium temperature soldering, cream soldering on leads should be done at low temperature.
さらに、第１ｅ ｆｅ）に示すように、リードと絶縁基
板２の導体配線３との接続を行い、最後に第１図（［）
に示すように、第６図（６）と同様にゲル状充填物１５
を充填し、その上に樹脂１６が注入さねて密封されろ。Furthermore, as shown in Figure 1e fe), the leads are connected to the conductor wiring 3 of the insulating substrate 2, and finally, as shown in Figure 1 ([)
As shown in FIG. 6(6), the gel-like filling 15 is
The resin 16 is injected onto the resin 16 and sealed.
上記主フレーム１３とリードブロック１４の詳細を第２
図〜第５図について説明するつ第２図（ａ）、（ｂ）は
主ケース１３とリードブロック１４の斜視図をそれぞれ
示し、主ケース１３は、リード７が複数配設されたリー
ドブロック１４を着脱自在に装着できるようになってお
り、その装着法は、例えば接続部１７において、第３図
（ａ）〜（ｄｉに示すようにビス止め、凹凸の嵌合、あ
るいは舌片による係合等により装着できるようになって
いる。The details of the main frame 13 and lead block 14 are shown in the second section.
2A and 2B are perspective views of the main case 13 and the lead block 14, respectively. It is designed to be able to be attached removably, and the attachment method is, for example, at the connection part 17, as shown in FIGS. etc., so that it can be installed.
また、第４図（ａ）、（ｂ）はリードブロック１４の各
リード７の出力方向を変更した例を示すもので、その装
着法は、第３図と同様に行われている。4(a) and 4(b) show an example in which the output direction of each lead 7 of the lead block 14 is changed, and the mounting method is the same as that shown in FIG. 3.
第５図に装着法の一例を示す。１例えば主ケース１３便
の装着部に凸部１３ａを形成し、リードブロック１４側
に凹部１４ａを形成しておき、り一ドブロ・ツク１４を
主ケース１３に装着したとき、凹部１４ａに凸部１３ａ
が係合し、主ケース１３にリードブロック１４が着脱自
在に装着される。FIG. 5 shows an example of the mounting method. 1. For example, a convex portion 13a is formed on the mounting portion of the main case 13, and a concave portion 14a is formed on the lead block 14 side, and when the Dobro Tsuk 14 is attached to the main case 13, the convex portion 14a is formed 13a
are engaged, and the lead block 14 is detachably attached to the main case 13.
し発明の効果〕
以上説明したように、この発明は、ケースを半導体素子
を囲む主ケースと、この主ケース内に装着可能としたフ
し−ム構成の複数のリードを配設したリードブロックと
に分割して構成し、リードブロックを主ケースに装着し
たので、半導体素子を囲む主ケースと接続されるフレー
ム構成のリードブロックを変更するだけで組立てを変更
できるので、工程が簡単になり、リードの寸法精度が向
上する。また、主ケースを変更することなく、リードの
出力方向を変更できる等の効果が得られる。[Effects of the Invention] As explained above, the present invention includes a main case that surrounds a semiconductor element, and a lead block in which a plurality of leads in a frame structure that can be mounted inside the main case are arranged. Since the lead block is attached to the main case, the assembly can be changed simply by changing the lead block of the frame structure connected to the main case surrounding the semiconductor element, simplifying the process and attaching the lead block to the main case. Improves dimensional accuracy. Furthermore, effects such as being able to change the output direction of the leads can be obtained without changing the main case.
第１図はこの発明の一実施例を説明する半導体装置の組
立て工程の概要構成を模式的に示した図、第２図１８）
、（ｂ）はこの発明の主フし−ムとリードゴロ・ツクを
示す斜視図、第３図（ａ）〜（ｄ）はこの発明の主ケー
スとリードゴロνりとの装着法を示す概略図、第４図（
ａ）、（ｂ）はリードの出力方向を変えた装着法を示す
斜視図、第５図は装着法の具体例を示す概略図、第６図
１よ従来の半導体装置の組立工程を説明する図である。
図において、１は放熱板、２は絶縁基板、３は導体配線
、４はクリーム半田、５は半導体素子、６はワイヤ、７
はリード、１３は主ケース、１４はリードブロック、１
５はゲル状充填物、１６は樹脂、１７は接続部である。
なお、各図中の同一符号は同一または相当部分を示す。
代理人 大 岩 増 雄 （外２名）第１図
第２図
１７て廃那
第３図
（ａ）
１°′１７
第４図
第５図
］３
第６図Fig. 1 is a diagram schematically showing the general configuration of the assembly process of a semiconductor device explaining one embodiment of the present invention, and Fig. 2 (18)
, (b) is a perspective view showing the main frame and lead ball mount of the present invention, and FIGS. 3(a) to 3(d) are schematic diagrams showing how to attach the main case and lead ball holder of the present invention. , Figure 4 (
a) and (b) are perspective views showing a mounting method in which the output direction of the leads is changed, FIG. 5 is a schematic diagram showing a specific example of the mounting method, and FIG. 6 explains the assembly process of a conventional semiconductor device. It is a diagram. In the figure, 1 is a heat sink, 2 is an insulating substrate, 3 is a conductor wiring, 4 is cream solder, 5 is a semiconductor element, 6 is a wire, and 7
is the lead, 13 is the main case, 14 is the lead block, 1
5 is a gel-like filling, 16 is a resin, and 17 is a connecting portion. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1, Figure 2, Figure 17, Figure 3 (a) 1°'17 Figure 4, Figure 5] 3 Figure 6
Claims (1)
ように前記ケースの下部に接着された放熱板と、この放
熱板上に接着された導体配線がなされた絶縁基板と、こ
の絶縁基板上に搭載された半導体素子およびリードとを
有する半導体装置において、前記ケースを前記半導体素
子を囲む主ケースと、この主ケース内に装着可能とした
フレーム構成の複数のリードを配設したリードブロック
とに分割して構成し、前記リードブロックを前記主ケー
スに装着したことを特徴とする半導体装置。A bottomless box-shaped case, a heat sink bonded to the bottom of the case to form the bottom plate of the case, an insulating board with conductor wiring bonded onto the heat sink, and the insulating board. A semiconductor device having a semiconductor element and a lead mounted on a substrate, wherein the case is a main case surrounding the semiconductor element, and a lead block in which a plurality of leads are arranged in a frame structure that can be mounted inside the main case. 1. A semiconductor device characterized in that the semiconductor device is configured by being divided into two parts, and the lead block is attached to the main case.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33531790A JPH04196580A (en) | 1990-11-28 | 1990-11-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33531790A JPH04196580A (en) | 1990-11-28 | 1990-11-28 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04196580A true JPH04196580A (en) | 1992-07-16 |
Family
ID=18287171
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33531790A Pending JPH04196580A (en) | 1990-11-28 | 1990-11-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04196580A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010287726A (en) * | 2009-06-11 | 2010-12-24 | Fuji Electric Systems Co Ltd | Semiconductor device |
| CN105765716A (en) * | 2014-05-15 | 2016-07-13 | 富士电机株式会社 | Power semiconductor module and composite module |
-
1990
- 1990-11-28 JP JP33531790A patent/JPH04196580A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010287726A (en) * | 2009-06-11 | 2010-12-24 | Fuji Electric Systems Co Ltd | Semiconductor device |
| CN105765716A (en) * | 2014-05-15 | 2016-07-13 | 富士电机株式会社 | Power semiconductor module and composite module |
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