JPH03234047A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03234047A JPH03234047A JP3034290A JP3034290A JPH03234047A JP H03234047 A JPH03234047 A JP H03234047A JP 3034290 A JP3034290 A JP 3034290A JP 3034290 A JP3034290 A JP 3034290A JP H03234047 A JPH03234047 A JP H03234047A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- semiconductor chip
- substrate
- board
- cooling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000001816 cooling Methods 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims description 28
- 238000007789 sealing Methods 0.000 abstract description 4
- 239000002826 coolant Substances 0.000 abstract 1
- 238000005476 soldering Methods 0.000 abstract 1
- 239000000919 ceramic Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 4
- 239000012809 cooling fluid Substances 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- RVZRBWKZFJCCIB-UHFFFAOYSA-N perfluorotributylamine Chemical compound FC(F)(F)C(F)(F)C(F)(F)C(F)(F)N(C(F)(F)C(F)(F)C(F)(F)C(F)(F)F)C(F)(F)C(F)(F)C(F)(F)C(F)(F)F RVZRBWKZFJCCIB-UHFFFAOYSA-N 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔概要〕 半導体チップが基板に実装された半導体装置に関し。[Detailed description of the invention] 〔overview〕 Regarding semiconductor devices in which semiconductor chips are mounted on substrates.
冷却フィンの面積を大きくとって熱抵抗を低減し、チッ
プの置き換えが容易にできる構造を提供することを目的
とし。The purpose is to reduce thermal resistance by increasing the area of the cooling fins, and to provide a structure that allows for easy chip replacement.
表面に素子形成された半導体チップ（２）と、素子形成
面を上にして該半導体チップ（２）を搭載し、該半導体
チップ（２）と基板入出力端子（４）との間を結ぶ配線
が形成されている基板（１）と、該基板を貫通して該半
導体チップの裏面に熱的に接続される冷却フィン（５）
とを有するように構成する。A semiconductor chip (2) with elements formed on its surface, mounting the semiconductor chip (2) with the element forming side facing up, and wiring connecting the semiconductor chip (2) and substrate input/output terminals (4). a substrate (1) on which is formed, and a cooling fin (5) that penetrates the substrate and is thermally connected to the back surface of the semiconductor chip.
It is configured to have the following.
本発明は半導体チップが基板に実装された半導体装置に
関する。The present invention relates to a semiconductor device in which a semiconductor chip is mounted on a substrate.
発熱量の大きい半導体チップ、例えばＧａＡｓ ＩＣチ
ップを基板に高密度に実装して、コンピュータのＣＰυ
モジュール等に本発明を利用することができる。Semiconductor chips that generate a large amount of heat, such as GaAs IC chips, are densely mounted on a substrate to reduce the
The present invention can be applied to modules and the like.
従来構造は、半導体チップを基板上にフェイスダウンで
実装し、ヒートシンクとして冷却フィンをチップ上に積
み上げる構造をとっている。In the conventional structure, a semiconductor chip is mounted face down on a substrate, and cooling fins are stacked on top of the chip as a heat sink.
第３図は従来例を説明する断面図である。FIG. 3 is a sectional view illustrating a conventional example.
図において、セラミック基板ｌは半導体チップ２の配置
される位置の周囲にはチップのＩ１０パッドと接続する
ためのパッドが形成されており、これらのパッドは基板
のＩ１０端子まで、薄膜多層配線により導かれる。In the figure, a ceramic substrate 1 has pads formed around the position where a semiconductor chip 2 is placed for connection to the I10 pad of the chip, and these pads are connected to the I10 terminal of the substrate by thin-film multilayer wiring. It will be destroyed.
半導体チップ２はセラミック基板１上にフェイスダウン
でリード３を介してボンディングされている。A semiconductor chip 2 is bonded face down onto a ceramic substrate 1 via leads 3.
チップ２の裏面には冷却フィン８がろう付けされており
、矢印で示すエアの流れにより空冷される。Cooling fins 8 are brazed to the back surface of the chip 2, and are air-cooled by air flows shown by arrows.
又、チップ２はキャップ９により基ｊｌｉ ｌ上で封止
されてきる。Also, the chip 2 has been sealed on the base jli l by a cap 9.
この際、キャップ９は各冷却フィン８との間も封止しな
ければならず構造が複雑となる。At this time, the cap 9 must also be sealed with each cooling fin 8, making the structure complicated.
この構造では、封止が複雑で、空冷のため冷却効率が悪
く、チップの置き換えが殆ど不可能であるという欠点が
あった。This structure has the disadvantages that the sealing is complicated, the cooling efficiency is poor due to air cooling, and it is almost impossible to replace the chip.
本発明は、半導体チップが高密度に基板上に実装された
半導体装置において、冷却を液冷化できる構造にして熱
抵抗を低減し、封止とチップの置き換えが容易にできる
構造を提供することを目的とする。An object of the present invention is to provide a structure in which semiconductor chips are mounted on a substrate in a high density, with a structure that allows cooling to be liquid cooled to reduce thermal resistance and facilitate sealing and replacement of chips. With the goal.
上記課題の解決は９表面に素子形成された半導体チップ
（２）と、素子形成面を上にして該半導体チップ（２）
を搭載し、該半導体チップ（２）と基板入出力端子（４
）との間を結ぶ配線が形成されている基板（１）と、該
基板を貫通して該半導体チップの裏面に熱的に接続され
る冷却フィン（５）とを有する半導体装置により達成さ
れる。The solution to the above problem is to provide a semiconductor chip (2) with elements formed on its surface, and a semiconductor chip (2) with the element forming side facing up.
The semiconductor chip (2) and the board input/output terminal (4)
), and a cooling fin (5) that penetrates the substrate and is thermally connected to the back surface of the semiconductor chip. .
〔作用］
本発明は基板に貫通孔を開け、冷却フィンを基板に対し
て半導体チップと反対面に配置し且つ貫通孔を介して半
導体チップ裏面に熱的に接続することにより、下記の理
由による効果を利用したものである。[Function] The present invention has a through hole in the substrate, arranges the cooling fin on the opposite side of the substrate from the semiconductor chip, and thermally connects it to the back surface of the semiconductor chip through the through hole, thereby achieving the following effect. It uses the effect.
■ 冷却フィンは基板裏面にあるためチップの存在に邪
魔されることなく大面積化ができる。■ Cooling fins are located on the back of the board, allowing for a large area without being hindered by the presence of chips.
■ チップは冷却フィン上にフェイスアップに装着され
ているから、置き換えが容易である。■ The chip is mounted face-up on the cooling fins, making it easy to replace.
第１図（ａ）〜（Ｃ）は本発明の一実施例を説明する平
面図と断面図である。FIGS. 1(a) to 1(C) are a plan view and a sectional view illustrating an embodiment of the present invention.
図において、セラミック基板１は半導体チップ２が配置
される位置に図のようにテーバのついた貫通孔が開いて
いる。In the figure, a ceramic substrate 1 has a tapered through hole at a position where a semiconductor chip 2 is disposed as shown in the figure.
又、セラミック基板１はチップの配置される位置の周囲
にはチップのＩ１０パッドと接続するためのパッドが形
成されており、これらのパッドは基板の１辺に配設され
ている基板Ｉ１０端子４まで。Further, the ceramic substrate 1 has pads formed around the position where the chip is placed for connection to the I10 pad of the chip, and these pads connect to the board I10 terminal 4 arranged on one side of the board. to.
薄膜多層配線により導かれる。Guided by thin film multilayer wiring.
薄膜多層配線は本発明に特に関係がないので図示されて
いない。Thin film multilayer wiring is not particularly relevant to the present invention and is therefore not shown.
又、チップ２はフェイスアップに基板上に載せられ、チ
ップのパッドと基板のパッド間は１例えばり一ド３でＴ
ＡＢ （Ｔａｐｅ Ａｕｔｏｍａｔｅｄ Ｂｏｎｄｆｎ
ｇ）法によりボンディングされている。Also, the chip 2 is placed face-up on the substrate, and the distance between the pad of the chip and the pad of the substrate is 1, for example, 1 and 3.
AB (Tape Automated Bondfn
g) Bonded by a method.
裏面及び貫通孔内部のメタライズ層に半田により接合さ
れている。It is bonded to the back surface and the metallized layer inside the through hole by solder.
冷却フィン５は冷却流体が流れる方向に多数の溝が形成
されている。The cooling fins 5 have a large number of grooves formed in the direction in which the cooling fluid flows.
基板１の下部はハウジング６によりカバーされて、内部
を冷却流体としてフロリナート、水等が流される。The lower part of the substrate 1 is covered by a housing 6, and Fluorinert, water, or the like is flowed inside as a cooling fluid.
基板１の上部はチップ２を覆ってキャップ７で封止され
ている。The upper part of the substrate 1 covers the chip 2 and is sealed with a cap 7.
実施例の場合、熱抵抗はチン１１個当たり、チップにつ
いては０．０４°Ｃ／Ｗで、セラミック基板及びヒート
シンクについて０．５℃／Ｗの値が得られた。In the case of the example, the thermal resistance was 0.04°C/W for the chip and 0.5°C/W for the ceramic substrate and heat sink per 11 chips.
チップ上に空冷のヒートシンクをつけた従来例の熱抵抗
はセラミック基板及びヒートシンクについて２．７°Ｃ
／Ｗであった。The thermal resistance of the conventional example with an air-cooled heat sink attached to the chip is 2.7°C for the ceramic substrate and heat sink.
/W.
上記の測定結果から、従来例に比べて熱抵抗が低減され
ていることがわかる。The above measurement results show that the thermal resistance is reduced compared to the conventional example.
第２図は本発明の他の実施例を説明する斜視図である。FIG. 2 is a perspective view illustrating another embodiment of the present invention.
この例では、冷却フィン５Ａは第１図の個々の冷却フィ
ンを一体化して形成したもので、大抵の場合、チップは
基板接地であるのでこの実施例を採用することができる
。In this example, the cooling fins 5A are formed by integrating the individual cooling fins shown in FIG. 1, and since the chip is grounded to the substrate in most cases, this embodiment can be adopted.
勿論、この実施例の方が第１図の実施例より冷却効果は
大きい。Of course, this embodiment has a greater cooling effect than the embodiment shown in FIG.
従来例に比して実施例の利点は次のように要約すること
ができる。The advantages of the embodiment over the conventional example can be summarized as follows.
■ 封止が簡単である。■ Easy to seal.
■ チップの置き換えが容易である。■ Chip replacement is easy.
■ 液冷化が容易である。■ Easy to liquid cool.
■ チップサイズやチップ周囲のＩ１０パッドやキャッ
プの影響を受けることなく冷却フィンを配置できるので
、冷却効率の高い構造を採用することができる。■ Since cooling fins can be placed without being affected by the chip size or the I10 pads and caps around the chip, a structure with high cooling efficiency can be adopted.
以上説明したように本発明によれば、半導体チップが高
密度に基板上に実装された半導体装置において、冷却を
液冷化できる構造にして熱抵抗を低減し、封止とチップ
の置き換えを容易にできる構造が得られた。As explained above, according to the present invention, in a semiconductor device in which semiconductor chips are mounted on a substrate at high density, a structure that allows cooling to be liquid cooled reduces thermal resistance and facilitates sealing and chip replacement. A structure that can be obtained was obtained.
第１図（ａ）〜（Ｃ）は本発明の一実施例を説明する平
面図と断面図。
第２図は本発明の他の実施例（一体化構造の冷却フィン
）を説明する斜視図。
第３図は従来例の断面図である。
図において。
１はセラミック基板。
２は半導体チップ。
３はリード。
４は基板Ｉ１０端子。
５．５Ａは冷却フィン。
６は冷却流体のハウジング。
７はキャップ
（１２）平面図
尖施例の説明図
第１囚FIGS. 1(a) to 1(C) are a plan view and a sectional view illustrating an embodiment of the present invention. FIG. 2 is a perspective view illustrating another embodiment of the present invention (cooling fins having an integrated structure). FIG. 3 is a sectional view of a conventional example. In fig. 1 is a ceramic substrate. 2 is a semiconductor chip. 3 is the lead. 4 is the board I10 terminal. 5.5A is a cooling fin. 6 is a cooling fluid housing. 7 is the cap (12) Plan view Explanation diagram of the tip example 1st prisoner
Claims (1)
面を上にして該半導体チップ（２）を搭載し、該半導体
チップ（２）と基板入出力端子（４）との間を結ぶ配線
が形成されている基板（１）と、該基板を貫通して該半
導体チップの裏面に熱的に接続される冷却フィン（５）
とを有することを特徴とする半導体装置。A semiconductor chip (2) with elements formed on its surface, mounting the semiconductor chip (2) with the element forming side facing up, and wiring connecting the semiconductor chip (2) and substrate input/output terminals (4). a substrate (1) on which is formed, and a cooling fin (5) that penetrates the substrate and is thermally connected to the back surface of the semiconductor chip.
A semiconductor device comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3034290A JPH03234047A (en) | 1990-02-09 | 1990-02-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3034290A JPH03234047A (en) | 1990-02-09 | 1990-02-09 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03234047A true JPH03234047A (en) | 1991-10-18 |
Family
ID=12301162
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3034290A Pending JPH03234047A (en) | 1990-02-09 | 1990-02-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03234047A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007201334A (en) * | 2006-01-30 | 2007-08-09 | Kyocera Corp | Light emitting device, and lighting apparatus |
| JP2012142532A (en) * | 2010-12-15 | 2012-07-26 | Fujitsu Ltd | Semiconductor device, cooling device, and manufacturing method of cooling device |
| DE102019213956A1 (en) * | 2019-09-12 | 2020-12-24 | Vitesco Technologies GmbH | (Power) electronics arrangement with efficient cooling |
-
1990
- 1990-02-09 JP JP3034290A patent/JPH03234047A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007201334A (en) * | 2006-01-30 | 2007-08-09 | Kyocera Corp | Light emitting device, and lighting apparatus |
| JP2012142532A (en) * | 2010-12-15 | 2012-07-26 | Fujitsu Ltd | Semiconductor device, cooling device, and manufacturing method of cooling device |
| DE102019213956A1 (en) * | 2019-09-12 | 2020-12-24 | Vitesco Technologies GmbH | (Power) electronics arrangement with efficient cooling |
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