JPH04196449A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH04196449A JPH04196449A JP32803690A JP32803690A JPH04196449A JP H04196449 A JPH04196449 A JP H04196449A JP 32803690 A JP32803690 A JP 32803690A JP 32803690 A JP32803690 A JP 32803690A JP H04196449 A JPH04196449 A JP H04196449A
- Authority
- JP
- Japan
- Prior art keywords
- wiring layer
- insulating film
- pad
- semiconductor integrated
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 230000002093 peripheral effect Effects 0.000 claims description 10
- 238000000034 method Methods 0.000 abstract description 9
- 101100008047 Caenorhabditis elegans cut-3 gene Proteins 0.000 abstract 3
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 29
- 239000000758 substrate Substances 0.000 description 9
- 230000000694 effects Effects 0.000 description 5
- 230000001681 protective effect Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は半導体集積回路のパターン形状に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a pattern shape of a semiconductor integrated circuit.
［発明の概要］
本発明は、ボンディングワイヤーを接続する半導体集積
回路のボンディングパッド部において、半導体集積回路
製造過程に形成される保護膜 または、絶縁ｊ！（以下
絶縁膜と呼ぶ）の−部を、ボンディングワイヤーが接続
されるパッド部の配線層（以下パッド部の配線層と呼ぶ
）の形状に沿って除去し、パッド部の配線層の周辺部を
下方に向けることにより、パッド部の配線層周辺部分か
らのまくれを大幅に減少させると共にはがれ強度の大幅
な向上が図られ、半導体集積回路実装の品質の向上と、
回路パターン設計におけるボンディングパッドの形状
および、サイズ縮小への自由度が高まり、設計工数削減
、チップサイズの縮小によるコストダウンを実現したも
のである。[Summary of the Invention] The present invention provides a protective film or an insulating film formed during the manufacturing process of a semiconductor integrated circuit in a bonding pad portion of a semiconductor integrated circuit to which a bonding wire is connected. (hereinafter referred to as the insulating film) is removed along the shape of the wiring layer of the pad part (hereinafter referred to as the wiring layer of the pad part) to which the bonding wire is connected, and the peripheral part of the wiring layer of the pad part is removed. By facing downward, it is possible to significantly reduce the curling up of the pad portion from the peripheral portion of the wiring layer, and to significantly improve the peeling strength, thereby improving the quality of semiconductor integrated circuit packaging.
Bonding pad shape in circuit pattern design
In addition, the degree of freedom in size reduction has increased, reducing design man-hours and reducing costs by reducing chip size.
［従来の技術］
パッド部の配線層は、半導体集積回路製造過程で形成さ
れる保護膜 または、絶縁膜（以下絶縁膜と呼ぶ）上に
、設計された回路パターン形状を実現するのみであり、
パッド部の配線１と絶縁膜の接触によってはがれ強度を
確保するものであった。[Prior Art] The wiring layer of the pad portion only realizes a designed circuit pattern shape on a protective film or an insulating film (hereinafter referred to as an insulating film) formed during the manufacturing process of a semiconductor integrated circuit.
Peeling strength was ensured by the contact between the wiring 1 of the pad portion and the insulating film.
第２図は、本発明を使用しない従来の例を示す半導体集
積回路の断面図である。FIG. 2 is a sectional view of a conventional semiconductor integrated circuit that does not use the present invention.
１は半導体集積回路表面を保護し、パッド関口部が取り
除かれた保護膜、２は配線層間を絶縁、保護する絶縁膜
、４はボンディングワイヤーとの接続を取るパッド部の
配線層、５はパッド部の下方に位置する基板である。1 is a protective film that protects the surface of a semiconductor integrated circuit and from which the pad entrance part has been removed; 2 is an insulating film that insulates and protects between wiring layers; 4 is a wiring layer of a pad part that connects with a bonding wire; 5 is a pad This is the substrate located below the section.
第２図に示すように、従来のパッド部のはがれ強度は、
パッド部の配線層４と絶縁膜２の接触面積に依存するも
のであった。As shown in Figure 2, the peel strength of the conventional pad part is
This depended on the contact area between the wiring layer 4 and the insulating film 2 in the pad portion.
［発明が解決しようとする課題］
しかし、前述の従来技術では、パッド部の配線層のはが
れ強度は、絶縁膜とボンディングパッド部の配線材の接
触面積に比例するものであり、はがれ強度を確保するた
め、ボンディングパッドのサイズを大きくしなければな
らない。[Problems to be Solved by the Invention] However, in the above-mentioned conventional technology, the peeling strength of the wiring layer in the pad portion is proportional to the contact area between the insulating film and the wiring material in the bonding pad portion, and the peeling strength is ensured. Therefore, the size of the bonding pad must be increased.
また、はがれ強度を確°保するためにボンディングパッ
ドの必要面積を確保することは、高密度 及び、多入出
力回路を保有するパターンを設計する上での制限となる
。更に、パッド部の配線層の周辺部分のはがれ強度につ
いては、パッド部の全体強度とは別に、周辺部としての
はがれ強度を必要としており、端面のめくれから発生す
るパッド全体のはがれ強度の劣化は、パッド面積の拡大
だけでは改善につながらない等の問題点を有する。In addition, securing the necessary area for the bonding pad to ensure peel strength is a limitation in designing patterns that have high density and multiple input/output circuits. Furthermore, regarding the peeling strength of the peripheral part of the wiring layer of the pad part, the peeling strength of the peripheral part is required in addition to the overall strength of the pad part, and the deterioration of the peeling strength of the entire pad that occurs due to the curling of the end face is However, there are problems in that simply increasing the pad area does not lead to improvement.
そこで、本発明はこのような問題点を解決する゛もので
、その目的とするところは、パターン設計納期の短縮と
チップサイズの縮小によるコストの削減を実現し、品質
の寓い小型で低コストの半導体集積回路 及び、半導体
集積回路組立品を提供するところにある。Therefore, the present invention is intended to solve these problems.The purpose of the present invention is to shorten pattern design delivery time and reduce costs by reducing chip size. The company provides semiconductor integrated circuits and semiconductor integrated circuit assemblies.
［課題を解決するための手段］
本発明の半導体集積回路は、ボンディングパッド部にお
いて、パッド部の配線層の形状に合わせて絶縁膜の一部
を取り除き、配線層の周辺部を下方にむけることにより
周辺部からのめくれを排除し、積極的にはがれ強度を確
保することを特徴とする。[Means for Solving the Problems] In the semiconductor integrated circuit of the present invention, in the bonding pad portion, a part of the insulating film is removed in accordance with the shape of the wiring layer in the pad portion, and the peripheral portion of the wiring layer is directed downward. This feature eliminates peeling from the periphery and actively ensures peeling strength.
［実施例］
第１図は、本発明の１実施例を示す半導体集積回路の断
面図である。[Embodiment] FIG. 1 is a sectional view of a semiconductor integrated circuit showing one embodiment of the present invention.
１は半導体集積回路表面を保護し、パッド開口部が取り
除かれた保護膜、２は配線層間を絶縁、保護する絶縁膜
、３はパッド部の配線層の周辺部を下方に向けるために
絶縁膜を除去した部分、４はボンディングワイヤーとの
接続を取るパッド部の配線層、５はパッド部の下方に位
置する基板である。1 is a protective film that protects the surface of the semiconductor integrated circuit and has the pad opening removed; 2 is an insulating film that insulates and protects between wiring layers; and 3 is an insulating film that directs the peripheral part of the wiring layer in the pad part downward. 4 is the wiring layer of the pad portion for connection with the bonding wire, and 5 is the substrate located below the pad portion.
第１図に示すように、絶縁膜除去部３は、パッド部の配
線層４の周辺部を下方に向けるため絶縁膜２の一部をプ
ロセス処理の過程で除去することにより設ける。As shown in FIG. 1, the insulating film removal section 3 is provided by removing part of the insulating film 2 during a process in order to direct the peripheral part of the wiring layer 4 of the pad section downward.
絶縁膜２に絶縁膜除去部３が設けられることにより、パ
ッド部の配線層４が形成される課程において、パッド部
の配線層４の周辺部が絶縁膜除去部３に形成されること
となり、パッド部の配線層４が、パッド部の配線層４の
下に位置する絶縁膜２を覆うように形成され、平坦な絶
縁［！２の上にパッド部の配線層４を形成する場合より
はがれに対する強度の向上が図れる。By providing the insulating film removed part 3 in the insulating film 2, in the process of forming the wiring layer 4 of the pad part, the peripheral part of the wiring layer 4 of the pad part is formed in the insulating film removed part 3, The wiring layer 4 of the pad portion is formed to cover the insulating film 2 located below the wiring layer 4 of the pad portion, and is flatly insulated [! The strength against peeling can be improved compared to the case where the wiring layer 4 of the pad portion is formed on the wiring layer 2.
また、プロセス的な加工を加えることにより、絶縁膜除
去部３においてパッド部の配線層４と基板５の間で共晶
状態を生成して密接な接続を図り、第２図で示す従来の
半導体集積回路が、パッド部の配線層４と絶縁膜２の面
接触によって得るはがれ強度より、更に高いはがれ強度
を得ることが可能となり、ボンディングの品質向上が図
れる。In addition, by adding process-like processing, a eutectic state is created between the wiring layer 4 of the pad part and the substrate 5 in the insulating film removed part 3, and a close connection is achieved. It becomes possible for the integrated circuit to obtain a peel strength higher than that obtained by surface contact between the wiring layer 4 and the insulating film 2 in the pad portion, and the quality of bonding can be improved.
またボンディングパッドの面積が小さくても高いはがれ
強度が得られるため、ボンディングパッド自体の占める
面積を小さくすることができると同時に、ボンディング
パッドの形状に対する自白層が高まり、半導体集積回路
の設計条件が緩和され、チップの小型化や各人出力対応
が容易となりコストダウンが図れる。In addition, high peel strength can be obtained even if the area of the bonding pad is small, so it is possible to reduce the area occupied by the bonding pad itself, and at the same time, it increases the level of control over the shape of the bonding pad, easing the design conditions for semiconductor integrated circuits. This makes it easier to miniaturize the chip and accommodate individual outputs, leading to cost reductions.
ここで本発明を単純に利用して半導体集積回路を設計し
たのでは、複数のパッドと基板５は当然接続されること
となり、パッド間にショートが発生し、各パッドの信号
及び、電位の確保が不可能となる。この現象を回避す
るには、各パッド下の パッドと接続する基板領域の電
気的分離を行えばよい。If the present invention were simply used to design a semiconductor integrated circuit, a plurality of pads would naturally be connected to the substrate 5, and a short circuit would occur between the pads, making it difficult to ensure the signal and potential of each pad. becomes impossible. To avoid this phenomenon, it is sufficient to electrically isolate the area of the substrate connected to the pad below each pad.
この方法は図示していないが、ダイオードの逆方向構造
を造れば容易に実現可能である。Although this method is not shown, it can be easily realized by creating a reverse diode structure.
例えば、もとの基板領域を ｎ−領域とし、各パッド下
の パッドに接続される基板領域をＰ十拡散層とする方
法、また、Ｐ〜領領域する方法が考えられる。For example, a method can be considered in which the original substrate region is made into an n- region and the substrate region connected to the pads below each pad is made into a P+ diffusion layer, or a method is made into a P- region.
この両者の方法は、半導体集積回路の製造工程で容易に
実現可能である。但し、もとの基板の電位と同等のパッ
ドについては、この処理が不要であることは言うまでも
ない。Both methods can be easily implemented in the manufacturing process of semiconductor integrated circuits. However, it goes without saying that this process is not necessary for pads that have the same potential as the original substrate.
ＰＮジャンクション構造を有する場合は、入力の静電気
に対しても吸収することが可能であり、静電気耐圧の向
上と言った効果も得られる。When the device has a PN junction structure, it is possible to absorb input static electricity, and the effect of improving the static electricity withstand voltage can also be obtained.
また、ジャンクション領域を拡散とすることにより、実
行的にコンデンサとしての効果を持たせることも可能で
ある。Further, by making the junction region diffused, it is possible to effectively provide the effect as a capacitor.
以上、ボンディングパッド部が１層配線の例を示したが
、多層配線においても同様の効果を期待できる。Although the example in which the bonding pad portion has a single-layer wiring has been described above, the same effect can be expected in a multi-layer wiring.
［発明の効果］
以上述べたように本発明によれば、パッド部の配線層の
周辺部を下方に向ける事により、ボンディングパッドサ
イズの縮小が可能となり、従来と同様のチップサイズで
の多入出力の対応による付加価値の向上 または、チッ
プの小型化による低コスト化につながると共に、半導体
集積回路チップの品質向上と、ボンディング品質の高い
半導体集積回路を提供出来るという効果を有する。[Effects of the Invention] As described above, according to the present invention, by directing the peripheral portion of the wiring layer of the pad portion downward, the bonding pad size can be reduced, and multiple inputs can be made with the same chip size as before. Improvement in added value by matching outputs Or, it leads to cost reduction by miniaturizing the chip, and has the effect of improving the quality of semiconductor integrated circuit chips and providing semiconductor integrated circuits with high bonding quality.
第１図は、本発明の１実施例を示す半導体集積回路の主
要断面図。
第２図は、本発明を使用しない従来の例を示す半導体集
積回路の断面図。
１０１．半導体集積回路表面の保護膜
２１１．絶縁膜
３１．、パッド部の配線層と下方の基板を接続するため
に絶縁膜を除去した部分
４１１．ボンディングワイヤーとの接続を取るパッド部
の配線層
５・ ・・基板
以 上
出願人 セイコーエプソン株式会社
代理人 弁理士 鈴木喜三部 他１名
第１図
第２図FIG. 1 is a main cross-sectional view of a semiconductor integrated circuit showing one embodiment of the present invention. FIG. 2 is a sectional view of a conventional semiconductor integrated circuit that does not use the present invention. 101. Protective film 211 on the surface of the semiconductor integrated circuit. Insulating film 31. , a portion 411 where the insulating film is removed to connect the wiring layer of the pad portion to the substrate below. Wiring layer 5 of the pad part for connection with the bonding wire... Above the board Applicant: Seiko Epson Co., Ltd. Agent Patent attorney: Kizobe Suzuki and 1 other person Figure 1 Figure 2
Claims (1)
ド部の配線層の形状に合わせて絶縁膜の一部を取り除き
、パッド部の配線層の周辺部を下方に向けることにより
はがれ強度向上させる構造を有する事を特徴とする半導
体集積回路。In bonding pads for semiconductor integrated circuits, a part of the insulating film is removed in accordance with the shape of the wiring layer in the pad part, and the peripheral part of the wiring layer in the pad part is directed downward to improve peel strength. Semiconductor integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32803690A JP2910231B2 (en) | 1990-11-28 | 1990-11-28 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32803690A JP2910231B2 (en) | 1990-11-28 | 1990-11-28 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04196449A true JPH04196449A (en) | 1992-07-16 |
| JP2910231B2 JP2910231B2 (en) | 1999-06-23 |
Family
ID=18205800
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32803690A Expired - Lifetime JP2910231B2 (en) | 1990-11-28 | 1990-11-28 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2910231B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8017959B2 (en) | 2006-02-17 | 2011-09-13 | Hitachi, Ltd. | Light source and liquid crystal display device using the same |
-
1990
- 1990-11-28 JP JP32803690A patent/JP2910231B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8017959B2 (en) | 2006-02-17 | 2011-09-13 | Hitachi, Ltd. | Light source and liquid crystal display device using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2910231B2 (en) | 1999-06-23 |
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