JPH04196351A - Multichip semiconductor device - Google Patents

Abstract

PURPOSE:To enable a logic circuit element provided with a large number of terminals and a large number of memories to be easily superposed and to enlarge a multilayer type multichip semiconductor device in scope of application by a method wherein semiconductor elements connected through a tape carrier method are connected to a multilayer printed wiring board provided with through-holes, and the printed wiring board is made to serve as a spacer. CONSTITUTION:Semiconductor chips are electrically connected to a film carrier tape, and two or more semiconductors are superposed interposing a multilayer printed wiring board 9 as a spacer between them to constitute a multilayer type semiconductor module. That is, a logic circuit element provided with a large number of non-common terminals and a large number of memories are using a multilayer printed wiring board as a spacer 9. By this setup, semiconductor elements can be freely superposed independent of their kinds, and these elements can be mixedly mounted, so that the superposed semiconductor elements can be used as a multilayer type multichip semiconductor device wide in a scope of application, and moreover a process where outer leads are formed and cut off can be dispensed of, in result a multilayer type multichip semiconductor device can be manufactured at a low cost.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multi-chip semiconductor device in which tape carrier type semiconductor elements are stacked.

[Conventional technology]

Conventional stacked type multi-chip semiconductor devices, for example, connect SRAM, which is a type of memory, using a tape carrier method, form the outer lead portion of the common terminal of each memory according to the height of each layer, and overlap the leads. Connect to the electrode on the board. For chip selection of non-common terminals, outer leads are prepared on the tape according to the number of memories to be stacked, and all the outer leads are cut off one by one for each layer, leaving only one outer lead. As a result, a method has been adopted in which memories are made independent for each layer and connected to electrodes on the substrate. By the above method, an expansion memory board for a computer with a mounting density more than doubled has been realized. In addition,
As a device of this kind, the Hybrid Microelectronics Association, M.E.N.S.
9th year) Pages 86 to 88 (Hybrid Microelectronics Association, MES'89 3rd My 3rd Microelectronics Symposium Theory 89)
pp.

86-88).

[Problem to be solved by the invention]

In the above conventional technology, when stacking semiconductors that have a large number of terminals and a small number of terminals that can be shared, such as logic circuit elements, or when stacking a large number of memories, it is necessary to form and cut non-common terminals. No consideration was given to the large number of semiconductor devices, and there were restrictions on the type and number of semiconductor elements that could be stacked, limiting the range of applications as a stacked multi-chip semiconductor device. In addition, the number of molds required for the forming and cutting process of the outer sheet increases, resulting in an increase in cost.

An object of the present invention is to solve the problems of the prior art described above, and to provide a method for easily stacking logic circuit elements with a large number of terminals and a large number of memories, thereby expanding the scope of application of stacked multi-chip semiconductor devices. .

[Means for Solving the Problems 2] The above object is achieved by connecting semiconductor elements connected by a tape carrier method onto a multilayer printed wiring board having through holes, and using this board as a spacer.

[Effect]

In the present invention, the non-common terminals of a large number of memories are routed through the through holes of the multilayer printed wiring board on a conductor layer within the board, and the non-common terminals are made independent and connected to the lower layer. This eliminates the need for processing non-common terminals during stacking, that is, forming and cutting the outer leads. Further, the number of conductor layers and the number of through holes are increased according to the number of non-common terminals, and the terminals of the logic circuit element are separated into conductor layers and made independent.

This makes it possible to stack logic circuit elements with a large number of non-common terminals.

[Embodiment C] A first embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a perspective view showing details of a first embodiment of a stacked multi-chip semiconductor device. 2 is a plan view and a vertical sectional view of the stacked multi-chip semiconductor device shown in FIG. 1.

FIG. 3 is a diagram showing the entire hardware configuration of an electronic computer including a stacked multi-chip semiconductor device. In FIGS. 1 and 2, the top layer consists of a main processor 1 as a logic circuit element, a main memory 2 as a storage element, and a floating point processor 3 as a logic circuit element. Each semiconductor element is electrically connected to bumps 4 formed on each semiconductor element by a tape carrier method and inner leads 6 on a tape carrier 5, respectively. Further, a resin material 7 is applied as a protective coating to the surface of the semiconductor element and the side surfaces of the semiconductor element including the inner lead portion.

Each outer lead 8 on the carrier tape is electrically connected to an electrode pattern on a spacer 9 made of a multilayer printed wiring board and routed through each conductor layer within the board. The spacers are electrically connected by through holes 10, forming a stacked multi-chip semiconductor device. The multilayer printed wiring board used for spacers consists of a signal layer, a power supply layer, a ground layer, and through holes.The number of conductor layers and through holes increases according to the number of input/output pins, and It constitutes a data bus line for data exchange. In FIG. 3, the electronic computer is comprised of a stacked multi-chip semiconductor device in which a main processor and a main memory are stacked, a communication control processor, an input/output control processor, a display controller, a system bus, and the like.

In the above-described stacked multi-chip semiconductor device, instructions to be executed by the main processor are read from the main memory in the lower layer via the data bus line in the multilayer printed wiring board, which is a spacer. When the main memory side receives a read instruction from the main processor side, it transfers the necessary instructions. The main processor side decodes the read instructions and
Execute. At that time, if data in the main memory is required, it is further read from the main memory. Finally, the main processor writes the execution result to the main memory and repeats the above routine. Also, when performing floating-point calculations, the main processor sends the necessary instructions and data to the lowest-level floating-point processor via the data bus line.
Performs calculation processing.

At this time, the main processor is in charge of overall management of data exchange between each element. The stacked multi-chip semiconductor device as described above issues instructions to the communication control processor via the system bus to exchange data with other electronic computers, and issues instructions to the input/output control processor to communicate with input and output devices. exchange data. According to this embodiment,
Logic circuit elements and memory elements having a large number of input/output terminals can be stacked together, and the planar packaging density can be reduced to 1/4 or less. Further, forming and cutting processes for the outer lead are not required.

Next, a second embodiment of the present invention will be described using FIGS. 4 and 5. FIG. 4 is a perspective view showing details of a second embodiment of the stacked multi-chip semiconductor device. Further, FIG. 5 is a longitudinal sectional view of the stacked multi-chip semiconductor device of FIG. 4. In FIG. 4, the control module consists of a central processing semiconductor device 11, an internal storage semiconductor device 12, and an input/output control semiconductor device 13, and the internal storage semiconductor device has a structure of a stacked multi-chip semiconductor device. ing.

In FIG. 5, each semiconductor memory element is connected to bumps on the element by a tape carrier method, as in the first embodiment.
The inner leads on the tape carrier are electrically connected to each other. Further, a resin material is coated on the surface of the semiconductor element. Each outer lead on the carrier tape is electrically connected to an electrode pattern on a spacer made of a multilayer printed wiring board. The spacers are electrically connected through through holes to form a stacked memory module. In the multilayer printed wiring board used for the spacer, as the number of stacked semiconductor elements increases, the number of chip select terminals as non-common terminals increases, so the number of through holes in the spacer increases accordingly. A stacked multi-chip semiconductor device is constructed by mounting a plurality of these stacked memory modules on a printed wiring board.

In the internal storage semiconductor device having the structure of the stacked multi-chip semiconductor device described above, a semiconductor storage element in a specific layer is selected by a chip select command coming from the central processing semiconductor device via a through hole in the multilayer printed wiring board. , data is written from an external input device via the input/output control semiconductor device. The internal storage semiconductor device stores data until the next read command is received from the central processing semiconductor device, and after receiving the read command, transfers the previous data to the output device via the input/output control semiconductor device. Repeat the above routine. According to this embodiment,
A large number of semiconductor memory elements can be stacked on the internal memory semiconductor device, and the planar packaging density can be reduced to 1/4 or less. In addition, since the capacity of the internal storage semiconductor device can be increased by more than four times, it is possible to process a large amount of data at once, and the number of inputs and outputs between the input/output control semiconductor device and the internal storage semiconductor device is reduced. The overall efficiency of the control module is increased. Furthermore, the process of forming and cutting the outer lead becomes unnecessary.

Next, a third embodiment of the present invention will be described using FIG. 6.

FIG. 6 is a perspective view showing details of a third embodiment of the stacked multi-chip semiconductor device. In FIG. 6, the processor element 14 of the parallel electronic computer consists of a processor and a large-capacity memory, each of which has the structure of a stacked multi-chip semiconductor device as in the first embodiment. That is, the processor and memory are electrically connected to bumps on the elements and inner leads on the tape carrier using a tape carrier method. Further, a resin material is coated on the surface of the semiconductor element.

Each outer lead on the carrier tape is electrically connected to an electrode pattern on a spacer made of a multilayer printed wiring board, and is routed through each conductor layer within the board. Each space is electrically connected by a through hole, forming a stacked multi-chip semiconductor device. The multilayer printed wiring board used for spacers consists of a signal layer, a power supply layer, a ground layer, and through holes.The number of conductor layers and through holes increases according to the number of input/output bins, and It constitutes a data bus line for data exchange. The entire parallel electronic computer has a structure in which a plurality of the above-mentioned processor elements are connected by a crossbar switch 15.

In the processor element having the structure of the above-mentioned stacked multi-chip semiconductor device, the processor uses a chip select command to select a semiconductor memory element in a specific lower layer via a data bus line in a multilayer printed wiring board, which is a spacer. , input/output of calculation results is performed. Once the arithmetic processing has finished, each processor element asynchronously transfers the arithmetic results to all other processor elements via the crossbar switch. At this time, each processor element has the function of relaying data. As described above, according to this embodiment, logic circuit elements and memory elements having a large number of input/output terminals are mixed and stacked, and the planar packaging density is reduced to 1/2.
By reducing the size to 4 or less, a large number of processor elements can be implemented, and the arithmetic processing speed of the entire computer improves.

〔Effect of the invention〕

According to the present invention, logic circuit elements with many non-common terminals and a large number of memories can be stacked using spacers of a multilayer printed wiring board, so there are no restrictions on the types of semiconductor elements that can be stacked, and these elements can be stacked. It becomes possible to stack them in a mixed manner, which has the effect of providing a wide range of applications as a stacked multi-chip semiconductor device. Further, the forming and cutting steps of the outer lead are not required, and there is an effect that a low-cost stacked multi-chip semiconductor device can be provided.

[Brief explanation of the drawing]

FIG. 1 is a perspective view showing details of the first embodiment of the application method of a stacked multi-chip semiconductor device, FIG. 2 is a diagram showing the stacked multi-chip semiconductor device of FIG. 1, and FIG. 3 is a stacked type multi-chip semiconductor device. A configuration diagram of the entire hardware of a computer including a multi-chip semiconductor device, FIG. 4 is a perspective view showing details of a second embodiment of the application method of the stacked multi-chip semiconductor device, and FIG. FIG. 6 is a perspective view showing details of a third embodiment of the application method of the stacked multi-chip semiconductor device. l...Main processor 2...Main memory 3.
...Floating point processor 4...Bump 5...Tape carrier 6
...Inner lead 7...Resin material 8...Outer lead 9...Spacer 10...Through hole 11...Semiconductor device for central processing 12...Semiconductor device for internal storage 13... Input/output control semiconductor device 14... Processor element 15... Crossbar switch study 1 Figure 42, j J l (
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Claims (1)

[Claims] 1. In a main module of an electronic computer consisting of a main processor, a floating point processor, a main memory, etc., each semiconductor chip is electrically connected to a film carrier tape and a spacer of a multilayer printed wiring board is interposed. A multi-chip semiconductor device characterized by using a stacked semiconductor module structure in which two or more semiconductor modules are stacked. 2. In a control module consisting of a semiconductor device for central processing, a semiconductor device for internal storage, and a semiconductor device for input/output control, a spacer of a multilayer printed wiring board is interposed in the semiconductor part for internal storage to vertically connect the memory. 2. The multi-chip semiconductor device according to claim 1, wherein the multi-chip semiconductor device is formed by stacking more than one chip. 3. A claim characterized in that, in a parallel electronic computer comprising a plurality of processors, memories, crossbar switches, etc., two or more multilayer printed wiring boards with built-in data bus lines are stacked vertically using them as spacers. The multi-chip semiconductor device according to item 1.