JPH04196315A - Formation of fine contact hole of semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to form a fine contact hole by a method wherein a resist pattern, larger than the target contact hole diameter, is formed on a polysilicon layer, the polysilicon layer is etched in taper form, and a silicon oxide film is anisotropically etched using the above-mentioned taper. CONSTITUTION:After polysilicon 3 has been deposited on a silicon oxide film 2, a resist pattern 4, which is larger than the target contact hole l2, is formed and the polysilicon pattern 4 is etched in taper shape using the resist 4 as a mask. Also, the silicon oxide film 2 is anisotropically etched, and the contact hole is etched using the above-mentioned taper. As a result, the contact hole, having the diameter of 0.5mum or smaller, can be formed even when the existing i-line stepper is utilized by combining the thickness of the polysilicon and the condition of etching.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for forming fine contact holes in semiconductor devices, particularly semiconductor memory devices.

(Prior art) Reducing the contact hole diameter is essential for increasing the degree of integration of semiconductor storage devices, and 4 megabit dynamic random access memory (4 megabit dynamic random access memory), which is a typical semiconductor storage device, is essential.
4MbDRAM) is about 0.8μm, 16MbD
A contact hole of about 0.5 μm is required for a RAM, and a contact hole of about 0.35 μm is required for a 64 Mb DRAM.

A conventional contact hole is formed by coating a silicon oxide film 2 covering a word line 1 on a semiconductor substrate, for example, a silicon substrate, with renost 3, as shown in FIG. 2.
After exposing the resist 3 using a reduction projection type exposure machine (stepper), the silicon oxide film is anisotropically etched using fluorocarbon plasma or the like using the resist 3 as a mask and removed by developing with an organic solvent (see Fig. 2b). Figure C), remove the resist with 02 plasma etc. (Figure 2 d)
This is especially true.

Here, since the diameter of the contact hole is almost determined by the process shown in FIG. 2(b), it is necessary to expose and develop the resist to a minute size in order to form a minute contact hole. In other words, the resolution of the stepper needs to be about the same as the required contact hole diameter.

Chipper resolution, λ: wavelength of light source, NA: numerical aperture of lens, K: coefficient 11 determined by Rennost process
Normally, it is expressed as 08), so to form a resist pattern with a diameter of 0.5 #1, N A = 1M of about 0.5.
Stepper (wavelength 365 urn) still N, h =
0.4 KrF excimer laser stepper (
A wavelength of 248 nm) is required.

(Problem to be solved by the invention) However, among the methods described above, ii mischipper-id 0
．． Since it is not possible to form a resist pattern with a diameter of approximately 35 μm, it is not possible to form the desired fine contact hole.

'1 For the KrF excimer laser stepper, the NA
=0.35μ by using a lens of about O855
Although it is possible to form a pattern with a length of approximately 10 mm, the lifespan of the KrF excimer laser is as short as 106 cm, making it unsuitable for mass production.
– positioning accuracy is about the same as the contact hole diameter.
．． Since it is 3 μm, there is a high risk of pattern displacement.

An object of the present invention is to provide a method for forming a contact hole of 05 μm or less, which is required in a semiconductor memory device of 16 Mb DRAM or later, for example.

(Means for Solving the Problems) This invention provides a micro contact hole forming method in which polysilicon is deposited on a silicon oxide film and then a resist having a size larger than the target contact hole diameter is formed.
The polysilicon is etched into a tapered shape using the resist as a mask, and the silicon oxide film is etched anisotropically. This taper is used to etch a contact hole.

(Function) According to this method, by combining the polysilicon film thickness and etching conditions, contact holes having a diameter of 0.5 microns or less can be formed even when using an existing i-line stepper.

(Example) FIG. 1 is a process diagram showing an example of the method of the present invention.

In FIG. 1, polysilicon 3 is deposited on a silicon oxide film 2 covering wiring 1, for example, word line 1, on a wafer, which is a silicon substrate, for example (FIG. 1a).

Next, a resist 4 is formed on the polysilicon layer 3, exposed using a suitable mask, and developed (FIG. 1b). Next, polysilicon layer 3 is taper-etched (FIG. 1C). Next, the silicon oxide film 2 is anisotropically etched using the silicone groove of the polysilicon layer 3 (FIG. 1d). Then, the resist 4 is removed using 02 plasma or the like (FIG. 1e).

It consists of Note that the steps shown in FIG. 1C and FIG. 1D are performed continuously under the same etching conditions using fluorocarbon plasma.

The thickness d1 of the deposited polysilicon layer 3 (FIG. 1a) and the dimension 11 of the resist 4 (FIG. 1b) are determined by the thickness d1 of the deposited polysilicon layer 3 (FIG. 1a) and the dimension 11 of the resist 4 (FIG. 1b). The treatment may be carried out under conditions that provide a good selectivity to the membrane. Such etching can be performed, for example, at a pressure of 3
50 m Torr, etching gas HBr/He
= 100/1008 CCM, a high frequency power supply frequency of 13.56 MHz, a high frequency power supply power of 250 W, an upper electrode coolant temperature of 40°C, and a lower electrode coolant temperature of 40°C.

The target contact hole diameter 12 (Fig. 1d) depends on the etching conditions, and is 11=12+2φ1/lan.
Satisfies θ. However, 11 is the diameter of the Lennost mask, dl
is the film thickness of the polysilicon layer 3, and θ is the taper angle.

For example, when 12 = 0.351 tm, the etching conditions are set to a pressure of 0.6 Torr using a parallel plate type etching device.
Etching gas Ar/CHF, /CF4=800/
20/20 SCCM.

High frequency power supply frequency 380 kHz, high frequency power supply room cuff 50W, electrode spacing 9 mm, upper electrode refrigerant temperature 20°C
, if the lower electrode coolant temperature is -20°C, the Chi/F-angle θ of polysilicon is 45°, so if d1 = 0.1 μm, '1-CL 55 μm, dl-0.2 μm
, then it is sufficient to set l1=0.75 μm.

Similarly, when t2 = 0.35 μm, the etching conditions were set to 1.5 μm using a parallel plate type etching device. OTorr,
Etching gas Ar/CHF″3/C’F4=800
/80/80. High frequency power supply frequency 380 kHz, high frequency power supply type cuff 50W.

Assuming that the electrode spacing is 91II11, the upper electrode coolant temperature is 20°C, and the lower electrode coolant temperature is -20°C, the taper angle θ of polysilicon is 55°, so if d1 = 0.1 μm, then 1
= 0.481"rn -62-0.2am then z
It is sufficient to set 1=0.62 μm.

In this example, after depositing polysilicon, as shown in FIG.
After performing the following series of steps (see Figure 1), after doping polysilicon with impurities such as phosphorus (P),
b) It is possible to achieve the same effect by performing the following series of steps.

(Effect of the invention) According to the present invention as described in detail above.

After depositing polysilicon on the silicon oxide film, a resist pattern with dimensions larger than the target contact diameter is formed, and the polysilicon is etched into a tapered shape, and the contact hole is etched under the conditions that the silicon oxide film is etched anisotropically. By combining the polysilicon film thickness and etching conditions, contact holes with a diameter of less than a micron, which is required for semiconductor memory devices such as 64 Mb DRAM, can be formed using existing i-line etching methods. It can be formed using stainless steel.

It is hoped that this will solve the practical problems associated with the KrF excimer laser process and establish a highly practical contact hole forming process.

[Brief explanation of the drawing]

FIG. 2 is a process diagram showing a conventional contact hole forming method. FIG. 1 is a process diagram showing a method of the present invention. 1... Wiring, 2... Silicon oxide film, 3... Polysilicon layer, 4... Renost. -/-2 f-2 Figure 1 (Beat 1) 3 Polysilicon 41 Nose Shock Figure 1 (Beat 2)

Claims (1)

[Claims] A polysilicon layer is deposited on a silicon oxide film for interlayer insulation formed on a semiconductor substrate, a resist pattern with a dimension larger than the target contact diameter is formed on this polysilicon layer, and this is used to deposit the polysilicon layer. 1. A method for forming a fine contact hole in a semiconductor device, which comprises etching a silicon layer into a tapered shape and using this taper to anisotropically etch a silicon oxide film to form a contact hole.