JPH04196121A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a gate insulating film from being destroyed by a charge at an ion implantation operation by a method wherein the charge which is generated when a source or a drain is formed escapes to a semiconductor substrate from a region which comes into contact with a gate electrode. CONSTITUTION:A LOCOS 102, a silicon oxide film 103 and the like are formed on a semiconductor substrate 101; after that, a polycrystalline silicon film 105 is deposited on the substrate 101; P (phosphorus) ions 107 as N-type impurity ions are diffused into the film 105 and into the substrate 101 coming into contact with the film 105. A region to be used as a gate electrode and a region at the film 105 on the substrate 101 connected to the gate electrode are patterned and etched. Then, an opening is made in order to form a high-concentration impurity diffusion layer for a source and a drain; ions are implanted; a resist is removed; after that, an interlayer insulating film 108 is deposited. Thereby, a charge generated when the source or the gate is formed is not accumulated in the gate electrode and escapes to the substrate 101 from a region coming into contact with the gate electrode. As a result, it is possible to prevent a gate insulating film from being destroyed and to enhance the reliability of the title device.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing an MO3 type semiconductor device, and particularly to a method for forming a gate electrode.

[Prior Art] A conventional method for forming a gate electrode is to deposit polycrystalline silicon on a gate insulating film formed on a semiconductor substrate without etching or sowing the gate insulating film.
After leaving only the gate electrode of the transistor, ion implantation was performed to form the source and train of the MO3 transistor.

[Problem to be Solved by the Invention] However, when ion implantation is performed to form a source or drain, charges generated during ion implantation are accumulated in the gate electrode, and the gate insulation under the gate electrode is There is a problem that the membrane is destroyed.

SUMMARY OF THE INVENTION An object of the present invention is to solve these problems, and to provide a method for manufacturing semiconductor devices that is less likely to cause defects by preventing charges during ion implantation from destroying the gate insulating film under the gate electrode. It is about providing.

[Means for Solving the Problems] The present invention includes a step of etching a part of a gate insulating film formed on an element formation region on a semiconductor substrate, and a step of depositing polycrystalline silicon on the semiconductor substrate. and MOS)
the polycrystalline silicon in the region that will become the gate electrode of the transistor; the polycrystalline silicon that covers the region where a part of the gate insulating film has been etched; and the MO3) the region that will become the gate electrode of the transistor and the gate insulating film. Etching the polycrystalline silicon to leave a region of polycrystalline silicon that connects the etched regions, and then performing ion implantation to form the source and drain of the MOS (MOS) radiator. and a step of etching the polycrystalline silicon covering the region where the gate insulating film is partially etched.

[Example] FIGS. 1(a) to 1(1) are cross-sectional views of a semiconductor substrate in an example of the present invention, and steps related to gate electrode formation will be described in detail below.

First, LOGOS 102 is formed on a semiconductor substrate, and an activated region and a non-activated region are divided. (Figure 1(a)
)) Next, the semiconductor substrate was subjected to steam oxidation at a temperature of 850°C for 2
0 minutes, film thickness 200 silicon oxide film 1.03,
103a is formed. (Fig. 1(b)) Then, after forming a hole in a part of the region where polycrystalline silicon will not remain as a gate electrode in the future by photolithography, wet etching is performed with HF (hydrofluoric acid) to form a hole in the region. The upper silicon oxide film 103a is removed, and then the resist l-104 is removed. (FIGS. 1(C) to (d)) Next, after depositing a polycrystalline silicon film 105 on the semiconductor substrate by the CVD method, a certain P (phosphorous) ion 107 is multiplied with N-type impurity ions. Crystalline silicon film 10
5, P (phosphorous) ions are diffused into the silicon substrate 101 in contact with the polycrystalline silicon film 105.

(FIGS. 1(e) to (f)) Then, by photolithography, the region that will become the gate electrode and the region of the polycrystalline silicon film on the silicon substrate connected to the gate electrode are patterned. The silicone film was heated to 100mTor with SF6 and Fronco, 14 gases.
Etching is carried out under a pressure of r. (FIG. 1(g)) Next, holes are formed by photolithography in order to form high concentration impurity diffusion layers for the source and drain.

Then, for N channel, P (phosphorus) or A,
Perform s (arsenic) ion implantation, and in the case of P channel, B
(boron) or BF2 ion implantation.

Next, after removing the resist, patterning was performed by photolithography so that only the gate electrode remained, and the polycrystalline silicon film other than the gate electrode was formed with SF6 and '70-11.
100 mT with the gas from step 4.

Etching is carried out under a pressure of rr.

Then, after removing the resist, an interlayer insulating film is deposited. (FIG. 1(h)) After that, formation is performed in the same manner as in the case of forming a normal MOS transistor.

On the semiconductor substrate formed in this manner, charges generated when forming the source or drain are not accumulated in the gate electrode, but leak into the silicon substrate from the region in contact with the gate electrode. Therefore, no potential difference occurs between the gate electrode and the silicon substrate, and dielectric breakdown of the gate insulating film under the gate electrode is unlikely to occur.

[Effects of the Invention] As described above, according to the method of manufacturing a semiconductor device of the present invention, the gate insulating film of the MOS transistor is less likely to be destroyed, so that the yield of the product is improved. Furthermore, since the gate insulating film is less damaged, the reliability of the device is increased.

[Brief explanation of the drawing]

6- FIGS. 1(a) to 1(h) are cross-sectional views showing the method for manufacturing a semiconductor device of the present invention. 101 , , , , , Semiconductor substrate 102 , , ,
,,, LOG O5103,103a ,,,
Silicon oxide film 104, 106, Resist 105, Polycrystalline silicon 107
,,,,,,, N-type ion 10B ,,,,,,,,
Interlayer insulation film and above Applicant Seiko Epson Co., Ltd. agent Patent attorney Kisanbu Meiki (1 other person) -7=

Claims (1)

[Claims] A step of etching a part of a gate insulating film formed on an element formation region or a scribe line on a semiconductor substrate, a step of depositing polycrystalline silicon on the semiconductor substrate, and a step of forming a gate electrode of a MOS transistor. The polycrystalline silicon covering the region in which the polycrystalline silicon and a part of the gate insulating film are etched, the region that will become the gate electrode of the MOS transistor, and a part of the gate insulating film are etched. a step of etching the polycrystalline silicon so as to leave the polycrystalline silicon in a region connecting the MOS regions;
The method is characterized by comprising the steps of performing ion implantation to form a source and drain of a transistor, and etching the polycrystalline silicon covering a region where a portion of the gate insulating film is etched. A method for manufacturing a semiconductor device.