JPH04195774A - Maximum liklihood decode control system - Google Patents

Abstract

PURPOSE:To reduce the error rate of decode by determining an assumed sample value based on the consideration for waveform interference induced by future data from an assumed pass. CONSTITUTION:The equalized output of an input signal which is subjected to waveform interference is sampled by an AD converter 2. This sampled value or a pulse to be added to a clock regenerative section 1 indicates the result of the input signal equalized and decided and it is input into a decode section 3 as a virtual decoded value. An assumed sample value is determined by the extent of interference by future data, using this virtual decoded value. It is, therefore, possible to determine the extent of interference induced by the past data to be given to the current data and an assumed sample value which estimates the extent of interference by future data. This construction makes it possible to reduce the error rate of decode without increasing the length of restraint.

Description

[Detailed Description of the Invention] [Summary] Regarding a maximum likelihood decoding control method for maximum likelihood decoding of an input signal subjected to waveform interference, the present invention aims to improve the decoding error rate without increasing the circuit scale. a clock regeneration unit that equalizes and pulses an input signal that has received interference and generates a sampling clock signal that is phase-synchronized with the pulse resulting from the pulsation; and an AD that samples the input signal in accordance with the sampling clock signal from the clock regeneration unit. a converting unit; and a decoding unit that performs maximum likelihood decoding using sample values and assumed sample values from the AD converting unit; Using the pulse after oxidation,
The configuration is such that the amount of interference due to data temporally previous to the current sample value is estimated, the assumed sample value is obtained, and maximum likelihood decoding is performed.

C. Industrial Application Field] The present invention relates to a maximum likelihood decoding control method for maximum likelihood decoding of an input signal subjected to waveform interference.

2. Description of the Related Art In magnetic disk devices and the like, recording densities have been increased in response to demands for larger capacities. Therefore, the reproduced signal is subject to a large amount of waveform interference, and waveform equalization processing becomes difficult, resulting in a high decoding error rate. It is possible to improve the decoding error rate by using a Viterbi decoder or the like to perform maximum likelihood decoding on the reproduced signal that has suffered from such waveform interference or the received signal that has suffered from waveform interference in the data transmission system. Proposed.

[Prior Art] A demodulation system of a conventional magnetic recording device has, for example, the configuration shown in FIG. 8, where 61 is a magnetic head for reproducing recorded data from a recording medium such as a magnetic disk, and 62 is an amplifier. , 63 is an equalizer, 64 is a pulse generator, 65 is a phase locked loop (PLL), 66 is an equalizer, 67 is an A
The D converter (A/D) 68 is a Viterbi decoder.

The reproduced signal from the magnetic head 61 is amplified by an amplifier 62, equalized and amplified by equalizers 63 and 66 including filters, and subjected to noise removal, etc., and a pulse is formed by peak detection in a pulse generator 64. A clock signal whose phase is synchronized with the reproduced signal is obtained from the phase synchronization circuit 65, and this clock signal becomes a sampling clock signal of the AD converter 67, and the reproduced signal equalized by the equalizer 66 is applied to the AD converter 67. It is sampled by a bit-period sampling clock signal from the phase synchronization circuit 65 and converted into a digital signal, and the sample value of the reproduced signal converted into the digital signal is applied to a Viterbi decoder 68 and subjected to maximum likelihood decoding.

The Viterbi decoder is known as a maximum likelihood decoder for convolutional codes, and for example, as shown in FIG.
ACS circuits 72-1 to 72-4, path memory 73,
It includes a normalization circuit 74 and a path selector 75,
The branch metric value is calculated by the distributor 71 and the AC
It is distributed to S circuits 72-1 to 72-4. These ACS circuits 72-1 to 72-4 are provided by -1 in 2, where k is the constraint length of the convolutional code, and in FIG. 9, four ACS circuits are provided. , the case where the constraint length is 3 is shown.

Further, each of the ACS circuits 72-1 to 72-4 has an adder (
A), a comparator (C), and a selector (S).The adder (A) adds the branch metric value and the previous path metric value, and the comparator (C) compares the added branch metric value with the previous path metric value. The smaller value is selected by the selector (S) as the bus metric value of the surviving path, and the path selection signal at that time is added to the path memory 73. It has a path memory cell, is stored as a surviving path, and the output of the final stage is added to the path selector 75, and a decoded output is obtained by majority vote processing or the like. In addition, in the calculation of the bus metric value, if the number of digits overflows, the normalization circuit 74 normalizes the bus metric value.

When such a Tavi decoder is used to decode a signal subjected to waveform interference, the ACS circuit calculates the sum of the squared output of the error between the assumed sample value and the actual sample value and the previous path metric value. The new path metric value is set as a new path metric value, each bus metric value is compared, the smaller of the new path metric values of the addition output is selected as the next path metric value, and the selection information is added to the path memory 73. be.

FIG. 10 shows a trellis diagram with a constraint length of 3, where solid arrows indicate the transition when the input data is loN, dotted arrows indicate the transition when the input data is "1", and circles indicate the internal state. For example, if the hypothetical sample values at buses PO and PI are
), (shown by the black circle in the waveform of (b))' 90+ y
It can be DI. This value is shown in (a) in Figure 11.
A 3-bit hypothetical path (a-1+ ”
O + al ) is obtained by waveform interference, and the first
Let g be the sample value according to the bit period in the isolated waveform shown in FIG. Therefore, y. , y□ is the constraint length = 3, then m = 1, so from 1 = -1 to i
= +1 is the value obtained by equation (1).

If interference from past data is also considered, it can be determined by using the path memory values (t12.b3. . . ).

FIG. 12 is a block diagram of the main part of a conventional example in which interference from past data is considered based on the above-mentioned equation (2).
It is equipped with an S circuit 81, a path memory 82, a path selector 83, and a hypothetical path memory 84.
It is added to the S circuit 81. The path memory 82 and the hypothetical path memory 84 have a shift register configuration that can store "1", "0", and "-1°', and the ACS circuit 81
The squared output of the difference between the hypothetical sample value and the actual sample value is calculated and compared with the previously calculated bus metric value, and the smaller one is selected. It is input into the path memory 82.

Therefore, although the value in the path memory 82 is not the most probable decoded value, it becomes a probable value at that point in time as a value connected to the assumed path. Moreover, the path selector 83 is
The minimum value of the bus metric value at that point in time is detected, a bus connected to that state is selected, and the last data is used as the decoded output. Further, the arrow connecting the path memory 82 and the assumed path memory 84 indicates that the current assumed sample value is obtained by performing multiplication and addition, as shown in equation (2).

[Issue Ia to be Solved by the Invention] As described above, by also considering interference from past data, accurate hypothetical sample values can be estimated. However, when considering a bus 1 bit ahead (1 bit before the current time), for example, in the trellis diagram of Figure 10, the hypothetical sample assumes that the buses following bus PO are POO and PIO. The values are (d) and (e
) is indicated by the black circle in the waveform. o+Vpl. So, 1
If the data in the future by a bit is "'1", the error in the assumed sample value will become large unless the amount of interference is taken into account. Therefore, it is necessary to increase the constraint length k, that is, increase the number of bits of the hypothetical path to accurately estimate the amount of interference.

However, since the circuit scale of the decoder is proportional to 2'', increasing the constraint length k would require an enormous circuit scale, making it difficult to realize.

Furthermore, in a decoding method that takes into account interference caused by past data, such as the conventional example shown in FIG. It is necessary to perform special equalization to reduce interference to zero.

This special equalization is a major hindrance in terms of practical application of magnetic disk devices, etc., in which the amount of interference differs for each magnetic recording track.

The present invention aims to improve the decoding error rate without increasing the circuit scale.

[Means to solve the problem]

The maximum likelihood decoding control method of the present invention estimates waveform interference due to future data using a signal on a path for clock recovery to improve the decoding error rate, and will be explained with reference to FIG. do.

An equalization and pulsing unit 4 converts the input signal subjected to waveform interference into pulses, and generates a sampling clock signal that is phase-synchronized with the pulse. The AD conversion unit 2 that samples and reproduces the
The decoding unit 3 performs maximum likelihood decoding using the sample value from the conversion unit 2 and the assumed sample value, and in this decoding unit 3, the equalized sample value or pulsed pulse of the input signal This method estimates the amount of interference caused by data temporally earlier than the current sample value to obtain a hypothetical sample value, and performs maximum likelihood decoding using the hypothetical sample value.

The decoding unit 3 also includes a shift register to which the sample value after equalization of the input signal or the pulse after pulse conversion is input, an ACS circuit to input the sample value of the input signal, a hypothetical path memory, a path memory, and a path register. A selector is provided, and a hypothetical sample value is determined and inputted to the ACS circuit based on the contents of the shift register, the contents of the hypothetical path memory, and the contents of the path memory.

[Effect]

In claim 1, the sample value obtained by sampling the equalized output of the input signal subjected to waveform interference by an AD converter or the pulse applied to the clock reproducing unit l represents the result of equalizing the input signal and making a hard decision, This will be input to the decoding section 3 as a temporary decoded value. By estimating the amount of interference due to future data using this temporary decoded value and obtaining a hypothetical sample value, the amount of interference due to past data given to the current data as well as the amount of interference due to future data is estimated. Sample values can be obtained.

Therefore, the decoding error rate can be improved without increasing the constraint length.

In claim 2, a temporary decoded value is input to the shift register, a sample value of the input signal is input to the ACS circuit, and based on the contents of the shift register, the contents of the assumed path memory, and the contents of the path memory, A hypothetical sample value that estimates the amount of interference from past and future data with respect to the current sample value is calculated and input to the ACS circuit, and the squared output of the error between this hypothetical sample value and the sample value of the input signal and the previous metric value are calculated. Maximum likelihood decoding is performed by adding and comparing the values and selecting the smaller one.

(Examples) Examples of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, in which 11 is a head, 12 is an amplifier, 13 is an equalizer,
14 is a pulse circuit, 15 is a phase locked loop (PLL),
16 is a filter, 17 is an AD converter (A/D), and 18 is a Viterbi decoder. Recorded information is reproduced by the head 11 of a magnetic recording medium in a magnetic disk device, etc., and this reproduced signal is used as an input signal. Indicates the case of decoding.

The input signal (reproduced signal) is subjected to waveform interference as described above, and is amplified by the amplifier 12 and applied to the equalizer 13 and filter 16, and the input signal whose waveform is equalized by the equalizer 13 is converted into a pulse. The signal is converted into a pulse by peak detection etc. in the circuit 14 and applied to the phase synchronization circuit 15. A clock signal whose phase is synchronized with the pulse from this phase synchronization circuit 15 is applied to an AD converter 17 as a sampling clock signal.
The input signal is sampled via the Viterbi decoder 18 and converted into a digital signal.
of the input signal from the pulsing circuit 14.
", "0°' are applied to the Viterbi decoder 18 as temporary decoded values.

The pulsing circuit 14 includes, for example, a differentiating circuit and a zero cross detecting circuit, and by differentiating the output signal of [0.3] with the differentiating circuit, the differential output becomes zero at the time corresponding to the peak point. A zero cross detection circuit detects the zero point and outputs a pulse. The Viterbi decoder 8 has the configuration shown in FIG.
A Viterbi decoder similar to the conventional example shown in the figure, 22 a shift register, 23 a hypothetical path memory, 24 an ACS circuit, 2
5 is a path memory, and 26 is a path selector.

The shift register 22, the assumed path memory 23, and the path memory 25 each have a configuration of multiple columns, and
It has a configuration that can store 1"Z, 1lQtl, and "-1pa. Further, as indicated by the arrow, it has a hypothetical sample value calculation section that calculates hypothetical sample values through multiplication and addition processing.

When considering the interference of past data and future data with respect to the current sample value, the sample value g of the focus period of the isolated waveform in FIG. 11(C).

and the value ai of the bus corresponding to the present, past, and future.

Using bi'+C7, the assumed sample value y is calculated using the following formula % Formula % As mentioned above, if the constraint length is set to = 3, then m = 1,
The three bits a-1, ao+81 from 1=-1 to i=+1 in the hypothetical path memory 23 are multiplied and added by the sample values g+, go, g-+ of the isolated waveform, and n= 4, from i=2 to i=4 in the path memory 25
3 bits up to b2. b, , b4 and the isolated waveform sample value g-z+g-3+ga are multiplied and added, and the shift register 22 changes from 1=-4 to 1=-2.
Multiplying and adding the 3 bits up to c-4r c-3+04 and the isolated waveform sample value ga+g:+1gz are performed, and the results of these additions are added to form the hypothetical sample value y. That is, it is necessary to match the phases of the pulse input to the shift register 22 and the sample value from the AD converter 17 when the above-mentioned i=0 is the current time, and the number of stages of the shift register 22 must be selected. This is to perform delay processing in the hypothetical sample value calculation section.

FIG. 4 is a block diagram of the main part of the hypothetical sample value calculating section that calculates the hypothetical sample value y using equation (3), in which 22 is a shift register, 23 is a hypothetical path memory, 25 is a path memory, and 31 to 39 are multiplication units. 40 is an adder. The 3 bits C-4+C-L of the shift register 22 are applied to the isolated waveform sample values g4 to g-< (see (C) in FIG. 9).
c-i and 3 bits aI+ of the hypothetical path memory 23
a Or a I and 3 bits b, , b3 . of the path memory 25. b, and are added to multipliers 31 to 39 for multiplication, the outputs of each multiplier 31 to 39 are added to adder 40 for summation, and the output of adder 40 is used as the assumed sample value y in the ACS circuit. 24.

Then, the ACS circuit 24 calculates the difference from the sample value. That is, a hypothetical sample value y is obtained that takes into account interference due to past data and interference due to future data.

FIG. 5 is a block diagram of another embodiment of the present invention, 51
is a head, 52 is an amplifier, 53 is a container, 54 is a pulse generator, 55 is a phase locked loop (PLL), 56 is a filter, 57 is an AD converter (A/D), 5B is a Viterbi decoder, 59 is an AD converter (A/D) that samples the output of the flower vase 53 and converts it into a digital signal. Second
Instead of the pulses from the pulse generation circuit in the embodiment shown in the figure, a digital signal obtained by converting the output signal of the flower vase 53 by the AD converter 59 is input to the Viterbi decoder 58.

Further, the Viterbi decoder 58 is the Viterbi decoder 1 of the above-mentioned embodiment.
The sample value from the AD converter 59 is input to the shift register 22.

Figure 6 is an explanatory diagram of the amount of interference, and shows the amount of interference that the signal at time -1 exerts on time O.The possible values of the signal at time -1 are as follows: Assuming that there is no ``l1jl, ``0'', ``-I
It can be considered that there is a normal distribution centered on I+ due to the influence of noise. Probability p (x.

X") is Represented by Also, the data is “1” and “’0”.

The amount of interference exerted at time 0 when it is "-1" is g, v, gitt, gi?, respectively, as shown in the figure.
Assuming that it is an FF, the expected value gxi of the amount of interference when the sample value is xl is as follows.

Also, by substituting the conditions of the following equation (6) into equation (5), we get, where the sample value is shown on the horizontal axis, the expected value of the amount of interference at that time is shown on the vertical axis, and the S/N is expressed as a parameter. Then, the result will be as shown in FIG.

As can be seen from the figure, when the S/N is high, the amount of interference is
It is better to use a decoded value such as QZI “1”, but S
When /N is low, it means that the amount of interference must be found probabilistically using sample values. Therefore, considering the influence of noise, gxi"'giX
...(8), then the assumed sample value y is: y=;ffi, -g-yama+1:, soot, jitte2g-yama1
...(9) It can be obtained as follows.

Therefore, the sample value xi by the AD converter 59 in FIG.
9 is the shift register 22 (third
(see figure), and instead of C-1+C-1cm4, x-2°, and the ACS circuit 24 of the Viterbi decoder 58 (see FIG. 3).
The squared output of the difference with the sample value from the AD converter 57 is added to the previous metric value to obtain a new metric value, and the smaller one is selected by comparing the metric values. , the last value of the selected hypothetical path is input to the path memory 25 (see FIG. 3).

As mentioned above, waveform interference is within the range of the assumed path (constraint length k)
Even if the waveform interference exceeds , when calculating the waveform interference from data before the hypothetical path (corresponding to the future), use sample values that have been equalized to reduce waveform interference, and further take noise into account and use a slight configuration. By simply adding , it is possible to obtain accurate hypothetical sample values by probabilistically estimating the amount of waveform interference. Therefore, the decoding error rate can be improved.

The present invention is not limited to the above-mentioned embodiments, but can be modified in various ways, such as:
It can also be applied to decoding input signals subjected to waveform interference in data transmission systems.

〔Effect of the invention〕

As explained above, the present invention inputs the sample value of the input signal from the AD conversion section 2 to the decoding section 3, and converts it into pulses by detecting the sample value of the equalized output of the input signal or the peak of the input signal. This pulse is input to the decoding unit 3 and subjected to maximum likelihood decoding, and the assumed sample value is obtained by taking into account waveform interference from data in the future from the assumed path. Therefore, the constraint length k should not be increased ( In other words, it is possible to obtain accurate hypothetical sample values without increasing the circuit scale, thereby eliminating the need for special waveform equalization compared to the conventional example that only considers past data. There is an advantage that the decoding error rate can be improved without any problems.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is a block diagram of main parts of an embodiment of the invention, and Fig. 4 is a hypothetical sample value calculation section. 5 is a block diagram of another embodiment of the present invention, FIG. 6 is an explanatory diagram of the amount of interference, and FIG. 7 is an explanatory diagram of the expected value of the amount of interference.
Fig. 8 is a block diagram of the conventional example, Fig. 9 is a block diagram of a Viterbi decoder, Fig. 10 is a trellis diagram with a constraint length of 3, and Fig. 1
1A to 1E are explanatory diagrams of signal waveforms, and FIG. 12 is a block diagram of main parts of a conventional example. 1 is a clock recovery section, 2 is an AD conversion section, 3 is a decoding section, 4
is the equalization and pulsing section.

Claims (2)

[Claims] (1) A clock regeneration unit (1) that equalizes and pulses an input signal subjected to waveform interference and generates a sampling clock signal that is phase-synchronized with the pulse resulting from the pulsation; An AD converter (2) that samples the input signal according to a sampling clock signal, and a decoder (3) that performs maximum likelihood decoding using the sample value from the AD converter (2) and the assumed sample value, In the decoding unit (3), using the equalized sample value of the input signal or the pulsed pulse, the amount of interference due to data temporally earlier than the current sample value is estimated, and the A maximum likelihood decoding control method characterized by determining hypothetical sample values and performing maximum likelihood decoding. (2) The decoding unit (3) includes a shift register into which the equalized sample value of the input signal or the pulsed pulse is input, and an A into which the sample value of the input signal is input.
The system includes a CS circuit, a hypothetical path memory, a path memory, and a path selector, and calculates the hypothetical sample value based on the contents of the shift register, the contents of the hypothetical path memory, and the contents of the path memory. , the maximum likelihood decoding control method according to claim 1, wherein the maximum likelihood decoding control method is input to the ACS circuit.