JPH04195372A - Logic simulator - Google Patents
Logic simulatorInfo
- Publication number
- JPH04195372A JPH04195372A JP2327756A JP32775690A JPH04195372A JP H04195372 A JPH04195372 A JP H04195372A JP 2327756 A JP2327756 A JP 2327756A JP 32775690 A JP32775690 A JP 32775690A JP H04195372 A JPH04195372 A JP H04195372A
- Authority
- JP
- Japan
- Prior art keywords
- data
- memory
- state value
- memories
- logic simulator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 claims abstract description 53
- 238000004088 simulation Methods 0.000 claims abstract description 4
- 230000006870 function Effects 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 2
- 238000004904 shortening Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
- 102100030551 Protein MEMO1 Human genes 0.000 description 1
- 101710176845 Protein MEMO1 Proteins 0.000 description 1
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は論理シミュレータ、特に、ノ１−ドウエア化論
理シミュレータに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic simulator, and particularly to a node-based logic simulator.
従来、この種の論理シミュレータにおいては、メモリが
１個であるため、メモリ内への状態値収集がフル状態に
達すると、状態値収集を中断し、外部貯蔵装置へとメモ
リ内データを転送し、データ転送後、メモリ内へと再度
状態値収集を開始する、この一連動作を繰り返すものと
なっていた。Conventionally, this type of logic simulator has only one memory, so when the state value collection in the memory reaches a full state, the state value collection is interrupted and the data in the memory is transferred to an external storage device. After the data is transferred, the system starts collecting state values again into the memory, and this series of operations is repeated.
上述した従来の論理シミュレータにおける状態値収集は
、メモリが１個であるため、状態値収集、データ転送が
交互に行なわれ状態値収集時には、データ転送中断、デ
ータ転送時には、状態値収集中断処理が実行されるので
、時間を多大に要する欠点が・あった。Since state value collection in the conventional logic simulator described above uses one memory, state value collection and data transfer are performed alternately, and data transfer is interrupted during state value collection, and state value collection interruption processing is performed during data transfer. Since it is executed, it has the disadvantage that it takes a lot of time.
本発明の論理シミュレータは、メモリ内データを外部記
憶装置に転送する機能を持った論理シミュレータにおい
て、第１と第２のメモリと、シミュレーション結果であ
る出力状態値を前記第１と第２のメモリに交互に割り付
け格納を行なう状態値制御機構と、前記第１のメモリへ
の格納時には前記第２のメモリ内のデータフル状態を認
識して、フル状態であれば前記第２のメモリより外部記
憶装置にデータ転送を行ない、又前記第２のメモリへの
格納時には前記第１のメモリの認識、転送を行ない前記
外部記憶装置に交互にデータ転送を行なう貯蔵機構とを
含んで構成される。The logic simulator of the present invention has a function of transferring data in memory to an external storage device, and the logic simulator has a function of transferring data in memory to an external storage device. A state value control mechanism that alternately allocates and stores data in the first memory, and recognizes a full state of data in the second memory when storing data in the first memory, and if the data is full, transfers data from the second memory to external storage. The storage mechanism includes a storage mechanism that transfers data to the device, recognizes and transfers data to the first memory when storing data in the second memory, and alternately transfers data to the external storage device.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は、本発明の一実施例を示すブロック図であり、
論理シミユレータ１内部において、メモリ内データを外
部貯蔵装置に転送する機能を有している。FIG. 1 is a block diagram showing one embodiment of the present invention,
Inside the logic simulator 1, there is a function to transfer data in memory to an external storage device.
論理シミュレータ１において、シミュレーション結果で
ある出力状態値２は、状態値制御機構３ニヨリ、メモリ
に格納可能なデータ量と、アドレスに見合った状態値デ
ータを割り付け、判断を行ない、メモリＡ４へと収集を
行なう。In the logic simulator 1, the output state value 2, which is the simulation result, is collected in the memory A4 by the state value control mechanism 3, which allocates state value data that matches the amount of data that can be stored in the memory and the address, and makes a judgment. Do this.
次ニはメモリＢ５への格納可能なデータ量とアドレスに
見合った状態値データを同様に判断を行なう。Next, the amount of data that can be stored in the memory B5 and the state value data that are appropriate for the address are similarly determined.
ここでメモリＡ４への状態値収集が終了すると、メモＩ
Ｊ Ｂ ５へと状態値収集を開始する。When the state value collection to memory A4 is completed, the memory I
Start collecting status values for JB5.
この時、メモリＢ５に状態値収集を切り換えると同時に
貯蔵機構６がメモリＡ４内のデータをホストマシン側で
ある外部貯蔵装置７へと転送し、貯蔵を行なう。At this time, at the same time as the state value collection is switched to the memory B5, the storage mechanism 6 transfers the data in the memory A4 to the external storage device 7 on the host machine side for storage.
また、貯蔵機構６は、メモリＡ４内の全データを外部貯
蔵装置７へ転送完了した事と、メモリＢ５内のデータが
フル状態である事を認識した後にメモリＡ４内データの
転送から、メモリＢ５内データへの転送へと切り換える
。In addition, after the storage mechanism 6 recognizes that all the data in the memory A4 has been transferred to the external storage device 7 and that the data in the memory B5 is full, the storage mechanism 6 transfers the data in the memory A4 to the memory B5. Switch to internal data transfer.
以後メモリＢ５内の全データの転送が終了した時点で、
同様にメモリＡ４よりのデータ転送を開始し、動作を繰
り返すものである。Afterwards, when all data in memory B5 has been transferred,
Similarly, data transfer from memory A4 is started and the operation is repeated.
以上の様に状態値制御機構３と貯蔵機構６によりメモ１
ＪＡ４へのデータ収集中には、メモリＢ５ヨリデータを
取り出し、また逆にメモリＢ５へのデータ収集中には、
メモリＡ４よりデータを取り出す。As described above, the memo 1 is stored by the state value control mechanism 3 and the storage mechanism 6.
While collecting data to JA4, data from memory B5 is taken out, and conversely, while collecting data to memory B5,
Retrieve data from memory A4.
この事を繰り返し行う事により、メモリを２個使用する
のみで全出力状態値データを高速に収集可能となり収集
時間の短縮化が出来る。By repeating this process, all output state value data can be collected at high speed by using only two memories, and the collection time can be shortened.
以上説明したように本発明は、２個のメモリを使用し、
２個のメモリ内へ状態値収集とデータ′転送を交互に行
なうことにより、データ転送時の状態値収集中断、状態
値収集時のデータ転送中断がに不必要となり、シミュレ
ーション動作の高速化が達成される効果がある。
゛As explained above, the present invention uses two memories,
By alternately performing state value collection and data transfer into two memories, there is no need to interrupt state value collection during data transfer or data transfer during state value collection, achieving faster simulation operation. It has the effect of being
゛
第１図は本発明の一実施例を示すブ・ロ゛ツク図である
。
１・・・論理シミュレータ、２・・・出力状態値、３・
・・状態値制御機構、４・・・メモリＡ１５川メモリＢ
１６・・・貯蔵機構、７・・・外部貯蔵装置。FIG. 1 is a block diagram showing one embodiment of the present invention. 1...Logic simulator, 2...Output state value, 3.
...Status value control mechanism, 4...Memory A15 River memory B
16...Storage mechanism, 7...External storage device.
Claims (1)
論理シミュレータにおいて、第１と第２のメモリと、シ
ミュレーション結果である出力状態値を前記第１と第２
のメモリに交互に割り付け格納を行なう状態値制御機構
と、前記第１のメモリへの格納時には前記第２のメモリ
内のデータフル状態を認識して、フル状態であれば前記
第２のメモリより外部記憶装置にデータ転送を行ない、
又前記第２のメモリへの格納時には前記第１のメモリの
認識、転送を行ない前記外部記憶装置に交互にデータ転
送を行なう貯蔵機構とを含むことを特徴とする論理シミ
ュレータ。In a logic simulator having a function of transferring data in memory to an external storage device, first and second memories and output state values that are simulation results are transferred to the first and second memories.
a state value control mechanism that alternately allocates and stores data in the first memory; and when storing data in the first memory, it recognizes a full state of data in the second memory, and if the data is full, the data is stored in the second memory. Transfer data to external storage device,
The logic simulator further includes a storage mechanism that recognizes and transfers data to the first memory when storing data to the second memory, and alternately transfers data to the external storage device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2327756A JPH04195372A (en) | 1990-11-27 | 1990-11-27 | Logic simulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2327756A JPH04195372A (en) | 1990-11-27 | 1990-11-27 | Logic simulator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04195372A true JPH04195372A (en) | 1992-07-15 |
Family
ID=18202638
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2327756A Pending JPH04195372A (en) | 1990-11-27 | 1990-11-27 | Logic simulator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04195372A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5897653A (en) * | 1996-06-20 | 1999-04-27 | Mitsubishi Electric Semiconductor Software | Data tracing apparatus |
-
1990
- 1990-11-27 JP JP2327756A patent/JPH04195372A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5897653A (en) * | 1996-06-20 | 1999-04-27 | Mitsubishi Electric Semiconductor Software | Data tracing apparatus |
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