JPH04192162A - Block synchronizing circuit for digital data - Google Patents

Abstract

PURPOSE:To shorten the time for synchronization recovery and to attain a reduction of the frequency overlooking the effective data blocks by deciding the synchronization from the result of parity check for two blocks in a block synchronizing circuit. CONSTITUTION:After the input data are once stored in a shift register 2, the parity check for addresses 22, 26 is performed by parity check circuits 5, 6 to output a binary signal according to the existence of error, and also the synchronous signal is detected by a synchronous pattern detecting circuit 9 to output the binary signal according to the existence of synchronization. The state of synchronization is decided in a synchronization deciding circuit 12 by the operation of an AND circuit 11 or an OR circuit 10 in accordance with the outputs of the check circuit 6 and detector 9. When the synchronization is decided as abnormal, the synchronized position is searched by an address protecting circuit 7. Thus, the frequency overlooking the effective data blocks can be reduced.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a data block synchronization circuit in equipment that records, reproduces, or transmits digital data, and particularly relates to a data block synchronization circuit for converting video or audio signals into digital data. This invention relates to VTRs and digital audio tape recorders that perform recording and playback.

(Prior Art) Forward protection and backward protection are known as commonly used synchronization protection methods.

Forward protection is to prevent synchronization from being lost even if there are some bit errors after synchronization is established. For example, if a detection error occurs several times in succession, it is assumed that synchronization is lost.

In addition, backward protection is to prevent synchronization from occurring at locations other than the synchronization signal. For example, if the synchronization signal is detected several times in succession at regular intervals, it is assumed that synchronization has been established.

A conventional example of a conventional digital data block synchronization circuit will be described below with reference to FIG. 3, and a state where synchronization is established is called a synchronous state, and a state where synchronization is not established is called an asynchronous state.

- In boat fishing, the data string includes the address of the data block, a parity code for determining whether the address is correct, etc., and a parity check can also be included in the detection and determination of the synchronization signal.

In FIG. 3, data input terminal 31 is connected to the input of shift register 32. In FIG. The output of the shift register 32 is connected to the input of a shift register 33 and a parity check circuit 35 for checking parity of addresses and the like.

The output of the shift register 33 is connected to the input of the synchronization pattern detector 36 and the data output terminal 34. The output of the parity check circuit 35 and the output of the synchronization pattern detector 36 are connected to an AND circuit 37. AND circuit 3
The output of state counter 7 is connected to the input of state counter 38. The output of the state counter 38 is connected to a synchronization pulse output terminal 39.

This operation will be explained.

Data input to the data input terminal 31 is supplied to the input of the shift register 32.

All data stored in shift register 32 is fed in parallel to the input of parity check circuit 35. Further, the oldest data stored in the shift register 32 is supplied to the input of the shift register 33. All data stored in shift register 33 is fed in parallel to the input of sync pattern detector 36. Further, the oldest data stored in the shift register 33 is supplied to the data output terminal 34. The output of the parity check circuit 35 and the output of the synchronization pattern detector 36 are supplied to an AND circuit 37.

The output of the AND circuit 37 is output to the input of the state counter 38. The output of the state counter 38 is supplied to a synchronous pulse output terminal 39.

The shift registers 32 and 33 are shift registers that sequentially store input data, store the input data at the timing according to the input clock, and output the data in chronological order. The shift registers 32 and 33 are
All data stored in each is outputted to a parity check circuit 35 and a synchronization pattern detector 36, respectively.

The parity check circuit 35 outputs a check pulse when the error in the data input from the shift register 32 is less than a certain value. The synchronization pattern detector 36 checks whether the data input from the shift register 33 matches the synchronization pattern, and outputs a detection pulse if they match.

AND circuit 37 outputs a pulse when a check pulse and a detection pulse are input simultaneously.

The state counter 38 counts up at the clock timing when a pulse is input from the AND circuit 37, and counts down at the clock timing when no pulse is input from the AND circuit 37. When a pulse is detected from the AND circuit 37 twice in succession, a synchronizing pulse is output, and the AND circuit 37
If no pulse is detected three times in a row from then on, no synchronizing pulse will be output. By monitoring the synchronization state using the state value in this way, it is possible to recover from an incorrect synchronization state. Note that the synchronization detection position is predicted using a state counter.

In this way, conventional block synchronization circuits for digital data use state counters to count the number of synchronization signal detections and errors, but if the synchronization state changes during that time, the response is delayed and valid data is lost. There is a risk that the extraction rate will decrease (a phenomenon in which valid data blocks are missed), and the synchronization detection conditions will become stricter, causing problems such as an increase in detection errors.

(Problems to be Solved by the Invention) As described above, in the conventional block synchronization circuit, synchronization protection is not optimized, resulting in a substantial reduction in the error rate due to synchronization detection errors. The present invention eliminates such drawbacks, reduces the substantial drop in error rate due to synchronization signal detection errors, and shortens the time required to recover synchronization when synchronization is lost due to burst errors or the like. The purpose of this is to reduce the number of times valid data blocks are missed.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, in this invention, errors in first and second digital data and the first and second digital data are detected. a storage means capable of storing first and second parity codes necessary for a predetermined period of time, and detecting the first digital data and the first parity code stored in the storage means; , a first error detection means for detecting an error, and a second error detection means for detecting an error by detecting the second digital data and the second parity code stored in the storage means. and synchronization determining means for determining the state of synchronization based on the signals from the first and second error detecting means, wherein the error detection results by the first and second error detecting means are detected by the first and second error detecting means. If either of the second digital data is error-free digital data, the synchronization determining means outputs a signal indicating the synchronization state, and the error detection results by the first and second error detecting means are A block synchronization circuit for digital data is provided, characterized in that when the first and M2 digital data are both erroneous, the synchronization determining means outputs a signal representing an asynchronous state.

(Function) In the device configured in this way, synchronization protection is optimized and the actual drop in error rate due to synchronization signal detection errors is reduced, and when synchronization is broken due to burst errors etc. By shortening the time it takes to recover synchronization, the number of missed valid data blocks can be reduced.

(Embodiment) A digital data block synchronization circuit according to the present invention will be described below with reference to FIG.

In this embodiment, addresses 22 and 26 were used as the first and second digital data.

In FIG. 1, a data input terminal 1 is connected to a shift register 2. In FIG. The output of the parity code 21 is connected to the input of the parity check circuit 5. The output of address 22 is connected to the inputs of parity check circuit 6 and address protection circuit 7.

The output of the parity check circuit 5 is the address protection circuit 7,
It is connected to the input of the OR circuit 10. Valid data 24
The output of is connected to the input of the output control circuit 3. The output of parity code 25 is connected to the input of parity check circuit 6. The output of address 26 is connected to the inputs of parity check circuit 6 and address protection circuit 7. The output of the parity check circuit 6 is an address protection circuit 7, an OR circuit 10. It is connected to the input of the AND circuit 11. The output of the synchronization signal 27 is connected to the input of the synchronization pattern detector 9. The output of the synchronization pattern detector 9 is A
It is connected to the input of the ND circuit 11. Synchronization judgment circuit 1
The 2 and 1 block counters 13 exchange information with each other. OR circuit 10. The output of the AND circuit 11 is connected to the input of the synchronization determination circuit 12. The output of the synchronization determination circuit 12 is connected to the inputs of the output control circuit 3 and the address protection circuit 7. The output of the address protection circuit 7 is connected to the input of the output control circuit 3. The output of the output control circuit 3 is connected to a data output terminal 4 and an address output terminal 8.

Next, the operation will be explained.

If the pit error rate is better than the 13th power of 10, the number of forward protection and backward protection is usually sufficient to be 2 times or less, so the synchronization signal, address, and parity code stored in the shift register should be for 2 blocks. .

Data input from a data input terminal 1 is stored in a shift register 2, including a synchronizing signal, an address, and parity codes for two blocks.

A parity check circuit 5.6 that performs a parity check on an address checks the parity of each address 22.26 stored in the shift register 2, and outputs "12" if there is no error, and "0" if there is an error. If the synchronization pattern detector 9 can detect the synchronization signal 27, it outputs "1 degree"; if it cannot, it outputs "0 degree".

If there is an error in the address 22 or 26, the usability value of the data in that block will be reduced, so we put more emphasis on parity check than on the detection of synchronization patterns. A detector 9 is provided.

By freely combining the outputs of these two parity check circuits 5.6 and one synchronization pattern detector 9, type 1 errors in synchronization protection (synchronization cannot be detected even though synchronization is being sent) can be avoided. error) and type 2 error (
It is possible to control the probability of occurrence of an error in which synchronization is mistakenly recognized even though synchronization has not been sent.

A flowchart used in this synchronization determination circuit is shown in FIG.

The synchronization determination circuit 15 determines that the output of the synchronization pattern detector 9 is "l".
”, and the output of the parity check circuit 6 is “1”, the input from the AND circuit 11 becomes “1” and the synchronization determination circuit 12 considers that synchronization has been established (backward protection operation).
. - After synchronization is established (synchronized state), the next synchronization detection position is predicted by the 1-block counter 13. If the output of the detection result from the parity check circuit 5 or 6 is "1", the synchronization determination circuit 12 determines that the input from the OR circuit 10 is "L" and that the synchronization state is maintained. (Forward protection operation).

If an error occurs in two consecutive blocks during the parity check, the output of the OR circuit 10 becomes "0°" and it is assumed that the synchronization is broken (asynchronous state), and the synchronization position of all bits in the input data is determined. Explore.

If there is no error in the address parity check, the address protection circuit 7 outputs the address as is, and if an error occurs, the address protection circuit 7 shown in FIG. By estimating and embedding from the address of the block, it is possible to prevent a decrease in valid data.

The data and address are input to the output control circuit 3, and are output at the location where they should be output based on the determination of the synchronization position by the synchronization determination circuit 12.

Although the synchronization signal 27 is used in the synchronization pattern detector 9 here, the synchronization signal 23 may also be used.

In the block synchronization circuit according to the embodiment of the present invention, the certainty of synchronization can be determined by looking only at the parity check results of two blocks in the synchronization state, so unlike the conventional synchronization circuit, synchronization pattern detection and Compared to the case where determination is made using both parity checks, it is possible to lower the probability of occurrence of synchronization detection errors even if the error rate of the input signal is poor.

[Effects of the Invention] According to the present invention, when continuous errors occur in input data, it is possible to shorten the time required from going into an asynchronous state to returning to a synchronous state, thereby reducing the number of times valid data blocks are missed. By balancing the first type of error and the second type of error in block synchronization detection, it is possible to increase the extraction rate of valid data.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a digital data block synchronization circuit according to the present invention. FIG. 2 is a flowchart of the synchronization determination circuit. FIG. 3 is a block diagram of a conventional digital data block synchronization circuit. 2... Shift register, 5, 6... Parity check circuit, 10... OR circuit, 12... Synchronization determination circuit, 21.25... Parity code, 22
．． 26...Address No. 1 Atsushi No. 2

Claims (1)

[Scope of Claims] First and second digital data and first and second parity codes necessary for detecting errors in the first and second digital data, respectively, are stored for a predetermined period of time. a first error detection means for detecting an error by detecting the first digital data and the first parity code stored in the storage means;
a second error detection means for detecting an error by detecting the second digital data and the second parity code stored in the storage means; and the first and second error detection means. and a synchronization determination means for determining a synchronization state based on a signal, and the error detection result by the first and second error detection means indicates that one of the first and second digital data is an error-free digital data. data, the synchronization determination means outputs a signal representing a synchronization state, and the error detection results by the first and second error detection means indicate that both the first and second digital data are errors. A block synchronization circuit for digital data, characterized in that when the synchronization determining means outputs a signal representing an asynchronous state.