JPH04191931A - Electronic computer - Google Patents

Abstract

PURPOSE:To efficiently execute an instruction sequence by delay-controlling a delay branching instruction according to the value of the delay slot length of the delay branching instruction. CONSTITUTION:A delay branching instruction to have variable delay slot length is titled as a brd (N) in the case of an unconditional branching instruction when the delay slot length is defined as (N), instruction sequences <ope1>, <ope2>,..., <opeN> continued after the delay branching instruction brd (N) of which delay slot length is the (N) are executed in order within a delay slot period set by the delay branching instruction brd (N) to the certain instruction sequence, for instance, and after that, an <ope> which is the instruction of the branching destination of the delay branching instruction brd (N) is executed at time of passing through the delay slot (N). Thus, the optimization of the instruction sequences can be attained simply and efficiently and instruction executing time is shortened without causing the waste of a clock.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an electronic computer that efficiently executes instructions using delayed branch instructions having different delay slot lengths.

(Prior art) Recently, RISC (Recluded In5tru
Microprocessors with a ction SetComputer type architecture are attracting attention. In this type of microprocessor, executing instructions without disturbing the flow of its vibe line processing is an important issue in making full use of its performance.

Now, one of the causes of the disturbance in the above-mentioned vibe line processing is a branch instruction. That is, in the vibe line processing, decoding of an instruction already fetched in the previous phase and fetching of the next instruction are performed in parallel in the same phase. At this time, if the instruction type is interpreted as a branch by decoding, it is necessary to cancel the next fetched instruction and re-fetch the branch destination instruction of the branch instruction, as described above. Redoing such an instruction fetch results in a clock loss and causes a disturbance in the vibe line processing.

For example, rD,J,[,1lja] is a means for solving problems caused by disturbances in pipeline processing due to branch instructions such as 2.

”Reducing the Branch P
energy in PipelinedProc
essors,” Computer, July, 1
．． 988. As introduced in the literature such as pp, 47-55J, Static Branch mI (Static Branch
Prediction) ■Dynamic branch prediction (Dynam
It is considered to adopt techniques such as ic Branch Prediction, Delay Branch, and Loop BufTers.

The delayed branch instruction used in the delayed branch method described above is
A delay slot of a certain length is set immediately after the execution of the instruction (delayed branch instruction), and the instructions in this delay slot period are executed before the execution of the delayed branch instruction. Note that the delay slot length of this delayed branch instruction is determined depending on the number of stages of pipeline processing and the content of processing at each stage. For example, Berkeley RI
In SCIIJ and the like, a delayed branch instruction with a delay slot length of [1] is generally set.

Now, when a branch instruction is decoded, the immediately following (next) instruction has already been fetched, so if it is determined by decoding that the instruction is a branch, it is generally necessary to cancel the execution of the next instruction that has already been fetched. In this regard, according to the delayed branch instruction, instead of canceling the next instruction, nop (no operaNon) is executed after the delayed branch instruction.
This nop instruction will be executed as is. As a result, as described above, processing substantially equivalent to canceling the next instruction can be executed using simpler hardware and without disturbing pipeline processing.

By the way, in electronic computers that have this type of delayed branch instruction, for example, the instruction immediately before the branch instruction, the instruction at the branch destination, or the instruction at the destination to which the branch is not branched is brought into the delay slot period set by the delayed branch instruction. I can do it. By changing (shifting) the instruction execution order like this, the instruction sequence (code) "Optimizing Delay"
d Branches, -Proc, IEEE Ml
cro-15, Oct, 19B2. pp, 114~]2
0,” etc., in detail. However, by using such a code optimization method, it becomes possible to efficiently execute the instruction sequence by effectively using, for example, a clock that originally did not perform any processing.

A typical example of a code optimization method involving the above-mentioned delayed branch instruction will now be described. One of the typical code optimization methods shown here is that the branch destination a of a branch instruction A consisting of
This is an optimization method in which, when is a branch instruction B, the branch destination a of the branch instruction A that is the branch source is replaced with the branch destination of the branch instruction B that is the branch destination a. Another method is
This is an optimization method that removes unnecessary locks by bringing a branch instruction to the position of a nop instruction placed between two instructions that would otherwise cause an interlock. Note that the meaning of [interlock] used here will be described later.

First, we will consider constraints when actually applying these optimization methods.

When the branch destination of branch instruction A is branch instruction B, the number of branches is reduced by replacing the branch destination a of the branch instruction A that is the branch source with the branch destination of branch instruction B that is the branch destination a. This section describes the optimization method used. However, here, we will consider a case where both the branch instructions at the branch source and the branch destination are delayed branch instructions.

Further, to simplify the explanation, the delay slot length of these delayed branch instructions is assumed to be [1].

For example, as shown in FIG. 11(a), both the branch destination and branch source delayed instructions are unconditional branch instructions (hereinafter, [brd
), then at least one of the instructions <opel> and <ope2> following each of these unconditional branch instructions brd^ and brdB is no.
If it is a p instruction, this instruction sequence is changed from the branch source unconditional branch instruction brd A to brdB as shown in FIG. 11(b).
It can be rewritten and optimized.

Note that the command <ape> is the command <opel>, <ape
2>, which is not a nop instruction. Furthermore, if both of the above instructions <opel> and <ape2> are nop instructions, the above instruction <opel> and <ape2> are respectively nop instructions.
> is also a nop instruction.

Also, the above commands <opel> and <ape2> are both no.
If it is not a p instruction, the branch destination of the unconditional branch instruction that is the branch source is rewritten (b
rcl^→brd B), by moving (shifting) the instruction <opel> before this unconditional branch instruction, the instruction sequence can be optimized. But the command <op
If el> is moved before the unconditional branch instruction brd, there is a possibility that an interlock will occur with the instruction that originally exists before the unconditional branch instruction brdO.

Therefore, in such a case, it is necessary to insert, for example, a nop instruction between those instructions. Therefore, the optimization as shown in FIG. 11(e) described above cannot necessarily be said to be effective.

On the other hand, as shown in Figure 12(a), if the branch source is a conditional branch instruction (hereinafter referred to as [cbrd]) and the branch destination is an unconditional branch instruction brd, then the following The optimization can be done in this way. That is, if the conditional branch instruction cbrcl executes an instruction in the delay slot period regardless of whether the condition is met or not, then the conditional branch instruction c
Rewrite the branch destination of brd (cbrd cc, A -c
brd cc, B), it can be optimized by moving the instruction (opel> before the execution of the conditional branch instruction cbrd above.However, such optimization can only be performed on the result of execution of the instruction <opel>) , only if its condition code does not change.

By the way, if the condition code changes by executing the instruction <opel>, use the <opel> command above.
>° cannot be moved before the conditional branch instruction cbrd. However, in this case, for example, FIG.
) Rewrite the branch destination of the conditional branch instruction cbrd (cbrd cc, A −+cbrd cc, c )
, optimization can be achieved by setting the branch destination to the instruction <ape2>. However, for a basic block starting with label B:, the basic block immediately before it is a predecessor, and the last instruction of that basic block is not a branch instruction, nor does it exist in the delay slot period of a delayed branch instruction. In case, after the optimization mentioned above,
It is necessary to insert a branch instruction br B to label B: before label C:. Therefore, even if such optimization is performed, there is no guarantee that the execution time of the program will be shortened.

However, if entering the basic block starting with label B: occurs only by branching, there is no need to insert a new branch instruction as described above, and therefore the optimization described above cannot be said to be entirely bad.

Next, as shown in FIG. 13(a), for example, the conditional branch instruction of the branch source is subjected to a delay thrower when the condition is not met, in the same way as in the optimization shown in FIG.
As shown in b), change the branch destination of the conditional branch instruction (cbr
d" cc, ^-cbrd" cc, B) By doing,
Its optimization is possible.

However, even in this case, the basic block immediately before the basic block starting with label B: is a predecessor, and the last instruction of this basic block is not a branch instruction, and even if it exists in the delay slot period of a delayed branch instruction. If not, it is necessary to insert a branch instruction br B to label B before label C: after the optimization. Therefore, in this case as well, there is no guarantee that the above-described optimization will shorten the program execution time. However, the above label B
If entry into a basic block starting with : occurs only by branching as described above, there is no need to insert a new branch instruction, so this optimization will work very effectively.

Finally, there are two
We will describe an optimization method that removes unnecessary locks by bringing a branch instruction to the position of a nop instruction placed between two instructions.

Figure 14(a) shows a nop between two instructions <opel> and <ope2> that cause an ink clock.
It shows an instruction sequence with instructions. Here, the n inserted between the above two instructions <opel> and <ope2>
The op instruction is used to prevent interlocks caused by the instructions <opel,> and <open>.

Now, the above-mentioned interrotsuta means that there is some kind of dependency relationship between the fuse consisting of the instruction <opel> and the phase consisting of the instruction <opel>, and these instructions <opel><
This term refers to a phenomenon in which when ``op2>'' is executed continuously, the above dependency relationship violates the law of causality, and as a result, correct execution is not guaranteed.

For example, as shown in FIG. 15(a), if the phase E of the instruction <opel> cannot be executed until after the instruction <opel> has completed phase M, the instruction (Opel>(O
If pe2) is executed continuously, an interlock will occur.

Therefore, in case 2, it is necessary to prevent the occurrence of an interlock by placing a nop instruction between two consecutive instructions <opel> and <ope2> as shown in FIG. 15(b). be.

In case 2, for example, if the next instruction after the instruction <ope2> is an unconditional branch instruction br, the branch instruction br is changed to a delayed branch instruction brd as shown in FIG. 15(C), and the instruction By moving between <opel,> and <ope2>, it becomes possible to eliminate unnecessary locks in the part where the nop instruction was given. However, this kind of optimization can be performed if the nop instruction is two instructions before the br instruction (delay slot length + 1 slot before) =j=
', only in certain cases. If this condition is not met, it is necessary to move the nop instruction to that position, for example, by instruction scheduling.
It is not guaranteed that such a nop instruction movement is necessarily possible.

(Problems to be Solved by the Invention) As described above, in a microprocessor having a RISC type architecture, when the branch destination of a delayed branch instruction is a similar delayed branch instruction, the branch destination of the branch instruction that is the branch source is Optimization of the instruction code can be considered by replacing it with the branch destination of the branch instruction at the branch destination. However, depending on the type of delayed instruction, optimization may not always be possible due to various constraints. Further, when performing optimization, it may be necessary to add a new branch instruction, and there is no guarantee that the execution time will be reduced. Therefore, when these problems are considered, it is undeniable that the optimization becomes extremely complicated.

Furthermore, in optimizations that eliminate wasteful locking by moving a branch instruction between two instructions that cause an interlock, it is not always possible to place the nop instruction in a position that can be optimized by scheduling. .

The object of the present invention is to provide an electronic computer that has been made in consideration of such circumstances.

[Structure of the Invention (Means for Solving the Problems)] An electronic computer according to the present invention has a delayed branch instruction whose delay slot length is variable, or a plurality of delayed branch instructions whose delay slot lengths are different. The present invention is characterized in that the execution of a delayed branch instruction is delayed and controlled according to the value of the instruction's delay slot length.

In particular, the delay control of execution of the delayed branch instruction is performed by storing information regarding the delay slot length, and changing the value of the information regarding the delay slot length in accordance with the instruction cycle in the process of executing an instruction in the delay slot; This method is characterized in that it is determined whether or not to execute a branch depending on the value.

(Function) According to the present invention, the delay slot length of a delayed branch instruction is varied, and execution of a branch is controlled according to the delay slot length. has a delayed branch instruction with a variable delay slot length, and is realized by a microprocessor equipped with an instruction fetch unit configured as shown in FIG.

A delayed branch instruction with a variable delay slot length as described above is marked as brd(N) in the case of an unconditional branch instruction, and cbrd in the case of a conditional branch instruction, where the delay slot length is [N]. ” (N).For example, for an instruction sequence as shown in FIG. 2, the delayed branch instruction brd (N) whose delay slot length is [N] is
) is followed by the instruction sequence <opel>.

<ope2>, -, <opeN> are executed in order within the delay slot period set by the delayed branch instruction brd(N), and then, after passing through the delay slot [N], the delayed branch instruction brd( <Qpe>, which is the branch destination instruction of N), is executed.

In other words, since the present invention handles delayed branch instructions with variable delay slot lengths, the branch destination of the delayed branch instruction is set several slots ahead as shown in FIG. 3(a).
), at most one instruction can be executed during that delay slot. Therefore, as described above, various constraints arise in optimizing the instruction code sequence, making optimization difficult.

Hereinafter, a solution to the above-mentioned problem using a delayed branch instruction having a variable delay slot length will be explained.

First, for the instruction sequence shown in FIG. 11(a) mentioned above, the problem can be solved by using, for example, an unconditional branch instruction brd(2) with a delay slot length of [2]. can do. That is, in this case, for example, as shown in FIG. 4(a), the unconditional branch instruction b of the branch source
Change the branch destination of rd to the branch destination of the unconditional branch instruction brd (brd^-brd B ), and set the delay slot length to [2] (brd B
-”brd(N) B) Optimization can be performed.

In this case, unlike the optimization shown in FIG. 11(b), there is no need to consider either the instructions <opel> or <ope2>. However, the command <opel><op
It is necessary to fully consider the possibility of an interpolation between e2>. Such a new optimization is very simple and has a very high probability of success.

On the other hand, for an instruction sequence as shown in FIG. 12(a), for example, a conditional branch instruction cbrd(2) with a delay slot length [2] is prepared in the same manner. If you use such a conditional branch instruction cbrd(2), you can change the branch instruction cbrd cc, ^ from the branch source to cbrd(2) cc,B in the same way as in the case of the unconditional branch above. Figure 4 (
It becomes possible to optimize as shown in b).

In this case as well, there is no need to move the instruction <0pe1> before the branch instruction cbrd as in the optimization shown in FIG. 12(b) described above, so the instruction <opel> There is no need to consider whether or not to change it. Furthermore, unlike the optimization shown in FIG. 12(C), there is no need to insert a new branch instruction, so it is possible to reliably shorten the program execution time.

Using the conditional branch instruction cbrd" (2), change the conditional branch instruction cbrd' cc, A to cbrd" (2) cc, B
By changing, for example, optimization as shown in FIG. 4(C) becomes possible. Furthermore, the conditional branch instruction cbrd
' cancels the execution of the instruction existing in the delay slot when the condition is not satisfied. In this case as well, there is no need to insert a new branch instruction as in the optimization shown in FIG. 13(b) described above, so that the execution time of the program can be reliably shortened.

Incidentally, as shown in FIG. 5(a), the command <opel><op
Consider an instruction sequence in which a nop instruction for preventing an interlock is placed between e2>, followed by an instruction <opeM+l:> and a branch instruction brB. Conventionally,
Such an instruction sequence would not have been optimized unless M of the instruction <opeM+1> was [1].

Such an instruction sequence can generally be rearranged, for example, as shown in FIG. 6(a) by instruction scheduling. In the case of an instruction sequence scheduled in this manner, the branch instruction br described above represents an unconditional branch instruction with a delay slot length [0].

It should be noted that it is possible to similarly optimize the delayed branch instruction brcl in which the entire delay slot/soto period is filled with nop instructions. can be directly optimized as shown in FIG. 5(b). Therefore, by taking the trouble to schedule the instruction sequence shown in Figure 5(a),
There is no need to convert it into an instruction sequence as shown in Figure (a), and optimization can be performed very easily.

By introducing a branch instruction with a variable delay slot length in this way, the electronic computer according to the present invention solves the complexity of optimization that has conventionally been a problem, and moreover, Even for instruction sequences that do not become
This can be effectively optimized.

Generally speaking, the argument that the delay slot length increases is based on the premise that the delay slot length is fixed. However, if the delay slot length (period) is variable as described above,
On the other hand, the existence of delayed branch instructions with long delay slot lengths reduces the constraints on the instructions that can be moved within the long delay slot period, which brings about several advantages from an optimization perspective. Ru.

One of them, as mentioned above, is that optimization can be performed simply, and that it is also possible to perform optimization on instruction sequences that were not targets of optimization in the past. Another advantage is that the above-described new optimization method can be generalized and applied to instruction sequences including newly introduced delayed branch instructions with variable delay slot lengths.

A generalized application of this new optimization method will be explained. For example, considering the generalization of the optimization shown in FIG. 4(a) mentioned above, in this case, as shown in FIG. 7(a), the delayed branch instruction b with the delay slot length [M] of the branch source is
The branch destination of rd(M) replaces the branch destination of delayed branch instruction brd(M) with the branch destination of the delayed branch instruction brd(N) at the branch destination (brd(M)A−brd(M+N)B)
This makes it possible to optimize as shown in FIG. 7(b). For this optimization, any instructions moved within the delay slot need not be nap instructions. However, the command <open> and the command <opeM+
It is necessary to be careful about the interlock between 1> and 1>.

Similarly, an instruction sequence including the conditional delayed branch instruction cbrd(M) cc, ^ with variable delay slot length as shown in FIG. 8(a) can also be optimized as shown in FIG. 8(b). A conditional delayed branch instruction cbrd" (M) ce, A with variable delay slot length as shown in FIG. 9(a).
It is also possible to optimize an instruction sequence including the above as shown in FIG. 9(b).

In either case, consecutive instructions <open>.

It is necessary to be careful about the interlock with <opeM+1>, but since the instruction does not move to the position before the conditional branch instruction, it is difficult to determine whether the condition code will change or not. There is no need to be careful.

Columns <opel>, <ope2>, -=, <ope
M+N> and those that can be brought out from within the delay slot period can be moved to a position before the delayed branch instruction, for example, thereby reducing the required delay slot length to a considerable extent. It is also possible to use a long instruction sequence within the delay slot period as a new optimization target, or to convert it into an instruction sequence that becomes a new optimization target through scheduling. Therefore, even if branch instructions with variable delay slot lengths are introduced, conventional optimization techniques can be generalized as they are, the complexity of optimization can be eliminated, and various instruction sequences can be effectively optimized. It becomes possible to execute columns efficiently.

In addition, FIG. 10(a) shows the commands <opeD, copy2
An example of an instruction sequence in which a nop instruction is placed between > and a nop instruction to prevent interpolation, followed by a conditional branch instruction is shown. In this case, for example, as shown in FIG. 10(b), the conditional branch instruction is moved to the position of the nop instruction, and the nop You can erase commands and eliminate wasteful use of slots. This is possible only for losses. Also, in this way, the conditional branch instruction is
Of course, when moving to the position of the op instruction, it is necessary to take care not to create a new interpolation between the consecutive instructions <opeM+1> and (opeM+2>).

Next, electronic calculation 8! executes an instruction sequence including a delayed branch instruction with a variable delay slot length as described above! (microprocessor) instruction fetch unit will be explained. The second instruction fetch section is configured as shown in FIG. 1, as described above.

In FIG. 1, an instruction briefetch register 1 sequentially briefetches instructions from a program memory (not shown) via a cache bus 2 under the control of a program counter 3, which will be described later.

The instruction fetched into the instruction briefetch register 1 is decoded by the decoder 4 and interpreted. If the instruction is a delayed branch instruction having a variable delay slot length, the value of the delay slot length is stored in branch counter 5, and the branch destination address is stored in branch destination address register 8. If the instruction decoded by the decoder 4 is a normal branch instruction, the branch destination address of the branch instruction is stored in the program counter 3 as is.

-If the instruction decoded by the decoder 4 is the upper one, the program counter 3 is only incremented as the instruction is executed.

Now, if the value indicating the delay slot length stored therein is 1 or more, the branch counter 5 decrements it until it becomes 0 in response to the clock associated with the execution of the instruction.

In other words, when a value indicating the delay slot length of a delayed branch instruction is stored in the branch counter 5 by decoding, the value stored in the branch counter 5 is decremented as the slot progresses as the instruction is executed. The remaining slot period of the delay slot set by is shown. However, the value of this branch 5 is compared with the set value [1] in the comparator 7, and when a match is detected, it is determined that the delay slot period has ended. At this point, the value stored in the branch destination address register 6 (branch destination address) is transferred to the program counter 3.

The go selector 8 normally controls reading of instructions from the program counter, and executes instruction branching by selecting a delayed address as described above.

In other words, in this instruction fetch section, when a delayed branch instruction is given, by measuring the delay slot length of the delayed branch instruction using the branch counter 5, the instruction fetch section executes the delayed branch instruction only with the above-mentioned delay slot/soto long phrase. is configured to be delayed.

According to the instruction processing section configured in this way, for example, as shown in FIG. Since the delay slot period is set, multiple other instructions can be smoothly executed using this delay slot period.

By the way, conventionally, the delay slot length of a delayed branch instruction is fixed to [1], so at most one instruction can be executed within the delay slot period (1 slot soto) as shown in FIG. 3(b). can only be executed.

As a result, when optimizing instruction code as described above, various problems arise due to the constraints, such as moving an instruction to be executed before executing a delayed branch instruction. Ta.

In this regard, an example using a variable-length delayed branch instruction: ＼゛ ' - It becomes possible to efficiently execute multiple instructions.

As a result, it becomes possible to easily optimize the instruction sequence.

In addition, when performing the instruction code optimization described above, prepare arithmetic operation instructions and logical operation instructions that do not change the condition code, in addition to arithmetic operation instructions and logical operation instructions that change the condition code. Both are useful. In this way, for example, in the case of an operation that does not require condition determination, the possibility of optimization can be further increased by using an instruction that does not change the condition code.

Also, preparing separate arithmetic operation instructions and logical operation instructions that do not change the condition code increases the possibility that the instruction in the delay slot of the conditional branch instruction can be moved before the conditional branch instruction, so it is optimal. This can be said to further increase the degree of freedom in

Note that the present invention is not limited to the embodiments described above. For example, a method for providing information regarding the delay slot length in a delayed branch instruction is to prepare a field for directly specifying the delay slot length in the instruction code of the delayed branch instruction, or to provide a field for directly specifying the delay slot length in the instruction code of the delayed branch instruction. It is possible to omit the branch counter 5 for storing information regarding the delay slot length.If the branch counter 5 is omitted, for example, the information regarding the delay slot length may be incorporated into the logic of the control section of the processor. You can also store information about the delay slot length in a register or memory.
The control may be performed by specifying a register number or memory address. In addition, the present invention can be implemented with various modifications without departing from the gist thereof.

[Effects of the Invention] As detailed above, according to the present invention, when the branch destination of a delayed branch instruction is a delayed branch instruction, or when there is a nop instruction several steps before the delayed branch instruction, Now, it becomes possible to easily optimize a complicated instruction sequence and execute the instructions efficiently.

Moreover, the constraints on optimization can be significantly relaxed, and it is now possible to optimize some instruction sequences that were not previously subject to optimization. It has great practical effects.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the configuration of an instruction fetch unit that executes a delayed branch instruction according to an embodiment of the present invention, and FIG. 2 is a diagram showing the execution order of an instruction string including a delayed branch instruction in the present invention.
FIG. 3 is a diagram showing pipeline processing of delayed branch instructions, and FIGS. 4 to 10 are diagrams each showing a method of optimizing an instruction sequence including delayed branch instructions according to the present invention. Also the first
1 to 14 are diagrams each showing a conventional optimization method, and FIG. 15 is a diagram showing the occurrence of an interlock and its avoidance. ]...Instruction briefetch register, 2...Cache bus, 3...Program counter, 4...
Decoder, 5... Branch counter, 6... Branch destination address register, 7... Comparator, 8... Selector. Applicant Ken Sugiyu, Director of the Agency of Industrial Science and Technology

Claims (2)

[Claims] (1) Having a delayed branch instruction with variable delay slot length or multiple delayed branch instructions with different delay slot lengths,
An electronic computer characterized in that execution of a delayed branch instruction is delayed-controlled in accordance with a value of a delay slot length of the delayed branch instruction. (2) Delay control of execution of delayed branch instructions stores information regarding the delay slot length of the delayed branch instruction, and in the process of executing an instruction within the delay slot, information regarding the delay slot length is stored in accordance with the instruction cycle. 2. The computer according to claim 1, wherein the computer changes a value and determines whether or not to execute the branch depending on the value.