JPH0778736B2 - Electronic computer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) The present invention relates to an electronic computer that efficiently executes instructions using delayed branch instructions having different delay slot lengths.

(Prior Art) Recently, a microprocessor having a RISC (Reduced Instruction Set Computer) type architecture has attracted attention. In this type of microprocessor, it is possible to execute instructions without disturbing the flow of pipeline processing.
It is an important issue to fully demonstrate its performance.

A branch instruction is one of the causes of the disturbance of the pipeline processing described above. That is, in the pipeline processing, decoding of an instruction already fetched in the previous phase and fetching of the next instruction are performed in parallel in the same phase. At this time, if the decode interprets that the instruction type is branch, it is necessary to cancel the next instruction fetched as described above and fetch the branch destination instruction of the branch instruction again. Such re-execution of instruction fetch causes a clock loss, which causes disturbance of pipeline processing.

As a means for solving the problem caused by the disturbance of the pipeline processing due to such a branch instruction, for example, “DJLilja,“ Reducing the Branch Penalty in Pipelined Process
ors, "Computer, July, 1988, pp.47-55", etc., static branch prediction (Dynamic Branch Prediction) delayed branch (Delayed Branch) ) It is considered to adopt methods such as Loop Buffers.

The delay branch instruction used in the above-described delay branch method is
Immediately after the execution of the instruction (delayed branch instruction), a delay slot of a fixed length is set, and the instruction in this delay slot period is executed before the execution of the delayed branch instruction. The delay slot length of this delay branch instruction is determined according to the contents of processing in each stage of the number of stages of pipeline processing. For example, in "Berkeley RISC II" or the like, a delay branch instruction having a delay slot length [1] is generally set.

At the time of decoding a branch instruction, the immediately following (next) instruction has already been fetched. Therefore, in general, when the branch of the instruction is confirmed by decoding, it is necessary to cancel the execution of the already fetched next instruction. In this regard, according to the delayed branch instruction, instead of canceling the next instruction, a nop (no operation) instruction is placed after the delayed branch instruction, and this n
The op instruction is executed as it is. As a result, it becomes possible to execute the processing substantially equivalent to the case of canceling the next instruction as described above, with simpler hardware and without disturbing the pipeline processing.

By the way, in an electronic computer having a delayed branch instruction of this kind, for example, an instruction immediately before the branch instruction, a branch destination instruction, or a non-branch destination instruction is brought into the delay slot period set by the delay branch instruction. be able to. By changing (shifting) the instruction execution order as described above, it becomes possible to optimize the instruction sequence (code).

The method of optimizing the code is described in detail in, for example, “TRGross and JL Hennessy.“ Optimizing Delayed Branchs, ”Proc. IEEE Micro-15, Oct. 1982, pp. 114-120”. By using such a code optimizing method, it becomes possible to efficiently execute the instruction sequence, for example, by effectively using the clock that originally did not execute any processing.

Here, a typical example of the code optimization method related to the above-mentioned delayed branch instruction will be described. One of the typical code optimization methods shown here is a branch destination a of a branch instruction A.
Is a branch instruction B, the branch destination a of the branch instruction A of the branch source is replaced with the branch destination b of the branch instruction B of the branch destination a. Another method is
Originally, this is an optimization method in which a useless clock is erased by bringing a branch instruction at the position of a nop instruction placed between two instructions that cause an interlock. The meaning of [interlock] used here will be described later.

First, let us consider the constraints when actually applying these optimization methods.

When the branch destination of the branch instruction A is the branch instruction B, the branch destination a of the branch source branch instruction A is replaced with the branch destination b of the branch instruction B of the branch destination a to reduce the number of branches. The optimal variation method is described below. However, here, it is considered that both the branch source branch instruction and the branch destination branch instruction are delayed branch instructions. Further, for simplification of description, the delay slot length of these delay branch instructions will be described as [1] here.

For example, as shown in FIG. 11 (a), when both the branch target and the branch source delay instructions are unconditional branch instructions (hereinafter, referred to as [brd]), each of these delay instructions does not exist. Conditional branch instructions brd A, brd B next instructions <ope1>, <ope2
If at least one of> is a nop instruction, this instruction string is used as the branch source unconditional branch instruction as shown in FIG. 11 (b).
brd A can be rewritten to brd B for optimization.

The instruction <ope> is n out of the instructions <ope1> and <ope2>.
The instruction that is not the op instruction is shown. The above command <
When both ope1> and <ope2> are nop instructions, the above instruction <ope> is also a nop instruction.

If neither of the instructions <ope1> and <ope2> is a nop instruction, the branch destination of the unconditional branch instruction of the branch source is rewritten (brd A → brd B), for example, as shown in FIG. 11 (c). ,
The instruction sequence can be optimized by moving (shifting) the instruction <ope1> before this unconditional branch instruction. However, if the instruction <ope1> is moved before the unconditional branch instruction brd, there is a risk of interlocking with the instruction that originally exists before the unconditional branch instruction brd. So in such a case, say no between those instructions.
It becomes necessary to insert the p instruction. Therefore, the 11th
The optimization shown in FIG. 6C is not always effective.

On the other hand, as shown in FIG. 12A, when the branch source is a conditional branch instruction (hereinafter, referred to as [cbrd]) and the branch destination is an unconditional branch instruction brd, The optimization can be performed in this way. That is, a conditional branch instruction
If cbrd executes an instruction in the delay slot period regardless of whether the condition is satisfied or not satisfied, for example, the branch destination of the conditional branch instruction cbrd is rewritten (cbrd cc, A as shown in FIG. 12B). → cbrd cc, B), the instruction <ope1> can be optimized by moving it before execution of the conditional branch instruction cbrd. However, such optimization can be performed only when the condition code does not change as a result of the execution of the instruction <ope1>.

By the way, the condition by executing the instruction <ope1>
If the code changes, the above <ope1> cannot be moved before the conditional branch instruction cbrd. In this case, however, the branch destination of the conditional branch instruction cbrd is rewritten (cbrd cc, A → cbrd cc, as shown in FIG. 12 (c), for example.
C), it can be optimized by setting the branch destination to the instruction <ope2>. However, for the basic block starting with label B :, the basic block immediately before it is the predecessor, and the last instruction of the basic block is neither a branch instruction nor present in the delay slot period of the delayed branch instruction. In this case, after the above-mentioned optimization, it is necessary to insert a branch instruction br B to the label B: before the label C :. Therefore, even if such optimization is performed, there is no guarantee that the execution time of the program will be shortened.

However, if the basic block starting with the label B: is generated only by a branch, it is not necessary to insert a new branch instruction as described above, and thus the above optimization cannot be said to be bad.

Next, as shown in FIG. 13A, for example, the conditional branch instruction of the branch source cancels the execution of the instruction existing in the delay slot period when the condition is not satisfied (hereinafter,
[Cbrd ^* ])). In this case, the optimization shown in FIG. 12 (b) cannot be performed, and the optimization shown in FIG. 13 (b) can be performed in the same manner as the optimization shown in FIG. 12 (c). As described above, the branch destination of the conditional branch instruction can be changed (cbrd ^* cc, A → cbrd ^* cc, B) to optimize it.

However, even in this case, even if the basic block immediately before the basic block starting with label B: is the predecessor, the last instruction of this basic block is not a branch instruction, and it exists in the delay slot period of the delayed branch instruction. If not, it is necessary to insert a branch instruction br B to the label B: before the label C: after the optimization. Therefore, even in this case, there is no guarantee that the execution time of the program will be shortened by the above-described optimization. However, if the entry into the basic block starting with the label B: above is caused only by a branch as described above, there is no need to insert a new branch instruction, so this optimization works very effectively. .

Finally, 2 that would cause an interlock by nature
We describe an optimization method that eliminates unnecessary clocks by bringing a branch instruction to the position of the nop instruction placed between two instructions.

Fig. 14 (a) shows 2 which causes an interlock.
An instruction string having a nop instruction between two instructions <ope1> and <ope2> is shown. Here, the above two instructions <ope1>, <op
The nop instruction inserted between e2> is the instruction <ope1>,
This is to prevent interlock caused by <ope2>.

The interlock described above has some dependency between a certain phase of the instruction <ope1> and a certain phase of the instruction <ope2>, and these instructions <ope1> and <ope2> are consecutively connected. When this is executed, the above-mentioned dependency relationship violates the causality, and as a result, a correct execution operation is not guaranteed.

For example, as shown in FIG. 15 (a), if the instruction <ope1> cannot execute the phase E of the instruction <ope2> until the instruction <ope1> finishes the phase M, if the instructions <ope1><ope2> are continuously executed, Lock occurs. Therefore, in such a case, it is necessary to prevent the interlock from occurring by placing a nop instruction between two consecutive instructions <ope1> and <ope2> as shown in FIG. 15 (b). .

In this case, for example, when the instruction next to the instruction <ope2> is the unconditional branch instruction br, the branch instruction br is changed to the delayed branch instruction brd as shown in FIG. By moving between ope1> and <ope2>, it is possible to eliminate a wasteful clock at the portion where the nop instruction was given. However, such optimization can be done only if the nop instruction is two before the br instruction (delay slot length + 1
Only before the slot). If such a condition is not satisfied, it is necessary to move the nop instruction to that position by, for example, instruction scheduling, and it is not always guaranteed that such a movement of the nop instruction is possible.

(Problems to be Solved by the Invention) In a microprocessor having a RISC-type architecture as described above, when the branch destinations of the delayed branch instructions are similar delayed branch instructions, the branch destination of the branch instruction of the branch source is It is possible to optimize the instruction code to replace the branch instruction at the branch destination with the branch destination. However, depending on the type of delay instruction, it is not always possible to optimize it due to various restrictions. In addition, it may be necessary to add a new branch instruction when performing optimization, and there is no guarantee that the execution time can be reduced. Therefore, considering these problems, the optimization is unavoidably complicated.

Further, in optimization in which a wasteful clock is eliminated by moving a branch instruction between two instructions that cause an interlock, it is not always possible to place it in an optimizable position by scheduling a nop instruction. .

The present invention has been made in view of such circumstances, and an object of the present invention is to solve the complexity of the optimization procedure of the instruction sequence and further to relax the constraint on the optimization. An object of the present invention is to provide an electronic computer capable of easily optimizing an actual instruction sequence and efficiently executing the instruction sequence without waste.

[Configuration of the Invention] (Means for Solving the Problem) An electronic computer according to the present invention is configured such that an instruction prefetch register that sequentially acquires instructions, a decoder that interprets the acquired instructions, and the interpreted instructions are In the case of a delay branch instruction having a variable delay slot length or a plurality of delay branch instructions having different delay slot lengths, a branch destination address register storing a branch destination address of the branch instruction and the interpreted instruction are In the case of a delay branch instruction having a variable length or a plurality of delay branch instructions having different delay slot lengths, the value of the delay slot length of the branch instruction is stored, and the storage is performed according to a clock signal for synchronizing the instructions. A branch counter for reducing the value of the delay slot length, a set value for determining the end of the delay slot period, and the branch counter And a comparator for detecting the end of the delay slot period when there is a match by the comparison, and a branch destination of the branch instruction when the instruction decoded by the decoder is not the delay branch instruction. When the address is stored and the instruction decoded by the decoder is not a branch instruction, the address next to the stored address is stored, and when the end of the delay slot period is detected, the branch destination is detected. A program counter in which the address stored in the address register is stored and a value stored in the branch destination address register when the end of the delay slot period is detected, and the end of the delay slot period is detected. If not, the value of the program counter is selected to control the instruction to be acquired next. And a branch destination of the unconditional branch instruction is a branch destination of the unconditional branch instruction of the branch source, and a branch destination of the unconditional branch instruction of the branch destination is Change to a delayed branch instruction with a delay slot length of [2], and further optimize the instruction immediately after the unconditional branch instruction at the branch destination after the instruction immediately after the unconditional branch instruction at the branch source, When the instruction sequence is arranged in the order of the first instruction, the nop instruction for preventing interlock, the second instruction, ..., The M + 1th (M is an integer) instruction, and the unconditional branch instruction, The nop instruction is changed to a delayed branch instruction in which the branch destination of the unconditional branch instruction is the branch destination and the delay slot length is [M], and optimization is performed to delete the unconditional branch instruction. , The branch destination of the delay branch instruction with delay slot length [M] is delayed Lot length [N] (N is an integer)
, The delay source of the branch source is the branch destination of the delay branch instruction of the branch destination, the delay slot value of the delay branch instruction of the branch source, and the delay branch instruction of the branch destination. Of delay instructions of the branch destination delay branch instruction is changed to a delay branch instruction having a delay slot length as a sum of the delay slot value of It is characterized by performing optimization for copying later, and further characterized by having a pipeline function.

(Operation) According to the present invention, the delay slot length of the delayed branch instruction is changed and the execution of the branch is controlled according to the delay slot length. Can be efficiently executed, and the constraint condition for optimizing the instruction sequence can be significantly relaxed. As a result, it becomes possible to optimize the instruction sequence easily and efficiently, and to reduce the instruction execution time without wasting the clock.

(Embodiment) An electronic computer according to the present invention includes an instruction fetch unit configured as shown in FIG. The instruction fetch unit includes an instruction prefetch register for sequentially acquiring instructions, a decoder for interpreting the acquired instructions, and a plurality of delayed branch instructions having different delay slot lengths or different delay slot lengths for the interpreted instructions. In case of the delayed branch instruction of
A branch destination address register for storing a branch destination address of the branch instruction; and the interpreted instruction is a delay branch instruction having a variable delay slot length or a plurality of delay branch instructions having different delay slot lengths, the branch A branch counter that stores the value of the delay slot length of the instruction and decreases the stored value of the delay slot length according to a clock signal for synchronizing the instruction, and a set value for determining the end of the delay slot period And a value stored in the branch counter, and a comparator for detecting the end of the delay slot period when there is a match by the comparison, and a case where the instruction decoded by the decoder is a branch instruction which is not the delayed branch instruction. Is stored when the branch destination address of the branch instruction is stored and the instruction decoded by the decoder is not a branch instruction. The address next to the current address is stored, and when the end of the delay slot period is detected, the program counter storing the address stored in the branch destination address register and the end of the delay slot period are detected. When the value is detected, the value stored in the branch destination address register is selected, and when the end of the delay slot period is not detected, the value of the program counter is selected to control the instruction to be acquired next. An electronic computer having a selector and further having a pipeline function is used.

When the delay slot length is [N], the delay branch instruction having the variable delay slot length is marked as brd (N) in the case of an unconditional branch instruction, and cbrd in the case of a conditional branch instruction. ^* Marked as (N). Then, for an instruction string as shown in FIG. 2, for example, an instruction string <ope1>, <ope2>, ..., <opeN following a delayed branch instruction brd (N) having a delay slot length of [N]. > Are sequentially executed within the delay slot period set by the delayed branch instruction brd (N), and after that, when the delay slot [N] is passed, the instruction at the branch destination of the preceding delayed branch instruction brd (N) is executed. It is supposed to execute a certain <ope>.

That is, in the present invention, since a delay branch instruction having a variable delay slot length is handled, the branch destination of the delay branch instruction is intentionally extended to a few slots ahead as shown in FIG. Is capable of executing multiple instructions. By the way, in the prior art, since the delay slot length of the delay branch instruction is fixedly set as [1], as shown in comparison with FIG. Can only execute the command. Therefore, as described above, various restrictions occur in optimizing the instruction code string, which causes a problem that the optimization becomes difficult.

Hereinafter, the solution of the above-mentioned problem by the delay branch instruction having such a variable delay slot length will be described.

First, with respect to the instruction sequence as shown in FIG. 11 (a), the unconditional branch instruction brd (2) whose delay slot length is [2] is used to solve the problem. You can That is, in this case, as shown in FIG. 4A, for example, the branch destination of the unconditional branch instruction brd of the branch source is changed to the branch destination of the unconditional branch instruction brd of the branch destination (brd A → brd B), and its delay slot length is [2], and the instruction immediately after the unconditional branch instruction at the branch destination is copied after the instruction immediately after the unconditional branch instruction at the branch source (brd B → brd (N) B) Optimization may be performed.

In this case, it is not necessary for any of the instructions <ope1> and <ope2> to be a nop instruction as in the optimization shown in FIG. 11 (b) described above. Further, unlike the optimization shown in FIG. 11 (c), since it is not necessary to move the instruction <ope1> before the branch instruction brd (N) B, the instruction <ope1> and the instruction immediately before it are not There is no need to consider interlocks between them. However, it is necessary to fully consider the possibility of interlocking between the instructions <ope1> and <ope2>. Such a new optimization is very simple and very likely to succeed.

On the other hand, for the instruction sequence shown in FIG. 12 (a),
For example, similarly, a conditional branch instruction with a delay slot length [2]
Prepare cbrd (2). Such a conditional branch instruction cbrd
If (2) is used, the branch instruction cbrd cc, A of the branch source is changed to cbod (2) cc, B in the same manner as the case of the unconditional branch.
By changing to, it becomes possible to optimize as shown in FIG.

Also in this case, it is not necessary to move the instruction <ope1> before the branch instruction cbrd as in the optimization shown in FIG. 12 (b), so the instruction <ope1> changes the condition code. There is no need to consider whether or not. Further, unlike the optimization shown in FIG. 12 (c), it is not necessary to insert a new branch instruction, so that the execution time of the program can be surely shortened.

Also for the instruction sequence as shown in FIG. 13 (a), for example, the conditional branch instruction cb with the delay slot length [2]
Prepare rd ^* (2). And this conditional branch instruction cbrd
^{* Using} (2), the conditional branch instruction cbrd ^* cc, A is cbrd ^*
(2) By changing to cc, B, for example, Fig. 4 (c)
It is possible to optimize as shown in. The conditional branch instruction cbrd ^* cancels the execution of the instruction existing in the delay slot when the condition is not satisfied. Also in this case, since it is not necessary to insert a new branch instruction as in the optimization shown in FIG. 13 (b) described above, the execution time of the program can be surely shortened.

As shown in FIG. 5A, the instruction sequence is the first instruction, the nop instruction for preventing interlock, the second instruction,
Let us consider a case where the M + 1th (M is an integer) instruction and the unconditional branch instruction are arranged in this order. Conventionally, in such an instruction sequence, M of the instruction <opeM + 1> is [1].
Otherwise, it would not have been the object of optimization.

Such an instruction sequence can be generally rearranged by instruction scheduling, for example, as shown in FIG. 6 (a). In the case of an instruction sequence scheduled in this way, the above nop instruction is the branch instruction br 2
Only when placed before the slot (delay slot length + 1 slot before), that is, when the form becomes [M = 1], optimization as shown in FIG. 6 (b) is possible. However, the branch instruction br represents an unconditional branch instruction having a delay slot length [0]. In the case of the delayed branch instruction brd in which the entire delay slot period is filled with the nop instruction, the optimization can be similarly performed.

However, if the delay branch instruction having the delay slot length [M] described above is used, for example, the instruction sequence shown in FIG.
Even in the case where scheduling cannot be performed as shown in FIG. 7A, the instruction sequence is changed to the fifth (b)
Nop to prevent the interlock as shown in
Directly optimizing an instruction by changing it to a delayed branch instruction whose branch destination is the branch destination and whose delay slot length is [M], and further deleting the branch instruction. Is possible. Therefore, there is no need to purposely schedule the instruction sequence as shown in FIG. 5A and convert it into the instruction sequence as shown in FIG.
The optimization can be performed very easily.

By introducing a branch instruction having a variable delay slot length in this way, in the electronic computer according to the present invention, the complexity of optimization, which has been a problem in the past, can be solved. Even for the instruction sequence that did not become,
It is possible to effectively optimize this.

By the way, it is generally said that the optimization becomes difficult as the delay slot length increases. The reason is that there are restrictions on the types of instructions that can be moved within the delay slot period. However, such an argument is established based on the assumption that the delay slot length is fixed. However, as mentioned above, the delay slot length (period)
When the variable is variable, on the contrary, the existence of a delay branch instruction having a long delay slot length reduces the restrictions on the instructions that can be moved within the long delay slot period. There are advantages.

One of them is, as described above, that the optimization can be performed simply, and that it is possible to perform the optimization even for an instruction string that has not been conventionally targeted for optimization. The other is that the new optimization method described above can be generalized and applied to the newly introduced instruction sequence including a delayed branch instruction with a variable delay slot length.

A generalized application of this new optimization technique will be described. For example, considering the generalization of the optimization shown in FIG. 4A, in this case, as shown in FIG. 7A, the delayed branch instruction br having the delay slot length [M] of the branch source is br
The branch destination of d (M) can be generalized as a delay branch instruction brd (N) having a delay slot length [N].

However, in this case, the branch source delayed branch instruction brd
The branch destination of (M) is the sum of the value of the delay slot of the delayed branch instruction of the branch destination and the value of the delay slot of the delayed branch instruction of the branch destination of the branch destination of the delayed branch instruction of the branch destination. To the delay branch instruction with the delay slot length of (brd
(M) A → brd (M + N) B), and N instructions after the delayed branch instruction of the branch destination are M after the delayed branch instruction of the branch source.
By copying after each instruction, it becomes possible to optimize as shown in FIG. 7 (b). This optimization does not require that any instruction moved within that delay slot period be a nop instruction. However, it is necessary to pay attention to the interlock between the instruction <opeM> and the instruction <opeM + 1>.

Similarly, as shown in FIG. 8 (b), the instruction sequence including the conditional delay branch instruction cbrd (M) cc, A whose delay slot length is variable can be optimized as shown in FIG. 8 (b). It is possible to optimize the instruction sequence including the conditional delay branch instruction cbrd ^* (M) cc, A whose delay slot length is variable as shown in FIG. 9 (a) as shown in FIG. 9 (b). You can

In either case, consecutive instructions <opeM>, <op
It is necessary to pay sufficient attention to the interlock with eM + 1>, but since the instruction does not move to the position before the conditional branch instruction, it is necessary to pay attention to whether the condition code changes. Absent.

However, when the optimization is advanced in this way, the delay slot length of the branch instruction tends to be long.

However, the instruction sequence <ope1 placed within the delay slot period
, <Ope2>, ..., <opeM + N>, and those that can be output to the outside from within the delay slot period are, for example, moved to the position before the delay branch instruction to have a required delay slot length. It can be shortened. It is also possible to directly target a long instruction sequence within the delay slot period as a new optimization target or convert it into a new optimization target instruction sequence by scheduling. Therefore, even if a branch instruction with a variable delay slot length is introduced, the conventional optimization method is generalized as it is, the complexity of optimization is eliminated, various instruction sequences are effectively optimized, and It becomes possible to execute the column efficiently.

Further, FIG. 10 (a) shows that between the instructions <ope1> and <ope2>,
An example of an instruction string in which a nop instruction for preventing interlock is placed and a conditional branch instruction appears after that is shown. In this case, for example, as shown in FIG. 10B, the conditional branch instruction is moved to the position of the nop instruction, and the instructions <ope1>, <ope2
It is possible to eliminate the wasteful use of slots by deleting the nop instruction that was purposely provided to prevent interlock during>. However, it is not always possible to erase such a waste slot, and the instruction <ope2>, ...,
It is possible only when <opeM + 1> does not change the condition code. Further, when moving the conditional branch instruction to the position of the nop instruction in this way, it is necessary to take care so that a new interlock does not occur between the consecutive instructions <opeM + 1> and <opeM + 2>. Of course.

Next, the instruction fetch unit of the electronic computer (microprocessor) that executes the instruction sequence including the delayed branch instruction having the variable delay slot length described above will be described. This instruction fetch unit is configured as shown in FIG. 1 as described above.

In FIG. 1, an instruction prefetch register 1 sequentially prefetches instructions from a program memory (not shown) via a cache bus 2 under the control of a program counter 3 described later. The instruction fetched in the instruction prefetch register 1 is decoded by the decoder 4 and the instruction is interpreted. If the instruction is a delayed branch instruction having a variable delay slot length, the value of the delay slot length is stored in the branch counter 5, and the branch destination address is stored in the branch destination address register 6. If the instruction decoded by the decoder 4 is a normal branch instruction, the branch destination address of the branch instruction is stored in the program counter 3 as it is.

When the instruction decoded by the decoder 4 is a general instruction other than the branch instruction described above, the program counter 3 is only incremented as the instruction is executed.

When the position indicating the delay slot length stored therein is [1] or more, the branch counter 5 receives the clock associated with the execution of the instruction and decrements until it reaches [0]. That is, when the value indicating the delay slot length is stored in the branch counter 5 by decoding the delayed branch instruction, the value stored in the branch counter 5 is decremented as the slot progresses as the instruction is executed, and the delayed branch instruction is decremented. The remaining slot period of the delay slot set by is shown. Then, the value of the branch counter 5 is compared with the set value [1] by the comparator 7, and when the coincidence is detected, it is determined as the end of the delay slot period. At this point, the value (branch destination address) stored in the branch destination address register 6 is the program
It is moved to the counter 3.

The selector 8 normally selects the value of the program counter 3 to control the reading of an instruction from the program memory, and when the end of the delay slot period is detected as described above, the branch destination address register. By selecting the value (branch destination address) stored in 6, the instruction branch is realized.

That is, in this instruction fetch unit, when a delayed branch instruction is given, the delay slot length of the delayed branch instruction is measured by the branch counter 5 to intentionally send the execution of the delayed branch instruction by the delay slot length. Is configured to let.

Thus, according to the instruction fetch unit configured as described above, for example, as shown in FIG. 3A, after a delayed branch instruction is decoded, there is a delay period over a plurality of slots before the instruction at the branch destination is executed. Since the delay slot period is set, it is possible to smoothly execute a plurality of other instructions by using this delay slot period.

Incidentally, in the prior art, since the delay slot length of the delayed branch instruction is fixed to [1], only at most one instruction is executed within the delay slot period (1 slot) as shown in FIG. 3 (b). I can't. As a result, in the case of optimizing the instruction code as described above, various problems occur due to the restriction, and for example, a problem such as moving an instruction so that it is executed before the execution of the delayed branch instruction occurs. there were. In this respect, according to the embodiment computer using the variable-length delayed branch instruction, the phase in which the instruction of the branch destination of the delayed branch instruction is executed can be intentionally delayed. Multiple instructions can be efficiently executed. As a result, this can be easily done even when optimizing the instruction sequence.

When optimizing the instruction code described above, it is possible to prepare an arithmetic operation instruction or a logical operation instruction that does not change the condition code, in addition to the arithmetic operation instruction or the logical operation instruction that changes the condition code. It is useful. By doing so, for example, in the case of an operation that does not require the condition determination, it is possible to further increase the optimization possibility by using the instruction that does not change the condition code.

In addition, preparing an arithmetic operation instruction or a logical operation instruction that does not change the condition code increases the possibility that the instruction in the delay slot of the conditional branch instruction can be moved before the conditional branch instruction. It can be said that the degree of freedom of is further increased.

The present invention is not limited to the above embodiment. For example, as a method of giving information about the delay slot length to the delay branch instruction, a field for directly designating the delay slot length is prepared in the instruction code of the delay branch instruction, or a plurality of delay branch instructions having different delay slot lengths are prepared. The instructions may be prepared as independent instructions. In this case, the branch counter 5 for storing the information about the delay slot length can be omitted. When the branch counter 5 is omitted, for example, information about the delay slot length may be incorporated as the logic of the control unit of the processor. Alternatively, the information about the delay slot length may be stored in a register or a memory, and the control may be performed by designating a register number or a memory address. In addition, the present invention can be variously modified and implemented without departing from the scope of the invention.

[Effects of the Invention] As described in detail above, according to the present invention, the delay branch instruction has a branch destination of a delay branch instruction or a nop instruction several steps before the delay branch instruction. Thus, even for an instruction sequence that has been complicated to optimize, it is possible to easily optimize the instruction sequence and efficiently execute the instruction. Moreover, the constraint conditions for optimization can be significantly relaxed, and it is possible to perform optimization on some instruction sequences that were not previously targeted for optimization. Great effect can be achieved.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of an instruction fetch unit for executing a delayed branch instruction according to an embodiment of the present invention, and FIG. 2 is a diagram showing an execution sequence of an instruction string including a delayed branch instruction in the present invention,
FIG. 3 is a diagram showing pipeline processing of a delayed branch instruction, and FIGS. 4 to 10 are diagrams showing a method of optimizing an instruction string including a delayed branch instruction according to the present invention. Further, FIGS. 11 to 14 are diagrams showing a conventional optimization method and FIG.
FIG. 15 is a diagram showing a situation of occurrence and avoidance of interlock. 1 ... Instruction prefetch register, 2 ... Cache bus, 3 ... Program counter, 4 ... Decoder, 5 ... Branch counter, 6 ... Branch destination address register, 7 ... Comparator, 8 ... …selector.

Claims (1)

[Claims] 1. An instruction prefetch register for sequentially acquiring instructions, a decoder for interpreting the acquired instructions, and a plurality of delay branch instructions having different delay slot lengths or different delay slot lengths for the interpreted instructions. In the case of the delayed branch instruction, the branch destination address register for storing the branch destination address of the branch instruction, and the interpreted instruction are a delay branch instruction having a variable delay slot length or a plurality of delays having different delay slot lengths. In the case of a branch instruction, a value of the delay slot length of the branch instruction is stored, and a branch counter that decreases the stored value of the delay slot length according to a clock signal for synchronizing the instruction, and a delay slot period The set value for determining the end is compared with the value stored in the branch counter, and if there is a match by the comparison, the delay slot period A comparator for detecting the end of the interval, and if the instruction decoded by the decoder is a branch instruction other than the delayed branch instruction, the branch destination address of the branch instruction is stored and the instruction decoded by the decoder branches. If the instruction is not an instruction, the address next to the stored address is stored, and if the end of the delay slot period is detected, the address stored in the branch destination address register is stored. A counter and a value stored in the branch destination address register when the end of the delay slot period is detected, and a value of the program counter when the end of the delay slot period is not detected. , The branch to which the unconditional branch instruction branches is unconditional When the instruction is an instruction, the branch destination of the unconditional branch instruction of the branch source is changed to a delayed branch instruction in which the branch destination of the unconditional branch instruction of the branch destination is the branch destination and the delay slot length is [2], Further, the instruction sequence immediately after the unconditional branch instruction at the branch destination is copied after the instruction immediately after the unconditional branch instruction at the branch source, and the instruction sequence is the first instruction, no for preventing interlock.
p instruction, second instruction, ..., M + 1th (M is an integer)
When the unconditional branch instruction and the unconditional branch instruction are arranged in this order, the nop instruction becomes a delayed branch instruction whose branch destination is the unconditional branch instruction and whose delay slot length is [M]. The modification is further performed, and optimization is performed to delete the unconditional branch instruction. The branch destination of the delay branch instruction having the delay slot length [M] is the delay branch instruction having the delay slot length [N] (N is an integer). , The branch source delayed branch instruction is the branch destination of the branch destination delayed branch instruction, and the delay slot value of the branch source delayed branch instruction and the delay slot of the branch destination delayed branch instruction Optimal to change to a delayed branch instruction having a sum of the value and the delay slot length, and to copy N instructions after the delayed branch instruction at the branch destination after M instructions after the delayed branch instruction at the branch source A pipeline mechanism characterized by An electronic calculator to have.