JPH04190675A - Protecting device for power semiconductor - Google Patents

Protecting device for power semiconductor

Info

Publication number
JPH04190675A
JPH04190675A JP31391290A JP31391290A JPH04190675A JP H04190675 A JPH04190675 A JP H04190675A JP 31391290 A JP31391290 A JP 31391290A JP 31391290 A JP31391290 A JP 31391290A JP H04190675 A JPH04190675 A JP H04190675A
Authority
JP
Japan
Prior art keywords
gate
pulse
voltage
gto
comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31391290A
Other languages
Japanese (ja)
Inventor
Kazuhiro Yamada
和博 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP31391290A priority Critical patent/JPH04190675A/en
Publication of JPH04190675A publication Critical patent/JPH04190675A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the destruction of an element caused by an imperfect gate pulse by providing a function which monitors the pulse width and voltage of a gate signal given to the element. CONSTITUTION:When a gate pulse is supplied to a GTO, a comparator 8 compares the voltage of the gate pulse and, when the voltage is higher than the lowest igniting voltage of the GTO, the output of the comparator 8 is inverted. A one-shot multivibrator 10 is connected to the output of the comparator 8 and generates a pulse of a prescribed time width on the basis of the output of the comparator 8. The pulse width is set to the minimum time required for igniting the GTO. Then the drive circuit of the next stage amplifies the pulse to a voltage required for igniting the GTO and gives the amplified pulse to the gate of the GTO to turn on the GTO.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、GTO等を用いたVVVFインバータ等の素
子の保護方式に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a protection system for elements such as VVVF inverters using GTO and the like.

〔従来の技術〕[Conventional technology]

第21回 鉄道におけるサイバネティクス利用国内シン
ポジウム論文集 (1)高周波4象限チヨツパ (2)直流3000V電気機関車用670 KVA補機
インバータの開発 に挙げられている主回路素子の制御方法はいずれもゲー
トパルス作成(発生)回路の後段にゲートアンプを設け
、これにより素子の点弧に必要な電力に増幅し素子のゲ
ートにゲートパルスとして与える方式となっている。
Proceedings of the 21st Domestic Symposium on the Use of Cybernetics in Railways (1) High-frequency 4-quadrant chopper (2) The control methods for main circuit elements listed in the development of 670 KVA auxiliary inverter for 3000 V DC electric locomotives are all gate pulses. A gate amplifier is provided at the subsequent stage of the creation (generation) circuit, and this amplifies the power necessary for ignition of the element, which is then applied to the gate of the element as a gate pulse.

この種の方式では、これらゲートアンプ以降でての不具
合、あるいは、誤動作により不完全ゲートパルスが発生
した場合にはなんの保護もなく、場合によっては、点弧
電力不足による素子の破壊を招く必要性がある。
In this type of system, there is no protection in the event that an incomplete gate pulse is generated due to a malfunction or malfunction after the gate amplifier, and in some cases, the element may be destroyed due to insufficient ignition power. There is sex.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来技術では、素子の保護はその素子に流れる電流や、
素子の電圧分担を監視する等の制御の結果により、いわ
ゆる、主回路側での検出結果によりなされていた。
In conventional technology, the protection of an element is based on the current flowing through the element,
This has been done based on the results of control such as monitoring the voltage sharing of the elements, so-called detection results on the main circuit side.

また、素子のゲート回路はゲートドライブ回路と呼ばれ
るゲート能動回路に接続されて用いられる。が、従来は
このゲートドライブ回路の出力が、直接、素子のゲート
に接続されており、ゲートパルスのチエツクを行う機能
がなかったため、ゲートドライブ回路以降で不完全ゲー
トパルスが発生しても、その検出がなされないため、不
完全ゲートパルスについては必ずしも充分な素子の保護
がなされておらず、場合によっては、素子の破壊を招く
という問題があった。
Furthermore, the gate circuit of the element is used while being connected to a gate active circuit called a gate drive circuit. However, in the past, the output of this gate drive circuit was directly connected to the gate of the element, and there was no function to check the gate pulse, so even if an incomplete gate pulse occurred after the gate drive circuit, it could not be detected. Since no detection is performed, the device is not always sufficiently protected against incomplete gate pulses, and in some cases, the device may be destroyed.

本発明の目的は、不完全ゲートパルスによる素子の破壊
を防ぐことにある。
An object of the present invention is to prevent device destruction due to incomplete gate pulses.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的を達成するために、本発明は素子に与えるゲー
トパルスを常時監視する手段を設け、これにより、ゲー
トパルスの素子への印加時間及びその電圧あるいは電流
を監視し、印加電圧(電流)が所定の値を越えたら強制
的に、ゲートパルスを所定時間幅、所定電圧に変換し素
子に印加する機能を設ける事により、素子tこ常に正規
のゲートパルスを与えることにより、不完全ゲートパル
スによる素子の破壊を防ぐようにしたものである。
In order to achieve the above object, the present invention provides a means for constantly monitoring the gate pulse applied to the element, thereby monitoring the application time of the gate pulse to the element and its voltage or current, and adjusting the applied voltage (current). By providing a function that forcibly converts the gate pulse into a predetermined voltage with a predetermined time width and applies it to the element when a predetermined value is exceeded, it is possible to prevent incomplete gate pulses by applying a regular gate pulse to the element. This is to prevent destruction of the element.

〔作用〕[Effect]

ゲートパルス監視部は素子のゲートに与えられるゲート
パルスを、直接、監視し、その電圧(電流)が素子の最
小点弧電圧(電流)以上であることを検出する。
The gate pulse monitoring section directly monitors the gate pulse applied to the gate of the element, and detects that the voltage (current) is higher than the minimum firing voltage (current) of the element.

検出結果は、ゲートパルス発生部に与えられる。The detection result is given to the gate pulse generator.

ゲートパルス発生部では、この信号に基づき、素子に最
小限必要な時間幅と素子の点弧に充分な電圧(電流)を
もったゲートパルスを発生する。
Based on this signal, the gate pulse generator generates a gate pulse having the minimum necessary time width for the device and a voltage (current) sufficient for igniting the device.

このゲートパルスと先に述べたゲートパルスとを重ねあ
わせる事により、常に素子に必要な時間と電圧をもった
ゲートパルスを与える事ができ、これにより、素子の不
完全ゲートパルスによる、素子の破壊を未然に防ぐこと
ができる。
By superimposing this gate pulse with the gate pulse mentioned above, it is possible to always give a gate pulse with the necessary time and voltage to the device, and this allows the device to be destroyed due to an incomplete gate pulse. can be prevented from occurring.

〔実施例〕〔Example〕

以下、本発明の一実施例を第1図により説明する。 An embodiment of the present invention will be described below with reference to FIG.

第1図において、制御回路1より、ゲート制御信号がゲ
ートドライブ回路に与えられ、ゲートドライブ回路2で
素子7に対応するゲートパルスを発生しこれを素子のゲ
ートに与える事により、素子のオン、オフ制御を行ない
素子の負荷へ与える電力を制御する構成となっている。
In FIG. 1, a gate control signal is applied from the control circuit 1 to the gate drive circuit, and the gate drive circuit 2 generates a gate pulse corresponding to the element 7 and applies it to the gate of the element, thereby turning on the element. The configuration is such that off control is performed to control the power applied to the load of the element.

ここで、素子のゲート信号を比較器5に取り込む、比較
器にはゲート信号と比較基準電圧4が与えられており、
この基準電圧は素子の最小点弧電圧に設定されている。
Here, the gate signal of the element is taken into the comparator 5, and the comparator is provided with the gate signal and the comparison reference voltage 4.
This reference voltage is set to the minimum firing voltage of the element.

従って、この比較器はゲート信号が素子の最小点弧電圧
以上であるか否かをチエツクすることになる。
Therefore, this comparator will check whether the gate signal is greater than or equal to the minimum firing voltage of the element.

もし、ゲート信号が最小点弧電圧以上であれば、比較器
に接続されているゲートパルス発生部6にトリガ信号を
与える。
If the gate signal is equal to or higher than the minimum ignition voltage, a trigger signal is given to the gate pulse generator 6 connected to the comparator.

ゲートパルス発生部では、トリガ信号が与えられると、
所定時間幅、所定電圧のゲートパルスを発生し、これを
、先のゲートパルスと共に素子に印加する。
In the gate pulse generator, when a trigger signal is given,
A gate pulse of a predetermined time width and a predetermined voltage is generated and applied to the device together with the previous gate pulse.

ゲートパルス発生部には、自身の出力が、再び、入力さ
れることになるため、これにより、再び、ゲートパルス
を発生しないようにするため、ここの機能は、単安定マ
ルチ(ワンショット)の機能を備えている。
The output of the gate pulse generator will be input again, so in order to prevent the gate pulse from being generated again, the function here is to use a monostable multi (one shot) It has functions.

第2図は第1図の実施例の具体的回路例を示したもので
ある。
FIG. 2 shows a specific circuit example of the embodiment shown in FIG.

制御対象素子として、GTOを例に挙げている。The GTO is taken as an example of the controlled element.

GTOのゲートパルスは比較器8及び−比較器9に与え
られる。
The gate pulse of GTO is applied to comparator 8 and comparator 9.

比較器8はGTOの点弧用パルスのチエノーり用であり
、比較器のもう一方の入力には、GTOの最小点弧電圧
に相当する基準電圧が与えられている。
The comparator 8 is used to chienor the ignition pulse of the GTO, and the other input of the comparator is given a reference voltage corresponding to the minimum ignition voltage of the GTO.

いま、GTOにゲートパルスが与えられると、比較器8
により、このゲートパルス電圧を比較し、その電圧がG
TOの最小点弧電圧より、大きければ比較器の出力が反
転する。
Now, when a gate pulse is given to GTO, comparator 8
This gate pulse voltage is compared and the voltage is G.
If it is greater than the minimum firing voltage of TO, the output of the comparator is inverted.

比較器の出力には、ワンショットマルチバイブレータ1
0が接続されており、比較器の出力によリ、所定時間幅
のパルスを発生する。
One-shot multivibrator 1 is connected to the output of the comparator.
0 is connected, and a pulse of a predetermined time width is generated based on the output of the comparator.

このパルス幅は、GTOの点弧に必要な最小の時間に設
定されている。
This pulse width is set to the minimum time required for ignition of the GTO.

このパルスを次段のドライブ回路でGTOの点弧に必要
な電圧まで、増幅し、これをGTOのゲートに与えるこ
とにより、GTOをオンさせる。
This pulse is amplified by the next-stage drive circuit to a voltage necessary for igniting the GTO, and this is applied to the gate of the GTO to turn on the GTO.

この回路で発生される、ゲートパルスはGTOのオンに
必要な最小時間のパルス幅であるので、これにより長い
時間幅のゲートパルスがゲートドライブより与えられた
ときには、正規のゲートパルスが埋もれることになり、
通常の制御には何等影響を与えない。
The gate pulse generated by this circuit has a pulse width of the minimum time required to turn on the GTO, so when a gate pulse with a long time width is given from the gate drive, the regular gate pulse will be buried. Become,
It has no effect on normal control.

GTOのゲートドライブに要求される性能は、一般に、
ゲートパルスの立上り時に定常状態よりも大きな電圧(
電流)が要求されるため、ドライブ回路のトランジスタ
14のコレクタ側にコンデンサを設け、ここにGTOが
非点弧時に電源より充電を行なっておき、点弧時に、こ
の電荷を放電することにより、その目的を達成するよう
にして、電源部の容量を低減している。
The performance required for GTO gate drive is generally as follows:
A voltage larger than the steady state at the rise of the gate pulse (
Since a capacitor is required on the collector side of the transistor 14 of the drive circuit, this capacitor is charged from the power supply when the GTO is not ignited, and this charge is discharged when the GTO is ignited. The capacity of the power supply section is reduced to achieve the objective.

トランジスタのコレクダ側に接続されている、抵抗器1
6はそのための、コンデンサへの充電電流抑制用である
Resistor 1 connected to the collector side of the transistor
6 is for suppressing the charging current to the capacitor.

GTOの消弧時にも、全く同様にして消弧パルスを発生
する必要がある。
When arc-extinguishing the GTO, it is necessary to generate an arc-extinguishing pulse in exactly the same way.

このための回路が比較器9.ワンショットマルチバイブ
レータ11.トランジスタ13.コンデンサ15等であ
る。
The circuit for this purpose is comparator 9. One-shot multivibrator 11. Transistor 13. This is a capacitor 15 or the like.

動作は点弧時と同様であるが、消弧パルスは電圧の極性
が点弧時と逆極性になるため、比較用基準電圧の極性を
点弧用とは効にしである点が異なる。
The operation is similar to that during ignition, but the polarity of the extinguishing pulse voltage is opposite to that during ignition, so the difference is that the polarity of the reference voltage for comparison is set to be effective from that for ignition.

第3図に、本実施例の動作を示すタイムチャートを示す
FIG. 3 shows a time chart showing the operation of this embodiment.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、不完全ゲートパルスを無くすことがで
きるので、これによる素子の破壊を防ぐ効果が得られる
According to the present invention, since incomplete gate pulses can be eliminated, it is possible to obtain the effect of preventing element destruction due to incomplete gate pulses.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例のブロック図、第2図は第1
図の回路図、第3図は第2図の動作概要を示すタイムチ
ャートである。 1・・・制御回路、2・・・ゲートドライブ、3・・・
フォトカプラ、4・・・基準電圧、5・・・比較器、6
・・・ゲートパルス発生部、7・・・素子、8・・・比
較器、9・・・比較器、10・・・ワンショットマルチ
バイブレータ、11・・・ワンショットマルチバイブレ
ータ、12゜13・・・+ランジスタ、14.15・・
・コンデンサ、16・・・抵抗器。 第1図
FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
The circuit diagram shown in FIG. 3 is a time chart showing an outline of the operation of FIG. 2. 1... Control circuit, 2... Gate drive, 3...
Photocoupler, 4... Reference voltage, 5... Comparator, 6
...Gate pulse generating section, 7...Element, 8...Comparator, 9...Comparator, 10...One-shot multivibrator, 11...One-shot multivibrator, 12°13. ...+Ran resistor, 14.15...
・Capacitor, 16...Resistor. Figure 1

Claims (1)

【特許請求の範囲】 1、ゲートに点弧あるいは消弧パルス信号を与えること
により、素子の負荷への電力を制御する電力用半導体に
おいて、前記素子に与えるゲート信号のパルス幅とその
電圧を監視する機能を設けたことを特徴とする電力用半
導体の保護装置。 2、請求項1において、前記監視機能により、その信号
が前記素子によって規定される素子の点弧に必要な最小
の電圧が発生したときには、そのゲートパルスを所定の
時間幅、所定の電圧に変換し前記素子に与える機能を設
けた電力用半導体の保護装置。
[Claims] 1. In a power semiconductor that controls power to a load of an element by applying an ignition or extinguishing pulse signal to the gate, the pulse width and voltage of the gate signal applied to the element are monitored. A power semiconductor protection device characterized by having a function to protect the power semiconductor. 2. In claim 1, the monitoring function converts the gate pulse into a predetermined voltage with a predetermined time width when the signal generates a minimum voltage necessary for ignition of the element defined by the element. A protection device for a power semiconductor, which is provided with a function to provide protection to the element.
JP31391290A 1990-11-21 1990-11-21 Protecting device for power semiconductor Pending JPH04190675A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31391290A JPH04190675A (en) 1990-11-21 1990-11-21 Protecting device for power semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31391290A JPH04190675A (en) 1990-11-21 1990-11-21 Protecting device for power semiconductor

Publications (1)

Publication Number Publication Date
JPH04190675A true JPH04190675A (en) 1992-07-09

Family

ID=18047019

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31391290A Pending JPH04190675A (en) 1990-11-21 1990-11-21 Protecting device for power semiconductor

Country Status (1)

Country Link
JP (1) JPH04190675A (en)

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