JPH04190447A - Computer system - Google Patents

Abstract

PURPOSE:To enhance the processing speed by performing waiting operation for arbitor arbitrating and address translating operation in parallel. CONSTITUTION:A CPU 1 sends a logical address while sending a bus use request signal to an arbitor 3. An address translated by an address translating mechanism 5-1 is sent to a buffer 12 through a translated address signal line 16. The waiting operation for arbitor arbitration and the operation for address translation are performed in parallel. The arbitor arbitration wait time is unstable under the influence of the operation states of other CPUs, etc., but frequently longer than the time required for the address translation. The translation, therefore, ends until a bus use permission signal is supplied from the arbitor 3 to buffers 12 and 13. Consequently, a main memory 7 can be accessed immediately when the bus use permission is given. Only the time required to enabling access based upon a physical address is required and the processing is speeded up.

Description

[Detailed description of the invention] [Industrial application field]

The present invention provides a plurality of logical address generators (e.g. CPU
It relates to a computer device equipped with a central processing unit (such as a central processing unit).

[Conventional technology]

Some computer devices (eg, multiprocessor systems) include a plurality of logical address generating devices such as CPUs. These multiple logical address generators are connected to a single logical address bus and are translated into physical addresses to access the main memory and I10 devices. FIG. 4 shows a block diagram of such a conventional computer device. In the 4th session, 1°2 is the CPU, 3
is an arbiter, 4 is a logical address bus, 5 is an address translation unit (MMU), 6 is a physical address bus, 7 is a main memory, and 8 is an I10 device. In this figure, in order to avoid complexity, only two CPUs are shown as logical address generators, but there may be more than two CPUs. If the CPUs 1.2 issue address signals at the same time, the signals will collide on the logical address bus 4, making them meaningless. In order to prevent this, arbiter 3 performs arbitration,
Ensure that only a single CPU issues an address signal at the same time.0 For example, when the CPUI wants to issue an address signal, it issues a request to the arbiter 3 to use the logical address bus 4 and obtains permission to use it. and then issues an address signal. The logical address output from the CPUI is transmitted to the address translation mechanism 5 via the logical address bus 4. The address translation mechanism 5 translates logical addresses into physical addresses. The physical address obtained by the real translation is sent to the main memory I77 or I10 device 8 via the physical address bus 6, and is used to access the corresponding address. As mentioned above, since address signals are issued only from a single CPU at the same time, only one address translation mechanism for translating address signals is provided in the computer system. In addition, conventional literature related to such technology is as follows:
For example, JP-A-48-97455, JP-A-51-
141543, JP-A-60-114953, etc.

[Problem to be solved by the invention]

(Problem) However, in the conventional computer device described above,
The actual translation of the address signal output from the logical address generator C (e.g., CPU), which consists of C, can only be done after obtaining permission to use the logical address bus 4, which is an obstacle to increasing the processing speed. There was a problem. (Explanation of the problem) FIG. 5 is a diagram showing the relationship between arbiter arbitration waiting time and address real translation time, where (a) and (b) are the relationships in the present invention, and (c) and (d) are The relationship in the conventional example is shown. The horizontal axis represents time. Time Ll,l is the time when the CPU issues a bus use request to the arbiter 3, and time tlG is the time when permission to use the bus is granted. As shown in FIG. 5(C), conventionally, the device waits until permission to use the bus is granted (T1), and when it is granted, the logical address is sent to the address translation mechanism 5 and the translation is started. If the real translation requires time T2, the real translation ends at time LA, which is T2 after time tlG. Now, it is finally possible to access the main memory 7, etc., but it will take T, 10T. In this way, in the past, real translation could not be started until after the logical address bus 4 was secured, so the time required for both was unavoidably required, which became an obstacle to increasing the processing speed. Ta. An object of the present invention is to solve the above-mentioned problems. (Means for Solving the Problems 1) In order to solve the above problems, the computer device of the present invention includes a logical address generation device and an address translation mechanism dedicated to the logical address generation device, and is connected to a physical address bus. The bus mask unit is provided with a plurality of bus mask units, each having a physical address bus, and an arbiter that arbitrates the use of the physical address bus, and requests to use the bus to the arbiter and real translation of logical addresses are made in parallel.

[For production] A dedicated address translation mechanism is provided for each logical address generating device such as a CPU, and the translation is started at the same time as a bus use request signal is issued to the arbiter. In other words, the process can normally be completed before the bus permission signal is given, so access to the main memory etc. can be made immediately after the bus permission signal is given. Therefore, it is possible to make the processing speed of the combinator device faster than before. 【Example】

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows a block configuration of a computer device according to the present invention. The numbers correspond to those in FIG. 4, 4-1, 4-2 are dedicated logical address buses, 5-1.5-2 are address translation mechanisms, and 9 and 1o are bus master units (BMUs). Bus master unit 9 (10) is CP[JJ(2)
and an address translation mechanism 5-1 (5-2), and a dedicated logical address bus 4-1 (4-2) is connected between the two.
are tied together. Note that in this diagram, the bus master unit
Although only two 7-tos are drawn, it is not limited to two, and there may be more. The bus master units 9.10 are connected to a common physical address bus 6. There is no common logical address bus. Therefore, the bus use request signal issued by the bus master unit 9.10 to the arbiter 3 is the physical address bus 6.
This is a request for the use of The operation of a bus use request and the operation of address translation in the present invention will be explained with reference to FIGS. 2, 3, and 5. FIG. 2 shows the detailed structure of one bus master unit 9, and FIG. 3 shows the structure of logical addresses. In these figures, the symbols correspond to those in Figure 1, 11 is a logical address, 11-1 is an indirect address section, 11-2 is a direct address section, 12.13 is a buffer, and I4 is a bus use request signal line. , 15 is a bus use permission signal line, and 16 is a real address signal line. As shown in FIG. 3, the logic 71 pulse 11 output from the CPUI is an indirect address section 11-1 that requires translation.
and an unnecessary direct address section 11-2. Therefore, logical address 11 is C'P U 1
As shown in FIG. 2, the indirect address section 11-1 is sent to the address translation mechanism 5-1 through a dedicated logical address bus, and the direct address section 11-2 is sent without passing through it. is sent to buffer 13. In the present invention, the logical address 11 from the CPUI is
It is issued at the same time as U1 issues a bus use request signal to arbiter 3. Address translation mechanism 5-1 is CP
Since it is exclusive to U1, the real translation starts immediately. The real translated address is the real translated address signal line 16.
The data is then sent to the buffer 12. (a) and (b) in FIG. 5 show the relationship between arbiter arbitration waiting time and address real translation time in the present invention.
At the time when the bus use request was issued, the real translation of the address started at □. That is, the operation of arbiter arbitration and the operation of address translation are performed in parallel. The arbiter arbitration waiting time T is undefined because it is influenced by the operating status of other CPUs, but it is usually longer than the time T2 required for the address translation. Therefore, by the time the arbiter 3 gives the bus permission signal to the buffers 12 and 13, the translation has been completed. Therefore, once permission to use the bus is granted,
Access to the main memory 7 etc. becomes possible immediately. in the end,
The time required to access the physical address is T.
This is shorter than the conventional T and +T2, and the processing is faster. Note that the buffers 12 and 13 are connected to the physical address bus 6 only while the bus use permission signal is given.
If that signal disappears, the connection will be cut off. CPU1.2 and address translation mechanism 5-1゜5-2
may have different architectures and performances. In addition, although CP tJ is taken as an example of a logical address generator in the upper part, the DMA mechanism (Dir
ect Memory Access) or the like.

【Effect of the invention】

As described above, the computer device of the present invention performs the operation of waiting for arbiter arbitration and the operation of translating the address in parallel, so that when the bus use permission signal is given, the main memory etc. It is possible to immediately access the data using a physical address, and the processing speed can be increased.

[Brief explanation of drawings]

Fig. 1: A block diagram of a computer system according to the present invention. Fig. 2: A diagram showing the structure of one bus master unit. Fig. 3: A diagram showing the structure of a logical address. Fig. 4: A conventional Bronch configuration diagram of computer equipment Part 5... In the diagram showing the relationship between arbiter arbitration waiting time and address translation time, 1.2 is the CPU (central processing unit),
3 is an arbiter, 4 is a logical address bus, 4-1.4-
2 is a dedicated logical address bus, 5, 5-1.5-2 is an address translation unit (MMU), 6 is a physical address bus,
7 is the main memory, 8 is the I10 device, 9 and 10 are the bus master unit (BMU), 11 is the logical address, 11-1
11-2 is an indirect address part, 11-2 is a direct address part, and 12.
13 is Hanwha, 14 is a bus use request signal line, 15 is a bus use permission signal line, and 16 is a Japanese address signal line. Patent applicant Fuji Xerox Co., Ltd. Patent attorney Tomi Honjo Logical address ■ Indirect address section Direct address section Figure 3 Figure 4

Claims (1)

[Claims] It comprises a plurality of bus master units each having a logical address generation device and an address translation mechanism dedicated to the logical address generation device and connected to a physical address bus, and an arbiter that arbitrates the use of the physical address bus. A computer device characterized in that a bus use request and a logical address translation are performed in parallel.