JPH04190426A - Memory access device - Google Patents

Abstract

PURPOSE:To prevent an interruption flag from being reset during an interruption processing period by storing an interruption detection output when an interruption accompanying address conversion from a logical address to a physical address is detected, and holding the storage state throughout the interruption processing period. CONSTITUTION:When an address conversion exception is generated, an interruption detecting circuit 21 detects the interruption and the output of the circuit 21 goes up to 'H'. At this time, data '1' is held in a period discrimination register 24, the output of an AND circuit 251 becomes '1', and an interruption flag 22 is set to '1' through an OR circuit 253. Then when an interruption processing circuit 23 starts the interruption processing, the contents of the register 24 are changed into '0', the gate of the circuit 251 is closed, and the gate of a circuit 252 is opened. When the interruption processing ends, a circuit 23 changes the data in the register 24 into '1' and the flag 22 is reset. The flag 22 is therefore prevented from being reset in the interruption processing period.

Description

[Detailed Description of the Invention] [Summary of the Invention] Regarding a memory access device that accesses a main storage device based on a virtual memory method such as a paging method or a segmentation method, changes in interrupt flags can be controlled without deteriorating interrupt processing performance. Interrupt detection means for detecting interrupts associated with address conversion from a logical address to a physical address in a memory access device that accesses main memory based on a virtual memory method. The interrupt detection output storage means stores the detection output of the interrupt detection means, and the storage state holding means holds the storage state of the interrupt detection output storage means during the interrupt processing period.

[Industrial application field]

The present invention relates to a memory access device that accesses a main storage device based on a virtual storage method such as a paging method or a segmentation method.

In a virtual memory type memory access device, a physical memory device is accessed by converting a logical address into a physical address using a dynamic address conversion mechanism.

In such a memory access device, address translation exceptions such as an associative memory fault, protection fault, and page fault may occur during address translation.

Here, associative memory fault is, as shown in Figure 4,
This is a fault that occurs when a content addressable memory (TLB) is indexed to convert a logical address into a physical address because there is no physical page address corresponding to the logical page address in the content addressable memory.

Furthermore, a protection fault is a fault that occurs when a prohibited area on the main storage device is accessed.

Furthermore, a page fault is a fault that occurs when a corresponding page does not exist on the main storage device.

This page fault occurs, for example, when a page cross as shown in FIG. 5 occurs.

That is, if an attempt is made to write, for example, 4-byte data to the main memory, a page cross will occur if this 4-byte data spans two pages. Even if this page cross occurs, there is no problem if the main storage device is accessed using physical addresses. However, when accessing using a logical address, a page fault may occur because it is not known where the next page is.

In a virtual memory type memory access device, when an address translation exception as described above occurs, an interrupt is generated, and the address translation exception is handled by interrupt processing by a microprogram or the like. in this case,
The interrupt occurrence information is stored in the interrupt flag, and is reset when the interrupt processing is completed.

Incidentally, in a virtual memory type memory access device, memory access during interrupt processing is normally performed using a physical address.

However, in this case, when accessing the memory, it is necessary for the interrupt detection circuit to determine whether to access the memory using a physical address or a logical address, which increases the interrupt detection time.

Therefore, in recent years, memory access devices have been developed that perform interrupt detection but access memory using physical addresses as addresses.

However, in the case of this memory access device, the contents of the interrupt flag change due to address conversion during interrupt processing, so it is necessary to prevent this.

[Prior Art] Conventionally, as shown in Part 6, interrupt flag data is temporarily saved before memory access is performed, and the saved data is restored to the interrupt flag when memory access is completed. , the interrupt flag is designed to prevent glue cents.

However, during the interrupt processing period, there are various memory accesses such as page table conversion. Therefore, as described above, in the i-configuration in which the contents of the interrupt flag are saved/restored every time the memory is accessed, the number of processing steps of the microprogram increases and the performance of interrupt processing deteriorates.

[Problem to be solved by the invention]

As mentioned above, in conventional virtual memory type memory access devices, the contents of the interrupt flag are saved/restored for each memory access to prevent the interrupt flag from being set. There was a problem that processing performance deteriorated.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a memory access device that can prevent interrupt flags from being reset without reducing interrupt processing performance.

[Means for Solving the Problems] FIG. 1 is a block diagram showing the basic configuration of the present invention.

In the figure, reference numeral 11 denotes an interrupt detection means for detecting an interrupt associated with address conversion from a logical address to a physical address.

Reference numeral 12 denotes an interrupt detection output storage means for storing the detection output of the interrupt detection means 11.

Reference numeral 13 denotes a storage state holding means for holding the storage state of the interrupt detection output storage means 12 during the interrupt processing period.

[Operation] In the above configuration, when an interrupt is detected by the interrupt detection means 11, this interrupt occurrence information is stored in the interrupt detection output storage means 12. The interrupt occurrence information stored in the interrupt detection output storage means I2 is held by the storage state holding means 13 during the interrupt processing period.

As a result, even if address conversion is performed by memory access during the interrupt processing period, the interrupt detection output storage means 12 will not be overwritten.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of an embodiment of a memory access device according to the present invention.

In the figure, 2I is an interrupt detection circuit that detects interrupts caused by address translation exceptions.

For example, the interrupt detection circuit 21 normally outputs a low level signal, and when an interrupt is detected, outputs a high level signal for a certain period of time.

22 is an interrupt flag that holds the detection output of the interrupt detection circuit 21.

As will be described later, this interrupt flag 22 contains 1 bit of data rl when an interrupt is detected.

is cent. On the other hand, if no interrupt is detected, 1-bit data "0" is sent.

23 sets the data r1. to the interrupt flag 22. This is an interrupt processing circuit that executes interrupt processing when is set.

This interrupt processing circuit 23 executes interrupt processing based on, for example, a microprogram.

24 is a period identification register that holds period identification data indicating whether or not the interrupt processing period is in progress.

Here, the period identification data is 1-bit data 'IJ' when indicating a normal processing period, and 1-bit data ``0'' when indicating an interrupt processing period.

Note that the data in the period identification register 24 is changed from "1" to "1" by the interrupt processing circuit 23 at the start of interrupt processing.
0”.

A gate circuit 25 maintains the storage state of the interrupt flag 22 during the interrupt processing period based on the contents of the period identification register 24.

This gate circuit 25 includes ant circuits 251 and 252, an inversion circuit 253, and an OR circuit 254.

Here, the AND circuit 251 is supplied with the detection output of the interrupt detection circuit 21 and the data stored in the period identification register 24. The antenna circuit 252 also includes an interrupt flag 22.
The data stored in the period identification register 24 and the data stored in the period identification register 24 inverted by an inversion circuit 254 are supplied. Further, the outputs of the AND circuits 251 and 252 are supplied to the OR circuit 253. The output of this OR circuit 253 is supplied to the interrupt flag 22.

In the above configuration, the operation will be explained.

During a normal processing period, data r□J is set in the interrupt flag 22. The period identification register 24 also contains data r1. There are cents.

In such a state, when an address translation exception occurs, the interrupt detection circuit 21 detects an interrupt. As a result, the output of the interrupt detection circuit 21 becomes high level. At this time, the period identification register 24 contains data [1
, is held, the output of the AND circuit 251 is "
1".

This output is supplied to the interrupt flag 22 via the OR circuit 253. As a result, data "1." indicating that an interrupt has been detected is placed in the interrupt flag 22.

By setting the data "1" in the interrupt flag 22, the interrupt processing circuit 23 starts interrupt processing. In this interrupt processing, as shown in FIG.
First, the content of the period identification register 24 changes from rl to "0".
(step SL). After this, actual interrupt processing is performed.

By changing the content of the period identification register 24 from "1" to "0", the gate of the antenna circuit 251 is closed. On the other hand, the gate of AND circuit 252 is opened.

This is because the data "OJ" stored in the period identification register 24 is inverted to "1" by the inverting circuit 254 and then supplied to the AND circuit 252.

By opening the gate of the AND circuit 252, the output of the interrupt flag 22 is transferred between the AND circuit 252 and the OR circuit 252.
3 to the interrupt flag 22. As a result, the data stored in the interrupt flag 22 is held at "1".

This state is maintained during interrupt processing.

This is because the data stored in the period identification register 24 is held at "1" during the interrupt processing period.

As a result, as shown in FIG. 3, even if there is a memory access during the interrupt processing period (steps Sf, Sm), the stored data of the interrupt flag 22 is fixed to "1".

When the actual interrupt processing is completed, the interrupt processing circuit 23 changes the stored data in the period identification register 24 from r□ to "1j" (step Sn).
The gate of AND time WI251 is opened. On the other hand, the gate of AND circuit 252 is closed.

By opening the gate of the AND circuit 251, the detection output of the interrupt detection circuit 21 is supplied to the interrupt flag 22. At this time, the output of the interrupt detection circuit 21 is already at a low level.

Therefore, the interrupt flag 22 is set to data 701. As a result, the interrupt flag 22 is reset at the end of the interrupt process.

As detailed above, in this embodiment, the period identification register 2
4 and a gate circuit 25 are provided, and the data stored in the interrupt flag 22 is held during the interrupt processing period.

As a result, according to this embodiment, during the interrupt processing period,
Since it is not necessary to save/restore the data stored in the interrupt flag 22 every time the memory is accessed, it is possible to prevent the interrupt flag from being reset without degrading interrupt processing performance.

Furthermore, since forgetting save/restore processing can be eliminated, reliability of interrupt processing can be improved.

Although one embodiment of the present invention has been described in detail above, the present invention is not limited to this embodiment, and it goes without saying that various other modifications can be made.

〔Effect of the invention〕

As described above, according to the present invention, the contents of the interrupt flag can be held without being saved/restored, so that setting of the interrupt flag can be prevented without deteriorating interrupt processing performance.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the principle configuration of this invention, FIG. 2 is a block diagram showing the configuration of an embodiment of this invention, and FIG. 3 is a block diagram showing the operation of FIG. 2. Flow chart diagram, FIG. 4 is a diagram for explaining associative memory fault, FIG. 5 is a diagram for explaining page cross, and FIG. 6 is a diagram for explaining the operation of a conventional memory access device.
This is a diagram. In the figure, 11... Interrupt detection means, 12... Interrupt detection output storage means, 13... Memory state holding means, 21... Interrupt detection circuit, 22... Interrupt flag, 23... Interrupt Processing circuit, 24... Period identification register, 25... Gate circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (5)

[Claims] (1) In a memory access device that accesses a main memory based on a virtual memory method, an interrupt detection means (11) that detects an interrupt associated with address conversion from a logical address to a physical address; an interrupt detection output storage means (12) for storing the detection output of the interrupt detection output storage means (12);
1. A memory access device comprising: storage state holding means (13) for holding a storage state of (13). (2) The storage state holding means (13) has a period identification information storage means (24) for storing period identification information indicating whether or not the interrupt processing period is in progress; The memory access device according to claim 1, wherein the memory access device is configured to maintain the storage state of the interrupt detection output storage means (12) during the interrupt processing period based on the stored period identification information. . (3) The storage state holding means (13) stores the interrupt detection output storage means (12) during the interrupt processing period.
) is stored in this interrupt detection output storage means (12).
2. The memory access device according to claim 1, wherein the memory access device is configured to maintain the storage state of the interrupt detection output storage means (12) by supplying the interrupt detection output storage means (12) as input information. (4) The storage state holding means (13) includes a period identification information storage means (24) that stores period identification information indicating whether or not an interrupt processing period is in progress, and a period identification information storage means (24) that stores an interrupt processing period. When the period identification information indicating that the processing period is in progress is stored, gate means (25) supplies the stored information of the interrupt detection output storage means (12) to the interrupt detection output storage means (12) as input information.
2. The memory access device according to claim 1, wherein the memory access device is configured to include: ). (5) When a detection output indicating that an interrupt has occurred is stored in the interrupt detection output storage means (12), the memory state holding means (13) maintains an interrupt period indicating that the interrupt processing period is in progress. Interrupt period identification information generation means (23) for generating identification information; and interruption period identification information storage means (24) for storing interrupt period identification information output from the interruption period identification information generation means (23).
When no interrupt period identification information is stored in the interrupt period identification information storage means (24), the detection output of the interrupt detection means (11) is inputted into the interrupt detection output storage means (12). and when the interrupt period identification information is stored, the gate means (2) supplies the stored information of the interrupt detection output storage means (12) to the interrupt detection output storage means (12) as input information.
5) The memory access device according to claim 1, further comprising: 5).