JPH04189047A - System and device for serial data transfer and portable terminal equipment provided with the device - Google Patents

Abstract

PURPOSE:To transfer a data through a common signal line by using an ID code to select a reception circuit. CONSTITUTION:When a, serial data signal in which an ID code is added after a data is transferred synchronously with a clock signal 2, a 2bit ID code added to a tail end of the data stays in a shift register 4 of a strobe signal control circuit 140, but the data part passes through the shift register 4 before the ID code is inputted and a resulting data signal 143 is fed to each reception circuit and any of reception circuits 134-136 is selected depending on the ID code and the result is outputted as strobe signals 145-147.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a serial data transfer method for transferring data of a plurality of different data lengths.

(Prior Art) Conventionally, as one method of transferring serial data, a method of transferring data in synchronization with a clock signal and notifying the end of the transfer operation using a strobe signal is well known.

As an example of the prior art method, Japanese Patent Application Laid-Open No. 63-197
Japanese Patent No. 151 proposes a method in which an instruction code is sent after the data and the instruction code is always placed in the first stage of a shift register in a receiving circuit in order to transfer data of different bit lengths.

(Problems to be Solved by the Invention) The above conventional technology does not take into consideration the case where serial data is transferred to multiple receiving circuits, and in this case, the transmitting side sends a separate strobe signal to each receiving circuit. There is a problem in that as many strobe signals as there are receiving circuits are required.

FIG. 13 is a connection diagram when a plurality of receiving circuits are connected using the above-mentioned conventional technology.

When attempting to transfer serial data from the transmitting circuit 100 to the receiving circuits 101, 102 and 103 using a common serial data signal and clock signal.

Three strobe signals 104, 105, and 106 are required for each receiving circuit to notify the end of the transfer operation.

In such a serial data transfer device, there is a limit to the number of signal lines between each circuit.

For example, portable radio devices, which have recently been required to be more compact, have had the disadvantage that the wiring width directly leads to an increase in the board area. Furthermore, when converting the transmitter circuit to 1C, there is a drawback that the number of IC pins increases as the number of strobe signals increases.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a serial data transfer method that can transfer serial data of different bit lengths to a plurality of receiving circuits using common signals, that is, a serial data signal, a clock signal, and a strobe signal. .

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a clock signal, a serial data signal that is serially transferred in synchronization with the clock signal, and a strobe signal that notifies the end of the transfer operation. In a serial data receiving device that receives data using a serial data receiving device, a comparison means that determines whether an ID code assigned to the receiving device that receives the data matches a receiving destination designation code added to the end of the data; The present invention includes a processing circuit that performs processing based on the information.

(Function) In the present invention, the ID code for identifying the receiving circuit is transferred successively after the serial data.

Therefore, if the bit length of the code is N bits, even if the data bit length is variable, the ID code is always stored at a predetermined position, that is, in the N bits from the first stage of the receiving shift register, at the end of the transfer by the strobe signal.

This sent ID code is compared with the ID code designated by the ID code designation means by the ID code comparison means.

This allows only receiving circuits with matching ID codes to receive and process data.

Therefore, by assigning a different ID code to each receiving circuit, serial data can be transferred using common data signals, clock signals, and strobe signals even when data is transferred to multiple receiving circuits. .

(Margin below) (Example) A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of a receiving circuit which is a receiving device in a serial data transfer device according to the present invention.

1 is a serial data signal, 2 is a clock signal, 3 is a strobe signal, 4.5 is a 2-bit shift register, 6 is an 8-bit shift register, 7 is a decoding circuit, and 8 is an ID code comparison circuit which is a comparison means. , 9 is a gate circuit,
10 is a 6-bit latch circuit, 11 is a 7-bit latch circuit, and 12 is a processing means that inputs 8-bit data and executes processing specified by the 8-bit data at the timing of strobe signal 3. A certain 8-bit processing circuit, 13 is a serial data transmitting section, 14 is a receiving circuit,
15 is an ID code setting terminal which is an ID code input means.

FIG. 2 is a timing diagram showing the structure of data to be transmitted and the timing of transmission in the embodiment shown in FIG.
The same symbols as in FIG. 1 correspond to the same parts.

Here, as shown in FIG. 2, the serial data signal 1 includes 6 to 8 bits of data, followed by a 2-bit instruction code indicating the type of data, and further indicating the receiving circuit to which the data is to be transferred. Consists of a 2-bit ID code,
It is assumed that the data is transferred serially from the left.

FIG. 3 shows a configuration example in which a plurality of receiving circuits shown in FIG. 1 are connected to one serial data transmitter.

The operation of this embodiment will be described in detail below with reference to FIGS. 1, 2, and 3.

In FIGS. 1, 2, and 3, when serial data is transferred from the transmitter 13 at the timing shown in FIG.
The serial data signal 1 output from the serial data transmitter 13 is sequentially taken into the shift registers 4, 5, and 6 at the rising edge of the clock signal 2.

At the rising edge of strobe signal 3 indicating the end of transfer,
The instruction code and ID code are always stored in shift registers 5 and 4, respectively.

The ID code comparison circuit 8 compares the ID code stored in the shift register 4 and the ID code determined by the ID code setting terminal 15, and if they match, outputs it to the Hi multiplier signal gate circuit 9, and vice versa. If so, output the LO times signal.

Therefore, only when receiving serial data having a code that matches the ID code set in the ID code setting terminal 15, the strobe signal 3 sent from the transmitting section 13 passes through the gate 9 and becomes the strobe signal 3A. The signal is sent to the decoding circuit 7.

The decode circuit 7 selects the latch circuits 10 and 11 or the processing circuit 12 that processes the data according to the instruction code of the shift register 5, and outputs the strobe signal 3B to these circuits.

The latch circuit 10 receives this strobe signal.

Holds 6-bit data input from shift register 6.

Similarly, when the latch circuit 11 receives the strobe signal 3B from the decode circuit 7, it holds the 7-bit data input from the shift register 6.

When the processing circuit 12 receives the strobe signal 3B, it processes the 8-bit data input from the shift register 6.

According to this embodiment, unless the sent ID code and the ID code set in each receiving circuit in FIG. 3 match by the ID comparison circuit 8.

Strobe signal 3 is not transmitted to decode circuit 7. That is, the receiving circuit to which the data is transferred can be specified by the ID code.

Therefore, even if data is transferred to multiple receiving circuits, only the receiving circuit whose ID code sent to the receiving circuit matches the ID code set by the ID code setting terminal 15 will receive the data. I can do it.

As described above, according to this embodiment, since the receiving circuit can be specified by the ID code, the data signal, clock signal, and strobe signal input to each receiving circuit can be made common, and the number of signal lines can be reduced. There is.

Furthermore, even if the length of the data is changed, the shift register in which the ID code is stored remains constant, so an effect can be obtained in that the length of the data can be freely changed and sent. In the above embodiment, a 2-bit ID code was considered, but an ID code other than 2-bits may be set. The same applies to data and instruction codes. It goes without saying that if the bit length of the ID code is increased, the number of receiving circuits can be increased accordingly.

Further, here, 10.11 is a latch circuit, and 12 is a processing circuit, but these may be any number of bits as long as the number of bits is less than the limit due to the configuration of the shift register 6, and the same applies to the following embodiments.

Next, an embodiment showing the configuration of a serial data transmitting section that transfers data to a receiving circuit according to the present invention including the above-mentioned receiving circuit will be described.

FIG. 4 is a block diagram for explaining the actual *N of the transmitter.

13 is a serial data transmitter, 42 is a shift register for data, and 43 is a shift register for an ID code indicating a data transfer destination, which is connected after the shift register for data. 44 is a data generation circuit which is data generation means, 45 is an ID code generation circuit which is ID code generation means, 46 is a clock signal generation circuit, 47 is a central processing unit, 48 is a strobe signal generation circuit, and 49 is a transmission activation circuit. be.

Shift registers 42 and 43 are registers that hold serial data.

FIG. 5 is a diagram showing the structure of serial data transmitted from the serial data transmitting circuit shown in FIG. 4 to each receiving circuit.

As examples of serial data, sending data 54 for the receiving circuit whose ID code is 1 bit is sent to the receiving circuit, sending data 55 for the receiving circuit A whose ID code is 2 bits sent to the receiving circuit A, and sending data 55 for the receiving circuit A whose ID code is 2 bits, which is sent to the receiving circuit A. Send to E and F. Sending data 56 for receiving circuits E and F whose ID code is 3 bits.
Shows 5'7.

In FIG. 4, a data generation circuit 44 generates data to be transmitted according to instructions from a central processing unit 47, and transfers it to a shift register 42.

Further, the ID code generation circuit 45 generates an ID code indicating the data transfer destination and supplies it to the shift register 43.

Next, in response to instructions from the transmission activation circuit 49, the clock signal generation circuit 46 generates a clock signal matching the bit length of the data to be transferred, outputs it to the outside of the transmission circuit, and simultaneously supplies it to the shift registers 42 and 43. .

The shift registers 42 and 43 output the previously transferred data and LD code serially in the order of data and ID code in synchronization with the clock signal, and transfer them to the outside as serial data signal 1.

The bit length of the shift registers 42 and 43 varies depending on the configured system, and if the ID code is configured as shown in Figure 5 by transferring the ID code after the data, the data and ID code can be separated. Data can be transferred using a common signal line even to receiving circuits with different bit lengths.

In the first embodiment, the ID code is supplied from an ID code setting terminal outside the circuit, but it may also be supplied from an internally provided ID code specifying means.

Second and third embodiments of the present invention will be described below.

FIG. 6 is a block diagram of a receiving circuit 58 which is a second embodiment of the present invention.

The same reference numerals as in FIG. 1 correspond to the same parts, and 41 is a code setting circuit that sets the ID code in terms of circuitry.

In this embodiment, as the ID code designation means of the receiving circuit,
As shown in FIG. 6, the ID code is fixed circuit-wise by the ID code setting circuit 41.

Then, the sent ID code and the ID code set by the ID code setting circuit 41 are compared in the comparison circuit 8 in the same manner as in the first embodiment.

When both match, the strobe signal 3 is sent to the decode circuit 7.
Accordingly, in this embodiment, when data is sent to multiple receiving circuits, the ID code sent and the ID code set by the ID code setting circuit 41 match. Since only the receiving circuit that receives data can receive and receive data, there is an effect that the data signal, clock signal, and strobe signal input to each receiving circuit can be common.

Furthermore, in this embodiment, there is no need to provide an ID code setting terminal, and the number of external terminals can be reduced.

FIG. 7 is a block diagram of a receiving circuit 59 which is a third embodiment of the present invention.

The same reference numerals as in FIG. 1 correspond to the same parts, and 51 is a ROM which is a storage means in which an ID code is set in advance;
2, the ROM is a fuse ROM, an EPROM or an E
ROM is a setting change means for writing the contents when it is EFROM! A write circuit, 53 is the ROMI
This is a ROM write control signal that controls the F write circuit.

It is assumed that the ROM write control signal 53 is connected to a control circuit (not described) built in the receiving circuit.

In this third embodiment, instead of supplying the ID code by the ID code setting circuit, as shown in FIG.
It is supplied by the ROM 51 in which the D code is recorded.

In FIG. 7, the operations of each part are the same as those described in the second embodiment, except for the internal ID code setting means.

Here, if the ROM is a fuse ROM, EPROM, or EEFROM (7).

The ROM write control signal 53 is input to enter the ROM write mode, and the ROM write circuit 52 writes the ROM.
Write the value of .

Therefore, according to this embodiment, the ID code can be set after the circuit is created, and the ID code can be set in the EFROM.

The use of EEFROM has the additional effect of making it possible to change the ID code.

Moreover, if the ROM is a mask ROM, the ID
Although it becomes impossible to set the code, the ROM write circuit 52 and the ROM JF write control signal 53 become unnecessary.

Further, in this embodiment, the same effects as described in the second embodiment can of course be obtained.

Here, RA is further used as the internal ID code setting means.
M may be used, and the fourth aspect of the present invention using these will be described below.
An example will be explained.

FIG. 8 is a block diagram of a receiving circuit 6o according to a fourth embodiment.

The same symbols as in FIG. 1 correspond to the same parts, 61 is a strobe signal control circuit, 62 is a RAM for ID code setting, 6
3 is an AND gate, 64 is a strobe output signal, 65 is a reset signal, and 66 is a RAM setting signal.

FIG. 9 is an example of a connection configuration when a plurality of circuits shown in FIG. 8 are connected to one serial data transmitter, and 71
．． 72 and 73 are receiving circuits having the same configuration as in FIG. 8, and the same symbols as in FIG. 8 correspond to the same parts. FIG. 10 is a timing diagram showing the timing of data transmission, and the same symbols as in FIG. 9 correspond to the same parts.

In FIG. 8, 61 is a strobe signal control circuit, which outputs a RAM setting signal 66 synchronized with the strobe signal 3 only for the first strobe signal 3 input after the input of the reset signal 65, and for the second input strobe signal 3. In subsequent strobe signals, the RAM set signal 66 is not outputted, but the strobe signal 3 is output as is to the gate circuit 63 and the strobe output signal 64.

62 is a RAM for ID code setting, which holds the value of the shift register 4 at that time in response to the RAM setting signal 66, and thereafter supplies that value to the ID code comparison circuit 8 as the ID code of the receiving circuit.

Therefore, the data sent to the receiving circuit together with the first strobe signal after reset is set as the ID code of the receiving circuit.

When data having a structure similar to that shown in FIG. 2 is sent together with the second and subsequent strobe signals, as long as the ID code therein matches the ID code set in the receiving circuit, The ID code comparison circuit 8 outputs the H1 signal, and the strobe signal is transferred to the decoding circuit 7. The decoding circuit 7 decodes the value of the shift register 5 and outputs it to the latch circuit 10, 11 or the processing circuit. 12
is selected, the strobe signal is transferred, and the value of the shift register 6 is held or processed. The operation of this part is the same as in the previous embodiments.

If the ID codes do not match, the strobe signal is only output as the strobe output signal 64, is not transmitted to the decoding circuit 7, and is ignored without being processed.

An example in which a plurality of such circuits are connected is shown below.

As shown in FIG. 9, in a circuit in which three receiving circuits of the fourth embodiment are connected, when serial data is transferred at the timing shown in FIG. 10, the receiving circuit 71 receives the reset signal 65. After that, first the serial data transmitter 7
The ID code "01" transferred in advance is sent to the RAM of the receiving circuit by the strobe signal 3 output from 0.
to hold.

This ID code becomes the ID code specified by the receiving circuit 71. At this time, as described in the explanation of FIG. 8, the strobe output signal 3 is not output.

Next, when data containing an ID code "1o" different from the previously specified ID code is transferred to the receiving circuit 71 together with the second strobe signal 3, the data is ignored because the ID codes do not match, and the strobe signal is output as is as the strobe output signal 3'.

The strobe output signal is input to the receiving circuit 72 as the first strobe signal after reset.

Here, the data ignored by the receiving circuit 71 is sent to the receiving circuit 72.
ID included in the above data as it is also commonly input to
Code "10" is specified as the ID code of the receiving circuit 72 by the strobe signal 3'.

Similarly, the strobe signal sent after the next data signal passes through the receiving circuits 71 and 72 and receives the strobe signal 3''.
The received signal is inputted to the receiving circuit 73 as an ID code "11" of the receiving circuit.

In this way, by sequentially transferring different ID codes in the same way as in the data transfer procedure immediately after reset, ID codes can be assigned in order from the receiving circuit closest to the transmitter.

(Left below) According to this embodiment, the value of the ID code can be set immediately after reset without increasing the number of signal lines. As a result, it is not necessary to determine the ID code at the time of designing or manufacturing each receiving circuit, and it is possible to change it later, which has the effect of increasing the degree of freedom.

In the embodiments so far, unidirectional data transfer has been described, but the present invention can also be applied to bidirectional data transfer.

A fifth embodiment of the present invention that takes bidirectional data transfer into consideration will be shown below.

FIG. 11 is a block diagram showing a receiving circuit 88 and a transmitting circuit 89 according to a fifth embodiment of the present invention.

The same symbols as in FIG. 1 represent the same parts.

88 is a receiving circuit, 89 is a serial data transmitting circuit, 90
is the ID code storage device f explained in the second or third embodiment as an internal ID code setting means, 80.87 is a tri-state cover sofa, 81 is a transmission shift register, 86 is a NAND gate, and 91 is Strobe signal 59 for holding transmission information in the transmission shift register
2 is an ID code match notification signal, 93 is a data transfer direction instruction signal, 82 is a serial data signal, 83 is a clock signal, and 84 is a strobe signal.

The human output buffer 80 and the transmission shift register 81 are transmitting/receiving sections that transmit and receive data.

FIG. 12 is a timing diagram of the data transferred in FIG. 11, and also shows the direction of data transfer.

The data transfer direction is as follows from the transmitting circuit 89 to the receiving circuit 88.
The direction is called A, and the opposite direction is called B.

This embodiment will be explained below with reference to FIGS. 11 and 12.

While the strobe signal 84 is Lo, the data transfer direction instruction signal 93 becomes Hi by the NAND gate 86, and the single output buffer 80 is used for input, and the output buffer 87 is used for output, allowing transfer in the A direction. become a state.

Here, when data is transferred to the receiving circuit 88 at the timing shown in FIG. 12, the ID code and I
When the ID codes assigned by the D code storage device 90 match, the ID code match notification signal 92 becomes Hi.

At the rising edge of the strobe signal 84 input at that time, the output Q of the latch circuit 85 is held Hi, while the strobe signal is passed through the AND gate 9 and decoded! 137.

The decode circuit 7 selects the latch circuit 10, 11 or the processing circuit 12 that processes the data according to the instruction code of the shift register 5, and outputs a strobe signal to these circuits.

In response to this, the latch circuit 10 holds 6 bits of data, the latch circuit 11 holds 7 bits of data,
The processing circuit 12 processes 8-bit data.

This completes the data transfer in the A direction.

Next, since the latch circuit 85 is held at Hi in the transfer operation in the A direction, when the strobe signal is kept at Hi, the data transfer direction instruction signal 93 becomes Lo, and the single output buffer 80 is used for output and The input/output buffer 87 becomes for input and becomes ready for transfer in the B direction.

The processing circuit 12 is a transmission control processing circuit that controls data transmission, and is configured to output a strobe signal 91 when the processing circuit 12 is selected by the output of the decoding circuit 7.

The transmission shift register 81 receives the strobe signal 91
transfer information such as the state of the receiving circuit is held.

By sequentially inputting the clock signal 83, the transfer information can be sent through the single output buffer 80.87 to the serial data transmitting circuit 89 in synchronization with the clock signal.

By returning the strobe signal 84 to the Lo state, data transfer in the B direction is completed, and data transfer in the six directions becomes possible again.

According to this embodiment, by using the strobe signal as the switching signal for the human output buffer, the strobe signal,
Bidirectional data transfer is possible with one serial data signal and one clock signal.

As in the first to fourth embodiments, only the receiving circuit whose ID code in the data matches the ID code designated for the receiving circuit operates. Of course, you can also get the effect of being able to do it in common.

The main effect of the embodiments described so far is that data can be efficiently transferred using the minimum number of signal lines common to a plurality of receiving circuits. This effect can be applied, for example, to portable wireless devices, which have recently been particularly required to be miniaturized, and a sixth embodiment of the present invention will be described below.

FIG. 14 is a block diagram of a portable IIA machine (portable terminal device) according to the sixth embodiment.

25 is a VCTCX○ (voltage controlled temperature compensated crystal oscillator), the output of which is input to a receiving synthesizer 22 and a transmitting synthesizer 23.

The signal taken in from the antenna 35 is sent to the transmission/reception duplexer 20
The received signal is dropped to an intermediate frequency by a receive mixer 21 and demodulated by a demodulator 27.

The output voltage of the D/A converter 26 is controlled according to the deviation of the intermediate frequency, and the output voltage controls the output voltage of the VCTCXO2.
This is to adjust the oscillation frequency of 5. The signal dropped to the intermediate frequency is passed through the reception signal processing circuit 29 to the receiver 3.
2 is output as audio.

Furthermore, the voice input from the transmitter 34 is modulated by the modulator 28 through the transmitting signal processing circuit 30, and is then modulated by the transmitting mixer 24.
The signal is converted into a transmission frequency by the transmitter/receiver duplexer 20 and sent out from the antenna.

Here, the control circuit 31 includes a reception synthesizer 22, a transmission synthesizer 23, a D/A converter 26, a reception signal processing circuit 29, a transmission signal processing circuit 30, and a dial display section 33.
Controlled circuits such as the following are controlled by a serial interface.

When the control circuit transfers data to a plurality of controlled circuits in this manner, the number of wiring lines increases if a strobe signal is sent to each controlled circuit.

In particular, when the control circuit and the controlled path are installed on different boards, the number of connection signal lines between the boards increases.
This is disadvantageous in terms of miniaturization in portable radio devices and the like.

Therefore, if the present invention is applied, the strobe signal can be shared and the number of signal lines can be reduced, so that the effect of reducing the board area and ultimately downsizing the portable radio device can be obtained.

Note that it goes without saying that similar effects can be obtained in small portable devices other than such portable radio devices.

In the embodiments described so far, each receiving circuit is provided with a code identification function that compares the ID code included in the transmitted data with the ID code assigned to each receiving circuit.

However, some IC circuits include receiving circuits configured using conventional technology that do not have an ID code identification function.
It may also be necessary to transfer serial data to these circuits.

Therefore, a seventh embodiment will be described in which the present invention is applied to an additional circuit required when transferring data to a receiving circuit according to the prior art.

FIG. 15 shows a strobe control circuit 1 according to a seventh embodiment.
25, the same symbols as in FIG. 1 represent the same parts.

51 is R for setting the internal ID code described in the third embodiment.
OM, 125 is a strobe signal control circuit, 121 is ID
Serial data signal for transferring code and data, 122
123 is a clock signal, 123 is a first strobe signal for ID code, 124 is a second strobe signal for data, 126 is a latch circuit that is a storage means for serial data, and 127 is data held in the latch circuit. This is a selector (selection means) which determines the transfer destination of the data strobe signal 124 and outputs it as strobe signals 128 to 130.

FIG. 16 is a block diagram showing a connection example when data is sent to a plurality of receiving circuits using the strobe signal control circuit 125. The same symbols as in FIG. 15 indicate the same parts.

131 is a serial data transmitter, the data signal 121 and the clock signal 122 are commonly input to the strobe signal control circuit 125 and the receiving circuits 132 to 136;
2. 133 is a receiving circuit having an ID code identification function using the present invention as shown in the first to third embodiments; 134;
136 are receiving circuits using conventional technology and not having the ID code identification function.

FIG. 17 is a timing diagram of data when data is transferred to the receiving circuits 134 to 136 through the strobe signal control circuit 125.

In FIGS. 15 and 16, when data is transferred at the timing shown in FIG.
Serial data signals 121 sent from 1 to 1 in synchronization with a clock signal 122 are sequentially input to shift registers 4, 5, and 6.

This strobe signal control circuit 125 includes a ROM 5.
1, and the first strobe signal 123 is transferred to the decoding circuit 7 only when this ID code and the ID code stored in the shift register 4 match.

At the rise of the strobe signal, the decode circuit 7 decodes the instruction code stored in the shift register 5, and operates the latch circuit 126 with its output.

The latch circuit 126 holds the value of the data stored in the shift register 6, and the selector 127 selects the data transfer destination (any one of 134 to 136) based on the value.

Here, if the receiving circuit 134 is selected by the ID code, the next data to be sent is commonly input to each receiving circuit, but the data strobe signal 124 is transmitted to the receiving circuit 134 selected by the selector 127. Only to
It is transferred as a strobe signal 128 and is not transferred to other receiving circuits.

In this way, data transfer to the intended receiving circuit can be completed.

According to this embodiment, the strobe signal control circuit 125;
With only two strobe signals 123 and 124, it is possible to transfer data to multiple receiving circuits that do not have an ID code identification function, such as the single D code comparison circuit 8, thereby reducing the number of output signals from the transmitter. The effect that can be obtained is obtained.

Since the strobe signal control circuit has an ID code, the receiving circuit 132 has an ID code identification function.
, 133 can be used together.

Another embodiment in which data is transferred to a plurality of receiving circuits without an ID code identification function will be described below as an eighth embodiment of the present invention.

FIG. 18 is a block diagram of a strobe signal control circuit according to the eighth embodiment, in which the same symbols as in FIG. 1 indicate the same parts.

In FIG. 18, 140 is a strobe signal control circuit;
4 is a 2-bit shift register, 141 selects the data transfer destination according to the value of the shift register, and strobe signal 3 is sent to strobe signals 145, 146, . or 14
This is a selector (selection means) that appears as 7.

The data signal 1 input to the shift register 4 passes through the shift register 4 and outputs the data signal 1.1 from the last stage.
Output as 3.

FIG. 19 is a block diagram showing a connection example when data is transferred to a plurality of receiving circuits using the strobe signal control circuit 140, and the same reference numerals as in FIG. 18 indicate the same parts.

150 is a serial data transmitter, 14 is a receiving circuit having the ID code identification function described in the first embodiment, and 134
．． 135 and 136 are receiving circuits that have a shift register for data but do not have an ID code identification function.

In the circuit connected as shown in FIG. 19, if a serial data signal with an ID code added after the data is transferred in synchronization with clock signal 2, as in the first embodiment shown in FIG. 2-bit ID added to the tail
The code remains in the shift register 4 of the strobe signal control circuit 140, but the data portion passes through the shift register 4 before the ID code is input, and the data signal 14
3 and is commonly sent to each receiving circuit 134, 135, and 136.

The selector 141 of the strobe signal control circuit 140 selects the receiving circuit 134, 135 or 1 according to the value of the ID code stored in the shift register 4 at the rising edge of the strobe signal 3 sent after the serial data signal 1.
36, and converts the strobe signal 3 to the strobe signal 145.146.147 corresponding to the selected receiving circuit.
Output as .

As a result, the target receiving circuit 13 can be
Data can be transferred from 4 to 136.

FIG. 20 shows receiving circuits 134 to 13 according to the prior art.
6 and the internal state of the shift register 4 of the strobe signal control circuit 140 according to the present invention.

This shows how the ID code of the data input to the ID code control circuit is stored in the shift register 4 of the strobe signal control circuit 140.

In FIG. 20, when serial data obtained by adding 2-bit ID codes 11 and 12 to n-bit data D1 to Dn is input to the strobe signal control circuit 140 in order from Dl, the strobe signal control circuit 140 shifts. The data that has passed through register 4 is sent to receiving circuits 134 to 1.
1@ is transferred to each of the 36 shift registers.

After the transfer is completed, ID codes 1 and 2 are stored in the shift register 4 of the strobe signal control circuit 40, and data D1-Dn are stored in the shift registers of the receiving circuits 134-136.

Of course, since the receiving circuit 14 having an ID code identification function is directly connected to the data signal, clock signal, and strobe signal from the serial data transmitting section 150,
If the D codes match, the strobe signal control circuit 140
You can receive and receive data without passing it through.

According to this embodiment, by providing the strobe signal control circuit 140, it is possible to use the same data format in a conventional receiving circuit without an ID code identification function and a receiving circuit with an ID code identification function according to the present invention. data signal,
This has the advantage that data can be transferred using one common signal line for each of the clock signal and strobe signal.

In the embodiment described above, the data signal is directly taken out from the last stage of the shift register 4 of the strobe signal control circuit, and each receiving M
Although the data signal is input to the circuit, a flip-flop circuit may be added after the shift register 4 to change the timing of the data signal with respect to the clock signal.

FIG. 21 is a block diagram of a strobe signal control circuit for explaining a ninth embodiment related to this.

160 is a flip-flop circuit which is a phase adjustment means for shifting the output timing of the data signal 163 to the receiving circuit; 161 is an inverter that inverts the clock signal input to the flip-flop circuit 160; and 162 is a strobe signal control circuit.

Reference numeral 163 denotes a data signal that is the output of the flip-flop circuit, and the same reference numerals as in FIG. 18 indicate the same parts. Assume the same as the example.

FIG. 22 is a timing diagram of data in each part of the strobe signal control circuit 162, and also includes the data signal 143 that is the output of the shift register 4.

In FIG. 21, the output of the last stage of the shift register 4 (data signal 143) is shifted from the input data signal 1 by a half period of the clock signal, and changes at the same time as the clock signal rises.

On the other hand, the output data signal 163 of the flip-flop circuit 160 is outputted at a timing that changes with the falling edge of the clock signal 2, similar to the data signal 1.

As described above, according to this embodiment, the phases of data and clock can be changed by the flip-flop circuit 160, so when inputting data to the shift register of the receiving circuit, the data signal is held relative to the clock signal. This has the effect of making time leeway6.Furthermore, by adding the ID code to the end of the data, the bit length of the data can be made variable.

Also, the second. In the third embodiment, by further providing an ID code storage device inside the receiving circuit, the number of external input terminals of the receiving circuit can be reduced.

In the fourth embodiment, the degree of freedom can be increased by using a RAM as the ID code storage device.

In the fifth embodiment, bidirectional data transfer is also possible.

In the sixth embodiment, when the present invention is applied to a portable radio device, it is possible to reduce the board area and make the device smaller.

Furthermore, similar effects can be obtained in small portable devices other than such portable radio devices.

In the seventh and eighth embodiments, by providing a strobe signal control circuit, even if the receiving circuit does not have an ID code identification function, a common signal line can be used between the strobe signal control circuit and the serial data transmitting section. Data can be transferred with .

In the above embodiment, the ID code is added to the end of the serial data.

The present invention is not limited to this position, but the effects of the present invention can be obtained at any position as long as the subsequent positions are determined by the transmitting source and the receiving destination.

(Effects of the Invention) As explained above, according to the present invention, since a receiving circuit can be selected using an ID code, data can be transmitted through a common signal line without sending different strobe signals to multiple receiving circuits. It has the effect of being able to transfer.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a receiving circuit showing a first embodiment of the serial data transfer method according to the present invention, Fig. 2 is a timing diagram showing its operation, and Fig. 3 shows a configuration in which a plurality of receiving circuits of Fig. 1 are connected. Figure 4 is a block diagram of the transmitter circuit.
FIG. 5 is an explanatory diagram showing an example of the data structure output by the transmitting circuit, FIGS. 6 and 7 are examples of the second and third embodiments having an internal ID code storage means, and FIG. 8 is an internal storage. RA as a means
9 is a block diagram showing an example in which the circuit shown in FIG. 8 is connected, and FIG.
The figures are a timing diagram of input data when ID codes are sequentially set in each receiver a circuit in Fig. 9, Fig. 11 is a block diagram showing a fifth embodiment considering bidirectional data transfer, and Fig. 12 The figure is a timing diagram showing its operation, No. 13@
14 is a block diagram of a portable wireless device to which the present invention is applied, and FIG. 15 is a seventh embodiment of a portable radio device having an ID code identification function. FIG. 16 is a block diagram of a strobe signal control circuit for sending data to a plurality of receiving circuits using the strobe signal control circuit, and FIG. Figures 15 and 16 are timing diagrams for explaining the operation, and Figure 18 is an eighth embodiment, a strobe signal control circuit for sending data to multiple receiving circuits that do not have an ID code identification function. Block diagram 5 Figure 19 is a connection diagram when data is sent to a plurality of reception circuits using the strobe signal control circuit, and Figure 20 shows the internal state of the reception circuit and the shift register of the strobe signal control circuit. Explanatory Drawing 2 FIG. 21 is a block diagram of a ninth embodiment that is an improvement on the strobe signal control circuit of FIG. 18, and FIG. 22 is a timing diagram showing the operation of the strobe signal control circuit of FIG. 21. l... serial data signal, 2... clock signal, 3...
・Strobe signal, 4.5.6...Shift register, 7
...Decoding circuit, 8...ID code comparison circuit, 9
...AND gate, 10...6-bit latch circuit. 11... 7-bit latch circuit, 12... 8-bit processing circuit, 13... serial data transmitter, 14...
Receiving circuit, 15... ID code setting terminal, 20... Transmitting/receiving duplexer, 21... Receiving mixer, 22... Receiving synthesizer, 23... Transmitting synth, 24... Transmitting mixer, 2
5...VCTCXO126・=D/A, 27-
... Demodulator, 28... RI4 converter, 29... Reception signal processing circuit, 3o... Transmission signal processing circuit, 31...
Control circuit, 32...Telephone receiver, 33...Dial display section, 34--Telephone transmitter, 35...Antenna, 41...I
D code setting circuit, 51... ROM, 52. ROM writing circuit, 53... writing control signal, 61...
Strobe signal control circuit, 62...RAM, 63.A
ND gate, 64・Strobe output signal, 65・Reset signal, 66・RAM setting signal, 70・Serial data transmitter, 71 to 73・Receiver circuit, 80.87・
... Input/output buffer, 81... Transmission shift register, 82... Serial data signal, 83... Clock signal, 84... Strobe signal, 86... NAND gate, 88... Receiving circuit, 89. Serial data transmission circuit, 9o.. ID code storage device, 91.. Strobe signal for transmission shift register, 92.. ID code match notification signal, 101.102.103.. Receiving circuit, 121.. -Data signal, 122...clock signal. 123.124... Strobe signal, 125... Strobe signal control circuit, 126... Shift register. 127...Selector, 128-131...Strobe signal, 132...Serial data transmitter, 133-
136--receiving circuit, 140... strobe signal control circuit, 14-to selector, 143, 163... data signal, 145-147... strobe signal. 150... Serial data transmitter, 162... Strobe signal control circuit, 160... Latch circuit, D1 to Dn
・Data, Il, I2...ID code.

Claims (1)

[Claims] 1. In a serial data transfer method that transfers data using a clock signal, a serial data signal that is serially transferred in synchronization with the clock signal, and a strobe signal that notifies the end of the transfer operation, A serial data transfer method characterized by transmitting and receiving a data signal consisting of serial data and an ID code that specifies the data transfer destination. 2. In a serial data receiving device that receives data using a clock signal, a serial data signal that is serially transferred in synchronization with the clock signal, and a strobe signal that notifies the end of the transfer operation, the receiving device that receives the data A serial data receiving device comprising a comparison means for determining whether an assigned ID code matches a reception destination designation code added to the end of the data, and a processing circuit for performing processing based on the comparison result. . 3. In a serial data receiving device that transfers data using a clock signal, a serial data signal that is serially transferred in synchronization with the clock signal, and a strobe signal that notifies the end of the transfer operation, in synchronization with the clock signal. a register for storing received data; an ID code specifying means; a comparison means for comparing the ID code given by the ID code specifying means and a receiving destination specifying code added to the end of the serial data signal; A serial data receiving device comprising processing means for executing predetermined processing according to the data using the output of the comparison means and the strobe signal. 4. The serial data receiving device according to claim 3, wherein the code specifying means is an input means into which an ID code is input. 5. The serial data according to claim 4, wherein the ID code specifying means has a storage means for storing the ID code, and an ID code setting changing means for setting or changing the contents of the storage means. receiving device. 6. Transfer of data and subsequent data in a serial data transmitter that transfers data using a clock signal, a serial data signal that is serially transferred in synchronization with the clock signal, and a strobe signal that notifies the end of the transfer operation. A register that holds a serial data signal with an ID code added thereto for specifying a destination, a data generation means for generating the above data, and a code generation means for generating a code from the above. serial data transfer device. 7. In a serial data transfer method that transfers data using a clock signal, a serial data signal that is serially transferred in synchronization with the clock signal, and a strobe signal that notifies the end of the transfer operation, the strobe signal has one signal level. A serial data transfer method characterized by transmitting data at a certain signal level, receiving data at another signal level, and notifying the end of a data sending/receiving operation at a change point of the strobe signal. 8. In a serial data transmitting/receiving device that transfers data using a clock signal, a serial data signal that is serially transferred in synchronization with the clock signal, and a strobe signal that notifies the end of the transfer operation, a register for storing data received by the serial data signal, an ID code designation means, and a comparison means for comparing the ID code given by the code designation means with the reception destination designation code added to the end of the serial data signal. Serial data, characterized by comprising processing means for executing predetermined processing according to the data using the output of the comparison means and the strobe signal, and a transmitting/receiving section for transmitting and receiving data according to the signal level of the strobe signal. transmitting and receiving equipment. 9. During serial data transfer, the first strobe signal and the second A strobe signal control circuit that determines the destination of the strobe signal that is composed of a strobe signal, the circuit comprising: a register that stores a serial data signal in synchronization with a clock signal; an ID code designation means; Comparing means for comparing a given ID code with a transfer destination designation code added to the end of the serial data signal; Storage means for storing the data in accordance with the output of the comparing means; and Contents of the storage means. and selecting means for selecting a transfer destination of the second strobe signal based on the strobe signal control circuit. 10. Determine the destination of the strobe signal during serial data transfer to transfer data using a clock signal, a serial data signal that is serially transferred in synchronization with the clock signal, and a strobe signal that notifies the end of the transfer operation. A strobe signal control circuit, characterized in that it has a register that receives serial data and outputs the data, and selection means that selects a strobe signal transfer destination according to the contents of the register and outputs the strobe signal. Strobe signal control circuit. 11. The strobe signal control circuit according to claim 10, further comprising phase adjustment means for matching the phase of the data signal that has passed through the register that stores the ID code with the input data signal. 12. A mobile terminal device comprising the receiving device according to claim 2, 3, 4 or 5 and the strobe signal control circuit according to claim 9, 10 or 11. 13. In a serial data transfer method that transfers data using a clock signal, a serial data signal that is serially transferred in synchronization with the clock signal, and a strobe signal that notifies the end of the transfer operation, the transmission serial data and the serial A serial data transfer method characterized by transmitting and receiving a data signal having an ID code added at a predetermined position after the data to specify a data transfer destination.