JPH04188773A - Thin-film transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent the peeling of a film, to improve performance and to enhance reliability by making the crystal grain size of an active layer on the substrate side smaller than that on the insulating gate side. CONSTITUTION:A thin-film transistor is composed of a light-transmitting insulating substrate 21, a poly-Si film 23, a gate oxide film 25, a source electrode 29, a gate electrode 31, a drain electrode 33 and an ohmic contact layer 35. A crystal grain boundary on the lower side of the poly-Si film 23 is made smaller than that on the upper side. Consequently, thermal stress on the joint surfaces of the insulating substrate 21 and the poly-Si film 23 having the large difference of thermal expansion coefficients is relaxed. The crystal grain boundary of the upper side, a section functioning as an active layer, of the poly-Si film 23 is made lager, thus improving mobility, etc. Accordingly, the peeling of the film, etc., are prevented, performance is enhanced and reliability is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a thin film transistor and a method for manufacturing the same;
Particularly regarding improving mobility.

(Conventional technology) Electroluminescence, light emitting diode.

Display devices such as plasma displays, fluorescent displays, and liquid crystal displays can have thinner display sections, and are increasingly in demand for use in terminal display devices for measuring instruments, office equipment, computers, etc., or special display devices. Among these, electroluminescence and liquid crystal display devices using switching element matrix arrays of thin film transistors are attracting attention as display devices because they can reduce power consumption and cost.

Materials for such switching transistors include crystalline, polycrystalline, and amorphous Sl, 5JGe, and 5i.
CSCdSeSTe, CdS, etc. are used. Among these, polycrystalline semiconductors and amorphous semiconductors can be used to form active matrix elements of switching transistors even on substrates that need to be handled at relatively low temperatures, such as glass substrates, because thin film technology for low-temperature processes can be applied. , brought a low-cost, large-area display device to the practical stage.

FIG. 4 shows a cross-sectional view of a conventional thin film transistor (TPT) using a polycrystalline silicon film for the active layer.

A polycrystalline silicon (poly-5J) film 3 serving as an active layer is formed in a predetermined pattern on a transparent insulating substrate such as a glass plate. A protective film 5 having a thickness of 5 inches is provided in a predetermined region on this polycrystalline silicon film 3. A gate electrode 7 formed by patterning a first grade electrode material is provided on the protective film 5. A source electrode 9 and a drain electrode] are formed on the upper side of the polycrystalline silicon 3 on the end face facing the gate electrode 7. In addition, the source electrode 9. An n'' poly-Si film 3 is formed as an ohmic contact layer between the drain electrode 1] and the polycrystalline silicon film 3.

In a thin film transistor configured in this manner, it is known that transistor characteristics such as mobility can be significantly improved by enlarging the crystal grain boundaries of the active layer. The size of the crystal grain boundaries in the active layer can be adjusted by changing the ion implantation conditions, annealing treatment conditions, and the like. However, if an annealing step is provided in the manufacturing process to enlarge grain boundaries, the insulating substrate 1 and the p
Due to the difference in thermal expansion coefficient with the poly-5i film 3 (active layer), thermal stress is applied to the active layer of the poly-5i film 3, resulting in problems such as film peeling. Such inconveniences are more likely to occur as the grain boundaries become larger. Therefore, when annealing is performed to improve transistor characteristics such as mobility, the crystal grain boundaries become larger, but there is a problem in that film peeling occurs and reliability decreases.

(Problems to be Solved by the Invention) As mentioned above, in order to improve the transistor characteristics, when an annealing process is provided to increase the crystal grain size of the active layer, the thermal expansion coefficient of the substrate and the active layer attached to the substrate are There was a problem in that the film peeled off due to the difference in the coefficient of thermal expansion of the layers, resulting in a decrease in reliability.

The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a highly reliable thin film transistor having good transistor characteristics.

Another object of the present invention is to provide a method for manufacturing a thin film transistor having good transistor characteristics without causing element destruction due to film peeling or the like.

[Structure of the Invention] (Means for Solving the Problem) In order to achieve the above object, the thin film transistor of the present invention includes a substrate, an active layer formed with a predetermined pattern on the substrate, and a thin film transistor formed on the active layer. In a thin film transistor having source and train electrodes in contact with each other via an ohmic contact layer, and a gate electrode disposed above or below the active layer via a gate insulating film, the grain size of the active layer on the substrate side is It is characterized by a smaller comb than that on the membrane side.

Another thin film transistor of the present invention includes a substrate, an active layer formed with a predetermined pattern on the substrate, source and drain electrodes that are in contact with the active layer via an ohmic contact layer, and an upper part of the active layer or A thin film transistor having a gate electrode disposed below with a gate insulating film interposed therebetween, the thin film transistor comprising the steps of implanting inert atoms into the active layer, and annealing the active layer into which the inert atoms have been implanted. It is characterized by

Further, the method for manufacturing a thin film transistor of the present invention includes a substrate,
An active layer formed with a predetermined pattern on this substrate, source and drain electrodes that are in contact with this active layer via an ohmic contact layer, and a gate that is disposed above or below the active layer via a gate insulating film. The thin film transistor of the present invention is characterized in that the thin film transistor has a step of implanting inert atoms into the active layer, and a step of annealing the active layer into which the inert atoms have been implanted. According to the patent, by increasing the crystal grain size of the active layer on the gate insulating film side, characteristics such as mobility are improved, and because the crystal grain size of the active layer on the substrate side is made smaller, film peeling becomes less likely to occur. As a result, a thin film transistor with high performance and high reliability can be obtained.

Further, according to the method for manufacturing a thin film transistor of the present invention,
By implanting inert atoms into the active layer, problems such as ionization of the implanted atoms in the active layer do not occur. As a result, the grain size of the active layer on the gate insulating film side can be made large and the grain size of the active layer on the substrate side can be made small without causing deterioration of the characteristics of the active layer, so that a thin film transistor with high performance and high reliability can be manufactured.

(Example) Embodiments will be described below with reference to the drawings.

FIG. 1 shows a sectional view of the manufacturing process of a thin film transistor according to an embodiment of the present invention.

To explain this according to the manufacturing process, first, as shown in FIG. P is thermally decomposed to a thickness of approximately 250 nm.
Deposit an oly-5i film 23. Next, argon atoms are implanted into this polycrystalline silicon film 23 at a dose of 2×10 16 cm −2 at an acceleration voltage of 100 KeV. After this, annealing treatment is performed at 600° C. for 40 hours.

Next, as shown in the same figure (b), poly
A gate oxide film 25 is formed by thermally oxidizing the surface of the -5i film 23 and etching it into a predetermined pattern.

Next, as shown in FIG.
iH27 is formed using a thermal CVD method. Next this n″
A phosphorus atom is implanted into poly-5i27, and after this, 7
Annealing treatment is performed at 00° C. for 10 hours.

Finally, as shown in the same figure (d), Mo, A, and P are sequentially deposited on the n''a-8i film 27 by sputtering method, and these electrode materials and the n''poly 5i 27 are patterned. Source electrode 29. Kate electrode 31
．． Drain electrode 33 and ohmic contact layer 3
5 to complete the thin film transistor.

In this manufacturing method, even if thermal stress is applied to the poly-5i film 23 during an annealing process to enlarge the grain boundaries after argon atoms are implanted into the poly-8l film 23, the argon atoms Such stress is absorbed, and therefore distortion is less likely to occur, thereby preventing film peeling and the like. Furthermore, the thin film transistor manufactured in this manner has a structure in which the lower crystal grain boundary of the poly-5I film 23 is smaller than the upper crystal grain boundary because argon atoms are implanted under the above-mentioned conditions. . As a result, thermal stress is sufficiently alleviated even at the bonding surface between the insulating substrate 2 and the poly-Si film 23, which have a large difference in coefficient of thermal expansion, and film peeling can be prevented.

Since the crystal grain boundaries on the upper side of the poly-5i film 23, that is, in the part that functions as an active layer, are large, mobility and the like are improved, and a high-performance thin film transistor can be obtained. Also, since argon is an inert atom, pol
The y-5i film 23 is not ionized, and problems such as deterioration of film characteristics do not occur.

Using the above manufacturing method, the film peeling rate was determined by varying the argon concentration in the poly-5i film 23.

I looked into mobility. The argon concentration was changed by adjusting the dose of argon atoms, annealing temperature, and annealing time. FIG. 2 shows the results of measuring the relationship between the argon concentration in poly-3i@23, the film peeling rate, and the mobility. Here, the film peeling rate is the percentage of the number of chips in which film peeling occurred relative to the total number of chips. Also, I)01
'/-The argon concentration in the Si film 23 was determined by secondary ion mass spectrometry. As is clear from this figure, when the argon concentration in the film 23 is 0.01 atomic % or more, the film peeling IE hapo is small, but when it is less than that, it suddenly becomes high. This is thought to be because if the argon concentration is too low, thermal stress etc. cannot be absorbed sufficiently and distortion is likely to occur. Also, the mobility is argon concentration or 10 atom%
If the size exceeds this value, the size will suddenly become smaller, resulting in a thin film transistor that is not suitable for high-speed operation. This is considered to be because the grain boundaries on the upper side of the poly-8i film 23 do not become large unless the argon concentration exceeds a certain level.

Therefore, in FIG. 1(a), the dose amount, annealing temperature, and annealing time are each 2'XI Qlbcm-
Although the temperature was set at 2,600° C. for 40 hours, the same effect as in the above example can be obtained by changing these values as appropriate as long as the argon concentration is within the range of 0.01 atomic % or more and 10 atomic % or less. .

Next, a thin film transistor according to another embodiment of the present invention will be described.

The difference between the second thin film transistor and the one described above is that poly-5i23 was sputtered using an RF magnetron sputtering device (argon pressure: '] 0.2 x 10-3 Torr).
The reason is that the film was formed using an RF input power of 100 W), and the annealing was performed using an ArF ekin laser.

When the second thin film transistor was compared with the one annealed by heater heating or laser irradiation, it was confirmed that the thin film transistor of this example had higher mobility.

Thus, in this example, by implanting argon atoms into the poly-5i film that will serve as the active layer, a poly-5i film with large grain boundaries on the upper side and small grain boundaries on the lower side can be formed without causing deterioration of the film quality. Therefore, a highly reliable thin film transistor can be obtained.

Note that the present invention is not limited to the embodiments described above. In the above embodiment, argon atoms were implanted as inert atoms into the poly-5i film 23, or other inert atoms such as helium or neon were implanted.

Krypton, xenon, etc. may also be used. In addition, although the thermal CVD method was used to form the poly-3i film in the example,
Other CVD methods, such as plasma CVD and photo-CVD, may also be used. Furthermore, pol film formed by CVD method
Instead of annealing the y-5i film 23 by heating it with a heater,
Annealing may be performed by laser irradiation, or the poly-5i film 23 may be formed by sputtering and then annealed by heating with a heater. Furthermore, the same effect as in the previous embodiment can be obtained by using an alloy of silicon and germanium or an alloy of silicon and carbon instead of the poly-5i film 23. Although the present invention has been described with respect to a coplanar thin film transistor, it can also be applied to staggered and reverse staggered thin film transistors. In addition, various modifications can be made without departing from the gist of the present invention.

[Effects of the Invention] According to the thin film transistor of the present invention, the crystal grain size of the active layer on the substrate side is small due to the inert atoms contained in the active layer.
The crystal grain size of the active layer on the insulated gate side is increased, which improves transistor characteristics, making it possible to obtain a high performance and highly reliable thin film transistor.

In addition, since inert atoms are implanted into the active layer, it is possible to reduce the crystal grain size of the active layer on the substrate side and increase the crystal grain size of the active layer on the insulating cat side without causing deterioration of the active layer. It is possible to manufacture high-performance and highly reliable thin film transistors.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of the manufacturing process of a thin film transistor according to an embodiment of the present invention, Figure 2 is a diagram showing the relationship between argon concentration, film peeling rate, and mobility, and Figure 3 is a cross-sectional view of a conventional thin film transistor. It is. 2]...Transparent insulating substrate, 23...poly-Si film, 25...gate oxide film, 27...n″poly-
Si film, 29... source electrode, 31... gate electrode,
33...Drain electrode, 35...Ohmic contact layer. Applicant's representative Patent attorney Takehiko Suzue kJJ! 11 Figure 1

Claims (3)

[Claims] (1) A substrate, an active layer formed with a predetermined pattern on this substrate, source and drain electrodes that contact this active layer via an ohmic contact layer, and a gate insulating film on the top or bottom of the active layer. 1. A thin film transistor having a gate electrode disposed therebetween, wherein a crystal grain size of the active layer on the substrate side is smaller than that on the insulated gate side. (2) a substrate, an active layer formed with a predetermined pattern on this substrate, source and drain electrodes that contact this active layer via an ohmic contact layer, and a gate insulating film on the top or bottom of the active layer. 1. A thin film transistor having a gate electrode disposed therebetween, wherein the active layer contains inert atoms. (3) a substrate, an active layer formed with a predetermined pattern on this substrate, source and drain electrodes that contact this active layer via an ohmic contact layer, and a gate insulating film on the top or bottom of the active layer. A thin film transistor having a gate electrode disposed through the active layer, the thin film transistor comprising a step of implanting inert atoms into the active layer, and a step of annealing the active layer into which the inert atoms have been implanted. manufacturing method.