JPH04188772A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To inhibit the fluctuation of the threshold voltage of a MOS transistor, and to increase isolation voltage by previously forming uniform amorphous silicon onto a silicon semiconductor layer except a single crystal, which has the same face orientation, oxidizing amorphous silicon through a thermal oxidation method and forming a gate insulating film. CONSTITUTION:An amorphous silicon layer is shaped onto a base body 1 as an insulating film while the film thickness of the amorphous silicon layer is set previously in specified thickness enough for causing a sufficiently long oxidizing time when the oxidation of amorphous silicon reaching the subsequent interface of a silicon semiconductor is managed by a diffusion control, and amorphous silicon is oxidized through a thermal oxidation method. Consequently, amorphous silicon is deposited on a semiconductor layer 2 first and the uniform insulating film 5 can be formed on the whole surface even in the semiconductor substrate 1, in which the face orientation of a semiconductor crystal is not simply. Accordingly, the fluctuation of the threshold voltage of a MOS transistor is inhibited, and isolation voltage is increased.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to field effect transistors, particularly SOI (
The present invention relates to a method for manufacturing semiconductor devices such as field effect transistors (Silicon on Inverter).

[Prior Art] Conventionally, the gate insulating film of a field effect transistor is formed by heating a quartz tube from the outside to about 800 to 1200°C with an electric heater and introducing an oxidizing gas such as 02-82 into the tube. Thermal oxidation method, S
i H-, A I C1s, TaCl5 and other material gases and 02. N20, N2. Chemical lid @ (CVD) method for gas phase reaction with reactive gases such as NH, Si, Al, Ta
Metals such as sio*, Six N4, A12
Ar or A metal compounds such as 0x and Ta205
1.5 iOz, AlxO by sputtering with plasma such as r + 02, A r + N2, etc.
It is formed using a sputtering method or the like to deposit an insulating film such as x, Ta*Os-, or the like. In particular, the thermal oxidation method described above can form a high-quality silicon oxide film, and the insulating film has a smaller trap level density (interface state density) at the interface with the semiconductor layer than other methods. There is. In addition to these methods, there are also methods such as anodic oxidation and plasma oxidation.

However, due to the film quality of the insulating film and the interface characteristics with the semiconductor layer, the above-mentioned thermal oxidation method is used to form the gate insulating film in the silicon single crystal MOS process. A multilayer structure of insulating films using this and other manufacturing methods is often adopted.

[Problems to be Solved by the Invention] However, in the thermal oxidation method described above, the growth rate of the oxide film varies depending on the plane orientation of the crystal to be oxidized. This is due to the fact that in the thermal oxidation mechanism, the oxidation rate is determined by the reaction rate between silicon and oxygen at the initial stage of oxidation (reaction rate-determined), and the number of silicon atoms per unit area differs depending on the plane orientation of the crystal. This is because there is a difference in

Incidentally, if 1000 people were oxidized at 1000°C and oxygen partial pressure (PO,) = 1, the plane orientation of Sl with the largest difference in oxidation rate was (100) and (11,1). There is a difference in oxide film thickness of about 20%. For this reason, S
When using the normal thermal oxidation method for O-etched substrates, in SOI substrates other than single crystal where all crystals have the same plane orientation, when forming a gate insulating film, the oxidation rate differs depending on the plane orientation, so the thickness of the insulating film may be partially reduced. Differently, the threshold voltage (V th) of a MOS transistor has a non-uniform distribution within the substrate.

In the thermal oxidation method described above, the breakdown voltage distribution of the thermal oxide film is affected by defects due to crystal grain boundaries near the silicon surface existing in the silicon substrate. Further, the concentration of electric field in the step portion of the insulating film causes deterioration of the dielectric strength voltage.

On the other hand, a gate insulating film formed by a CVD method or a sputtering method has a thicker interface state density between a crystal layer and an insulating film (as well as a higher quality of the insulating film itself) than an insulating film formed by a thermal oxidation method. The leakage current, dielectric strength, fixed charge density in the insulating film, etching rate, etc. are often inferior to those formed by thermal oxidation.

However, even in the above thermal oxidation method, the oxidation reaction progresses,
When the oxidation rate is determined to such a rate that oxygen atoms thermally diffuse in the Sing region, there is no difference in the oxidation rate depending on the plane orientation in that region (diffusion-determined region). This point will be explained based on the following general formula for thermal oxidation (Deal &Grove's formula).

Xo t+ and 17! -=1+-□ -1(1) A/2 A''/4B In the above formula, z= (x+ 2+Ax+)/Bx1: Initial oxide film thickness xo: Oxide film thickness after oxidation t: Oxidation time A: 1inear rate constantB
: parabolic rate constant
In the equation of t(1), when the oxidation time is long, that is, t>
A2/4B, and when t) is (diffusion limited), equation (1) becomes as follows.

Xoj l/2 A/2 A, "/4B or xo2=Bt (2) Also, when the oxidation time is short, that is, when t<A2/4B (reaction rate limiting), equation (1) becomes as follows. Become.

Xo 1 t ””A/2
2 A2/4B or Xa = (10τ) (3) Therefore, for example, in thermal oxidation at 1000°C and 100% oxygen, the rate of reaction in equation (3) is completely controlled by the thickness of 300 people. If the gate insulating film is
When i 02 and the thickness is 300 Å or more, the subsequent thermal oxidation is completely controlled by diffusion and not by the reaction rate. In other words, if the thickness of the insulating film is sufficiently thick as described above, the progress of oxidation changes at a position beyond the thickness, and the dependence of the oxide film thickness on the surface orientation becomes less.

[Means for Solving the Problems] The present invention has been made based on the above circumstances, and is based on the above-mentioned circumstances. Crystalline silicon is formed in advance, and this amorphous silicon layer is oxidized using a thermal oxidation method.
The present invention aims to provide a method for manufacturing a semiconductor device in which a high-quality SiO2 film with a low interface state density with a crystal is formed in a substrate by forming a gate insulating film.

[Embodiments] Hereinafter, the present invention will be explained in detail with reference to illustrated embodiments. FIG. 1 shows a cross section of a MOS transistor as an example of the present invention. Here, reference numeral 1 is an insulating substrate, on which a semiconductor layer 2 is deposited. On the semiconductor layer 2 is an amorphous silicon layer 4 and a gate 5i.
O2plJ5 is deposited.

Next, a method for forming a 3 10 g film according to the present invention will be explained using a specific example.

[Example 1] (1) As shown in FIG. 2, after etching the quartz glass substrate 11 only in the element formation region to a depth of 4,000 mm, the Si, N layer 101, which is to become the nucleation surface, is etched by 500 mm. Deposits in thickness. Next, the Sin2 layer 10 which should become a non-nucleation surface
2 was deposited to a thickness of 500 cm by normal pressure CVD,
At the center of the element forming region, only a 2 μm square layer of Sin is etched.

(2) Throw this board into the CVD chamber and set it to 50 Tor.
r, 1050°C, 5iH2C12/HCI/H2:
0.53/1. 6/100 (1/min)
When treated with crystal formation, the height is about 250 mm as shown in Figure 2.
A chevron-shaped Si single crystal 12 with a diameter of 40 μm and a diameter of 40 μm is formed starting from each nucleation surface.

(3) Then, using a processing liquid containing SfO□ colloidal silica (average particle size 0.01 μm), the surface of the silicon wafer is polished at a pressure of 220 g/cm using a commonly used silicon wafer surface polishing device.
2. Polish at a temperature of 30 to 40°C. As a result,
As shown in FIG. 3, polishing of the silicon single crystal was stopped when the silicon single crystal reached the same height as the S j, 02 film outside the element forming area, and the film thickness was 4000 mm.
200 flat Si single crystal layers are obtained.

(4) Next, as shown in FIG. 4, the upper layer of the semiconductor layer 12 is coated with S I Ha = 50 (sccm
), the amorphous silicon layer 14 is deposited to a thickness of 2000 nm by depositing at 550° C. for 12 minutes.

(5) Then, as shown in FIG. 5, the amorphous silicon layer 14 is oxidized by thermally oxidizing the substrate in a quartz tube at 1000° C. for 125 minutes in an atmosphere of 0.02° C. to form a gate SiOx film of 450 people. form 15.

(6) After this, as shown in Figure 6, the poly-3
After depositing "P" (phosphorus) at an accelerating voltage of 70
A gate electrode 16 is formed by implanting 8X 10"cm-" at keV and patterning, and then implanting "P" (phosphorus) at 2X 10"cm-2 at an acceleration voltage of 95keV using the gate electrode as a mask. And then another 95
Heat treatment is performed at 0° C. for 130 minutes to form source and drain regions 13.13-.

(7) Next, as shown in FIG. 7, after depositing 6,000 PSG films as the interlayer insulating film 17 by atmospheric pressure CVD, contact holes were formed, and Al-
5i (1%) is deposited to a thickness of 1 μm, and then patterned to form the wiring 18. Finally, as a protective film 19, 6000 PSG films are deposited by atmospheric pressure CVD.

The gate insulating film of the MO3I-transistor formed by the above process has a film thickness distribution of 500 ± 20 mm within a 4-inch wafer.
It shows good uniformity with humans, and the distribution of threshold voltage is ±50 mV.
and the interface state density is 2, Ox 10”c
m-2 eV-'. Also, with regard to dielectric strength, I
Good results were shown with OMV/cm" or more.

[Example 2] (1) 800 g
After depositing human poly-3i, it is made amorphous by implanting Si ions.

(2) Next, the amorphous silicon layer is formed at a pitch of 4 μm.
After patterning to a size of m×1 μm, solid phase growth is performed by annealing at 600° C. for 1100 hours in an N2 atmosphere.

(3) Next, using selective epitaxial growth, SiH4
Si is deposited to a thickness of 2 μm using MCI gas and MCI gas as raw material gases.

(4) Thereafter, the single crystal was polished by a mirror polishing method to a depth of 3,000. As a result, a mesh-like single crystal layer having a thickness of 3000 wafers is formed at a pitch of 4 μm on the quartz glass substrate.

(5) Next, the surface of the semiconductor layer is made amorphous by ion implantation using silicon ions at 15 keV and 5×10” cm −2 into the substrate.

(6) Then, in the same way as in Example), 02
The amorphous silicon layer is oxidized by performing thermal oxidation at 1000° C. for 125 minutes in an atmosphere to form a 450-layer SiO□ film.

(7) After that, as in Example 1, a gate electrode is formed using the normal MO8 manufacturing process, and then a source/drain region is formed by ion-implanting "P" (phosphorous). 6000 PSG film as the film
Deposit and form contact holes. Then Al
-5i (1%) to form wiring, and finally, as a protective film, an SiN film of 8,000 layers is deposited by plasma CVD.

The gate insulating film of the MO3I-transistor formed through the above steps exhibits the same film thickness distribution, threshold voltage distribution, interface state density, and dielectric strength voltage as in Example.

[Example 3] (This is an example of poly-5i TFT) (1) Poly-5i was deposited on a quartz glass substrate using a low pressure CVD method.
Deposit 000 people.

(2) Next, as in Example, the upper layer of the semiconductor layer was coated with Si H4/400 (seem), 5
Deposit 450 amorphous silicon films by depositing at 50°C for 27 minutes.

(3) After that, the substrate was placed in a quartz tube under an atmosphere of 100
A 1000-layer SiO2 film is formed by thermal oxidation at 0°C for 135 minutes.

(4) Thereafter, as in Example 1, a gate electrode is formed using the usual MO8 manufacturing process, and then source/drain regions are formed by ion-implanting "P" (phosphorus). Next, a 6000mm PSG film was used as the insulating film between the eyebrows.
Deposit and form contact holes. Then Al
Wiring is formed using -3i (1%), and finally, a SiN film of 8,000 layers is deposited as a protective film by plasma CVD.

The gate insulating film of the MO5I-transistor formed through the above process has a film pressure distribution of 1000 ± 2 within a 4-inch wafer.
It shows good uniformity with 0 people and the threshold voltage distribution is ±50m.
It is within V. Also, with regard to dielectric strength, IcIM V
/ cm ” u shows good results.

[Effects of the Invention] The present invention has been described in detail above, and even in an SOI substrate in which the plane orientation of the semiconductor crystal is not uniform over the entire wafer surface, an amorphous silicon layer is first formed on the semiconductor layer. After formation, the gate insulating film is formed by thermally oxidizing the amorphous silicon, making it possible to form a uniform insulating film over the entire surface, resulting in small changes in the threshold voltage of the MOS device and excellent dielectric strength. A gate insulating film can be obtained.

[Brief explanation of drawings]

FIG. 1 is a longitudinal sectional side view of a MO3 type transistor for explaining one embodiment of the present invention, and FIGS. 2 to 7 are sectional views showing the manufacturing process thereof. 1... Insulating base 11... Quartz substrate 2.12... Semiconductor layer 3, ]3... Source, drain region 4.14... Amorphous silicon layer 5.15... Gate 5iO -Membrane 6.16...Gate electrode 7.17...Interlayer insulating film 8.18...A1 wiring 9.19...Protective film 101...5iaN4 102...SiO2 Agent Patent attorney Mt. 102 Figure 4 Figure 5 Figure 6 lpl

Claims (1)

[Scope of Claims] 1) A method for manufacturing a semiconductor device in which a gate insulating film is formed by depositing an insulating film on a substrate having a silicon semiconductor layer and then oxidizing the silicon semiconductor, wherein the insulating film is formed on the substrate. An amorphous silicon layer is formed on the substrate, and its thickness is set in advance to a predetermined thickness sufficient to provide a sufficiently long oxidation time for the subsequent oxidation of the amorphous silicon to the interface of the silicon semiconductor to be governed by diffusion control. 2) The amorphous silicon is formed using a chemical vapor deposition method or a sputtering method. 3) The method for manufacturing a semiconductor device according to claim 1, wherein the amorphous silicon is formed by implanting silicon ions into the semiconductor layer. Manufacturing method for semiconductor devices