JPH04188771A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the reduction of breakdown strength resulting from a defect by a crystal grain boundary near the silicon surface of an insulating film by forming the insulating film in specified thickness enough for causing a sufficiently long oxidizing time when the subsequent oxidation of a silicon semiconductor is managed by a diffusion control, and using a thermal oxidation method as oxidation. CONSTITUTION:A semiconductor layer 2 is deposited on the upper layer of an insulating base body 1, a gate insulating film 4 is formed onto the semiconductor layer 2, and an insulating film 5 is deposited on the gate insulating film 4. The insulating film 4 is formed in specified thickness enough for causing a sufficiently long oxidizing time when the subsequent oxidation of a silicon semiconductor is managed by a diffusion control, and a thermal oxidation method is employed as oxidation. Consequently, even when the thermal oxidation method is used, the SiO2 film 4 having small interface level density with an Si crystal can be shaped uniformly in the base body 1. Accordingly, the lowering of breakdown strength resulting from a defect by a crystal grain boundary near the silicon surface of the insulating film can be prevented.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to field effect transistors, particularly SOI (S OI)
The present invention relates to a method for manufacturing semiconductor devices such as field effect transistors.

[Prior Art] Conventionally, the gate insulating film of a field effect transistor is formed by heating a quartz tube from the outside to about 800 to 1200°C with an electric heater and introducing an oxidizing gas such as 0□+H2 into the tube. Thermal oxidation method, S
iH,, material gas such as AlCl-1T a CI R and 02. A chemical vapor deposition (CVD) method in which a reaction gas such as N*O1N, NH, etc. is reacted in a gas phase, a metal such as Si, AI, Ta, or a metal such as SiO2, Si, N4. AI=O=,
Metal compounds such as TazO+t are heated with Ar or Ar
Sputtering with plasma such as +Ot, Ar + N2, 5ift, A120! , Tag
It is formed using a sputtering method to deposit an insulating film such as ○. In particular, the thermal oxidation method described above can form a high-quality silicon oxide film, and the insulating film has a smaller trap level density (interface state density) at the interface with the semiconductor layer than other methods. There is. In addition to these methods, there are also methods such as anodic oxidation and plasma oxidation. - However, due to the film quality of the insulating film or the interface characteristics with the semiconductor layer, the above-mentioned thermal oxidation method is used to form the gate insulating film in the silicon single crystal MOS process, and a single layer of 5iO- film is formed using this method. In many cases, a multilayer structure of insulating films using this and other manufacturing methods is adopted.

[Problems to be Solved by the Invention] However, in the thermal oxidation method described above, the growth rate of the oxide film varies depending on the plane orientation of the crystal to be oxidized. This is because in the thermal oxidation mechanism, the oxidation rate is limited by the reaction rate between silicon and oxygen at the initial stage of oxidation (reaction rate limiting).
This is because the number of silicon atoms per unit area differs depending on the plane orientation of the crystal, resulting in a difference in oxidation rate.

Incidentally, if 1000 people were oxidized at 1000°C and 1 oxygen partial pressure (PO2) = 1, the difference in oxidation rate would be greatest for the Si plane orientations <100> and (1,11). There is a difference in oxide film thickness of about 20%. For this reason,
In the normal thermal oxidation method for SOI substrates, except for single crystals in which all crystals have the same plane orientation,
When a gate insulating film is formed, the oxidation rate differs depending on the plane orientation, so the thickness of the insulating film differs locally, and the threshold voltage (v th) of the MOS transistor has a non-uniform distribution within the substrate. In the thermal oxidation method described above, the breakdown voltage distribution of the thermal oxide film is affected by defects due to crystal grain boundaries near the silicon surface existing in the silicon substrate. Further, the concentration of electric field in the step portion of the insulating film causes deterioration of the dielectric strength voltage.

However, even in the above thermal oxidation method, the oxidation reaction progresses,
When the oxidation rate is determined by the rate at which oxygen atoms thermally diffuse through the 5102 antinode, there is no difference in the oxidation rate depending on the plane orientation in that region (diffusion-determined region). This point will be explained based on the following general formula for thermal oxidation (Deal &Grove's formula).

Xo j+τ l/2 □= 1 + −1 (1) A/ 2 A2/ 4B In the above formula, T= (Xl 2+Ax+ )/BX1; Initial oxide film thickness xo: Oxide film thickness after M conversion t: Oxidation time A: 1inear rate constantB
: parabolic rate constant
In the equation of t(1), when the oxidation time is long, that is, t>
A''/4B, and when t) is (diffusion limited), equation (1) becomes as follows.

Xo t 1/2 A/2 A”/4B or xo”=Bt (2) Also, when the oxidation time is short, that is, when t<:A”/4・B (reaction rate limiting), equation (1) becomes as follows.

Xo 1 t”” A/2 2 A”/4B or xo = (plus) (3) Therefore, for example, in thermal oxidation at 1000°C and 100% oxygen, the rate of reaction in equation (3) is completely determined. It is the thickness range of 300 that is controlled, and if the gate insulating film is
i02, if its thickness is 300 Å or more,
The subsequent thermal oxidation is completely controlled by diffusion and not by the reaction rate. In other words, if the thickness of the insulating film is sufficiently thick as described above, the state of progress of oxidation changes at a position exceeding the thickness, and the dependence of the oxide film thickness on the surface orientation becomes small.

[Object of the Invention] The present invention has been made based on the above-mentioned circumstances, and it aims to improve the conditions for forming a thermal oxide film by thermal oxidation in the next step when depositing an insulating film in advance on a substrate having a silicon semiconductor layer. It is an object of the present invention to provide a method for manufacturing a semiconductor device in which a SiO2 film having a low density of interface states with the Si crystal can be uniformly formed within the substrate.

[Means for Solving the Problems] Therefore, in the present invention, in a method for manufacturing a semiconductor device in which a gate insulating film is formed by depositing an insulating film on a substrate having a silicon semiconductor layer and then oxidizing the silicon semiconductor, The insulating film is formed to a predetermined thickness sufficient to provide a sufficiently long oxidation time for subsequent oxidation of the silicon semiconductor to be controlled by diffusion rate, and a thermal oxidation method is used for the oxidation.

In this case, the insulating film is preferably formed using a chemical vapor deposition method or a sputtering method.

[Function] Therefore, even if a thermal oxidation method is used, an SiO□ film with a low density of interface states with the Si crystal can be uniformly formed within the substrate, and as described above, an insulating film using a CVD method or the like can be formed uniformly. By performing the formation in advance, it is possible to avoid deterioration in breakdown voltage caused by defects due to crystal grain boundaries near the silicon surface of the insulating film caused by thermal oxidation.

[Example] Hereinafter, the present invention will be specifically explained based on the illustrated example. FIG. 1 shows a cross section of an MO3 type transistor as an example of the present invention. Here, reference numeral 1 is an insulating substrate, on which a semiconductor layer 2 is deposited. On the semiconductor layer 2, a 5ift film 4 is deposited as a gate insulating film by a thermal oxidation method, and an insulating film 5 is deposited by a CVD method.

As deposited films by CVD method, SiO□, Sis N4
, A120s, Ta205, etc. are used,
As a method for forming it, methods such as normal pressure CVD, low pressure CVD, plasma CVD, and photoCVD are used.

Next, a method for forming a SiO□ film according to the present invention will be explained using a specific example.

[Example 1] (1) As shown in FIG. 1, after etching the quartz substrate 11 only in the element formation region to a depth of 4000 mm, the layer 101, which should be the nucleation surface, was etched to a thickness of 500 mm. accumulate. Next, the Sis2 layer 102, which should be a non-nucleation surface, is
After depositing the SiOz layer to a thickness of 0.00 mm by atmospheric pressure CVD, only the SiOz layer is etched in a 2 μm square in the center of the element formation region.

(2) Install this board in the CVD equipment and heat it to 150 Tor.
r, 1050°C, 5iHa C12/HCI/H.

: 0.53/1. 6/ 100 (1/min
), the height is about 2 as shown in Figure 2.
A chevron-shaped Si single crystal 12 of 50 μm and 40 μm in diameter is formed starting from each nucleation surface.

(3) After that, using a processing liquid containing colloidal silica of SiO□ (average particle size 0.01 μm), the surface of the silicon wafer was polished at a pressure of 220 g /
Cm'' and a temperature in the range of 30 to 40°C.As a result, as shown in Figure 3, the silicon single crystal was polished to the same height as the Si0g film outside the element formation area. By the way, the polishing was stopped and the film thickness was 4000 ± 2.
A flat Si single crystal layer of 0.00 mm is obtained.

(4) Next, as shown in FIG. 4, 5iH-CI□/N, O
= 70/400 (scc+n), SiO□ film 15 was deposited by CVD method at 850°C for 40 minutes.
Deposit to a thickness of 400 people.

(5) Then, as shown in FIG. 5, the substrate is thermally oxidized in a quartz tube at 1000°C for 15 minutes in a 02 atmosphere to form a 100% A film 14 is formed using human SiO.

(6) After this, as shown in Figure 6, the poly-3
After depositing slP゛ (phosphorus) at an accelerating voltage of 70
Form the gate electrode 16 by implanting and patterning 8X 10111cm m-'' at keV, then
Using the gate electrode as a mask, "P" (phosphorus) is implanted at an acceleration voltage of 95 keV to a depth of 2.times.10 "cm", and further heat treatment is performed at 950 DEG C. for 230 minutes to form source and drain regions 13.13.

(7) Next, as shown in FIG. 7, after depositing 6,000 PSG films as the interlayer insulating film 17 by atmospheric pressure CVD, contact holes were formed, and Al-
The wiring 18 is formed by depositing 5i (1%) to a thickness of .mu.m and then patterning. Finally, as a protective film 19, 6000 PSG films are deposited by atmospheric pressure CVD.

The gate insulating film of the MOS transistor formed by the above process showed good uniformity in film thickness distribution within a 4-inch wafer of 500 ± 20 mm, and the threshold voltage distribution was 150 mV.
and the interface state density is 105×10”cm−
It was 2 eV. Also, the dielectric strength is 1.0MV.
/cm2 or more, which showed good results.

[Example 2] (1) 800 ps on a quartz substrate by low pressure CVD method
After depositing oly-Si, Si is ion-implanted to make it amorphous.

(2) Next, the amorphous silicon layer is formed with a pitch of 4% m and a pitch of 1 μm.
After patterning to a size of m×1 μm, solid phase growth is performed by annealing at 6008 C for 100 hours in an N2 atmosphere.

(3) Next, using selective epitaxial growth, Si
Deposit μm.

(4) Thereafter, the single crystal was polished by a mirror polishing method to a depth of 3,000. This allows 4 μm to be placed on the quartz substrate.
A mesh-like single crystal layer with a thickness of 3000 m pitches is formed.

(5) Next, RF (radio frequency) sputtering was performed on the semiconductor layer with 5iOi as a target, A r + 02 (10%) as a sputtering gas, a sputtering pressure of 0.67 Pa, and an RF power of 250 W.
Deposit 400 i02.

(6) Then, as in Example 1, 02
By performing thermal oxidation at 1000°C for 115 minutes in an atmosphere, 100 SiO
2 films are formed.

(7) Thereafter, as in Example 1, a gate electrode is formed using the usual MO8 manufacturing process, and then source/drain regions are formed by ion-implanting "P" (phosphorus). Next, a PSG film with a thickness of 5,000 mm was added as an interlayer insulating film.
Deposit and form contact holes. Then Al
Wiring is formed using -5i (1%), and finally a SiN film of 8,000 layers is deposited as a protective film by plasma CVD.

The gate insulating film of the MOS transistor formed through the above steps exhibits the same film pressure distribution, threshold voltage distribution, interface state density, and dielectric strength voltage as in Example 1.

[Example 3] (1) pOl and Y were deposited on a quartz substrate using low pressure CV and D method.
- Deposit 3D00 Si.

(2) Next, as in Example 1, the upper layer of the semiconductor layer was coated with 5iH2C1□/H20=70/400 using a CVD device.
(sc cm), deposited at 850°C for 40 minutes to deposit 400 5in2 films using the CVD method.

(3) After that, the substrate was placed in a quartz tube under an atmosphere of 100
By performing thermal oxidation at 0°C for 115 minutes, poly-S
5 of 100 between 5iO- films of CVD method on i semi-semiconductor
Form an iO- film.

(4) Thereafter, as in Example 1, a gate electrode is formed using the usual MO8 manufacturing process, and then source/drain regions are formed by ion-implanting "P" (phosphorus). Next, a PSG film with a thickness of 6000 mm was used as an interlayer insulating film.
Deposit and form contact holes. Then Al
Wiring is formed using -5i (1%), and finally a SiN film of 8,000 layers is deposited as a protective film by plasma CVD.

The gate insulating film of the MOS transistor formed by the above process has a film thickness distribution of 500 ± 20 within a 4-inch wafer.
Shows good uniformity with humans, and threshold voltage distribution is also 150m
It is within V. Also, with regard to dielectric strength, IOM V
/cm'' or more, indicating a good result.

[Effects of the Invention] The present invention has been described in detail above, and even in the case of an SOI substrate in which the plane orientation of the semiconductor crystal is not uniform over the entire wafer surface, it is possible to obtain a thickness such that the subsequent thermal oxidation becomes diffusion-limited. Since we deposited an insulating film in advance and then formed a silicon crystal layer using a thermal oxidation method, changes in the threshold voltage of the MOS device were small, the interface state density with the silicon crystal was small, and the dielectric breakdown voltage was low. An excellent gate insulating film can be obtained.

[Brief explanation of drawings]

FIG. 1 is a vertical side view of a MOS transistor for explaining an embodiment of the present invention, and FIGS. 2 to 7 are cross-sectional views showing the manufacturing process thereof. 1... Insulating base 11... Quartz substrate 2.12... Semiconductor layer 3.13... Source, drain region 4.14... SiOz film 5 by thermal oxidation method...
Insulating film 15 by CVD method...SiO□ film 6.16 by CVD method...Gate electrode 7.17...Interlayer insulating film 8.18...A1 wiring 9.19...Protective film 101...・ ・ si* N4 102・ ・ ・ S i Oz Agent Patent Attorney Minoru Yamashita Children 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Sip Ordinance Figure 7

Claims (1)

[Claims] 1) In a method for manufacturing a semiconductor device in which a gate insulating film is formed by depositing an insulating film on a substrate having a silicon semiconductor layer and then oxidizing the silicon semiconductor, the insulating film is formed by depositing a gate insulating film on a substrate having a silicon semiconductor layer. 2) A method for manufacturing a semiconductor device, characterized in that the semiconductor device is formed to a predetermined thickness sufficient to provide a sufficiently long oxidation time in which the oxidation of the semiconductor is governed by diffusion-limited oxidation, and a thermal oxidation method is used for the oxidation. 2) The above-mentioned method 2. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film is formed using a chemical vapor deposition method or a sputtering method.