JPH04186787A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH04186787A
JPH04186787A JP31400690A JP31400690A JPH04186787A JP H04186787 A JPH04186787 A JP H04186787A JP 31400690 A JP31400690 A JP 31400690A JP 31400690 A JP31400690 A JP 31400690A JP H04186787 A JPH04186787 A JP H04186787A
Authority
JP
Japan
Prior art keywords
layer
inp
active layer
gas
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31400690A
Other languages
Japanese (ja)
Inventor
Toshihiro Ono
智弘 大野
Toshio Kirihara
桐原 俊夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP31400690A priority Critical patent/JPH04186787A/en
Publication of JPH04186787A publication Critical patent/JPH04186787A/en
Pending legal-status Critical Current

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  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To bury both sides of the active layer of a semiconductor device with a high resistance InP layer by letting P supply gas such as PH3 gas and organic metal gas, which contains Fe and Co, flow inside a reaction tube. CONSTITUTION:InGaAP2, an InP layer 3, an InGaAsP active layer 4, an InP layer 5, InGaAsP6 are crystal-grown in order on an InP substrate 1. Thereon, SiO27 is patterned by ordinary photolithography method, and by dry etching, a ridge is made. Then, a wafer is put in etchant to etch the InGaAsP layer. This is put in a MOCVD device, and the iron and the cobalt of phosphine gas and organic metal gas are let flow at the same time, and the wafer is heated in PH3, Fe, Co atmosphere 11. Since Fe and Co are flowing, those are taken in at mass transport, and a high-resistance buried layer 12 is formed.

Description

【発明の詳細な説明】 [産業上の利用分野〕 本発明は半導体装置の製造方法に係り、特に半導体レー
ザや進行波型光増幅器などの半導体装置の製造に適した
方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method suitable for manufacturing semiconductor devices such as semiconductor lasers and traveling wave optical amplifiers.

〔従来の技術〕[Conventional technology]

従来から行われていたマストランスポート法について説
明する。
The conventional mass transport method will be explained.

第2図の様に、InP基板1上にInGaAsPウェー
ブガイド層2.InPストップInP層3゜InGaA
sP活性層4.P”−InP クラッド層5.P” −
InGaAsP  キャップ層6及びS i 02層7
を順次積層した後、第3図の様なりッジを形成し、次に
第4図の如く選択エッチにより活性層4をエツチングし
幅を狭くする。この際に活性層4の両サイドにはすきま
ができる。このウェハ10を第5図の様にMOCVD装
置の石英反応管8内サセプター9上に入れ、燐(P)供
給のためにPH,ガスが流しながら650℃位で約1時
間加熱する。これにより第6図の様に、InP層5から
InPが移動し、活性層4の両サイドのすきまを埋め込
んでくれる。
As shown in FIG. 2, an InGaAsP waveguide layer 2. InP stop InP layer 3゜InGaA
sP active layer 4. P"-InP cladding layer 5.P"-
InGaAsP cap layer 6 and SiO2 layer 7
After sequentially laminating the active layer 4, a ridge as shown in FIG. 3 is formed, and then the active layer 4 is etched by selective etching to narrow the width as shown in FIG. At this time, gaps are created on both sides of the active layer 4. This wafer 10 is placed on a susceptor 9 in a quartz reaction tube 8 of an MOCVD apparatus as shown in FIG. 5, and heated at about 650° C. for about 1 hour while flowing PH and gas to supply phosphorus (P). As a result, as shown in FIG. 6, InP moves from the InP layer 5 and fills the gaps on both sides of the active layer 4.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上記従来技術は、マストランスポートで埋め込まれたI
nP層のキャリヤ濃度の点について配慮がされておらず
、キャリヤ濃度が1016all−3台でn−形のこの
InP埋込み層と、P”−InP  クラッド層5との
間にpn接合が形成されるので、この部分から電流が流
れやすく、活性層へのキャリヤ注入が減るという問題が
あった。
The above-mentioned conventional technology is based on I
No consideration was given to the carrier concentration of the nP layer, and a pn junction was formed between this n-type InP buried layer and the P''-InP cladding layer 5 with a carrier concentration in the 1016all-3 range. Therefore, there was a problem in that current easily flows from this portion and carrier injection into the active layer is reduced.

本発明は、マストランスポートで埋込まれるInP層を
高抵抗化(10”Ω■以上)し、半導体装置の活性層等
、キャリヤ注入により動作する能動層における注入密度
を増やすことを目的とする。
The purpose of the present invention is to increase the resistance of the InP layer buried by mass transport (10" Ω or more) and increase the injection density in active layers that operate by carrier injection, such as the active layer of a semiconductor device. .

〔課題を解決するための手段〕[Means to solve the problem]

上記目的を達成するために、加熱装置を有する反応管内
に、PH,ガスの様なP供給ガスと。
In order to achieve the above objective, a P supply gas such as PH gas is added into the reaction tube with a heating device.

InPを高抵抗化するFeやCoを含む有機金属ガスを
同時に流してやりマストランスポートを行ったものであ
る。
Mass transport is carried out by simultaneously flowing an organometallic gas containing Fe and Co that increases the resistance of InP.

〔作用〕[Effect]

InPを高抵抗化するFeやCOを含む有機金属ガスを
同時に流しながらマストランスポートを行うとマストラ
ンスポートしたInP中にこれらの元素がとり込まれる
。それによって高抵抗化されたInPが活性層の両サイ
ドを埋込んでくれる。
When mass transport is carried out while simultaneously flowing an organometallic gas containing Fe and CO that increases the resistance of InP, these elements are incorporated into the mass-transported InP. As a result, the high resistance InP buries both sides of the active layer.

Fe及びcoはInP中107an−’程度の濃度が取
り込まれる。
Fe and co are incorporated into InP at a concentration of about 107an-'.

〔実施例〕〔Example〕

第1図及び第2−第6図を今−炭層いて、本発明に係る
実施例を説明する。以下は、高抵抗InP埋込層を形成
した。進行波型光増器の製造方法に関する。まず第2図
の様にInP基板1上にInGaAsP(波長1.15
μm)2.InP層3.InGaAsP (波長1.3
μm)活性層4゜InP層5 、 I n G a A
 s P (波長1.15μm)6を順次結晶成長する
。その上にSiO27を通常のホトリソ工程でパターン
を作り、ドライエツチング法により、第3図の様なリッ
ジを形成する。
Embodiments according to the present invention will be described with reference to FIG. 1 and FIGS. 2 to 6 showing a coal seam. Below, a high resistance InP buried layer was formed. This invention relates to a method for manufacturing a traveling wave optical multiplier. First, as shown in Fig. 2, InGaAsP (wavelength 1.15
μm)2. InP layer 3. InGaAsP (wavelength 1.3
μm) Active layer 4゜InP layer 5, InGaA
Crystals of s P (wavelength 1.15 μm) 6 are sequentially grown. A pattern of SiO27 is formed thereon by a normal photolithography process, and a ridge as shown in FIG. 3 is formed by dry etching.

この後ウェハを、硫酸:水:過酸化水素水=4=1:1
エツチング液中に入れる事によりInGaAsP層のみ
がエツチングされ、第4図の様にInGaAsP活性層
の幅を狭くすることができる。これを第1図の様にMO
CVD装置の反応管内に入れ、ホスフィン(PH,)ガ
スと有機金属ガスの鉄(Fe)とコバルト(Co)を同
時に流し、PH3,Fe、Co雰囲気11内でウェハを
650℃位で加熱してやる。
After this, the wafer was mixed with sulfuric acid: water: hydrogen peroxide solution = 4 = 1:1.
By placing it in an etching solution, only the InGaAsP layer is etched, and the width of the InGaAsP active layer can be narrowed as shown in FIG. This is MO as shown in Figure 1.
The wafer is placed in a reaction tube of a CVD apparatus, and phosphine (PH) gas and organometallic gases iron (Fe) and cobalt (Co) are flowed simultaneously, and the wafer is heated to about 650° C. in a PH3, Fe, and Co atmosphere 11.

第1図の工程を行うと、第6図に示すようにInP層5
のInPがマストランスポート現象を起こしI n G
 a A s P活性層の両サイドのすきまを埋め込ん
でくれる。この際、反応管内にはInPと結合して半絶
縁性を示すFeとCOが流れているので、マストランス
ポート時に取り込ま九て高抵抗InP埋込層12が形成
さ九る。
When the process shown in FIG. 1 is carried out, the InP layer 5 as shown in FIG.
InP causes a mass transport phenomenon, and InP
a A s P Fills the gaps on both sides of the active layer. At this time, since Fe and CO, which combine with InP and exhibit semi-insulating properties, are flowing in the reaction tube, they are taken in during mass transport and form a high-resistance InP buried layer 12.

本発明の方法により、活性層の両サイドを高抵抗InP
で埋め込んだ構造をもつ進行波型光アンプは、注入電流
が活性層に集中するので高い利得が得られる効果がある
By the method of the present invention, both sides of the active layer are formed using high-resistance InP.
A traveling wave optical amplifier with a buried structure has the effect of obtaining high gain because the injected current is concentrated in the active layer.

第7図は半導体レーザに応用した例である。FIG. 7 shows an example of application to a semiconductor laser.

InP基板13上に、InGaAsP層14゜InGa
AsP活性層16.InGaAsP層・ 17.InP
クラッド層18.InGaAsPキャップ層19.高抵
抗InP埋込層15を上述した実施例と同様に形成する
。この場合も、従来方法でマストランスポートして埋め
込んだものよりも、低しきい値化等に効果がある。
On the InP substrate 13, an InGaAsP layer 14°InGa
AsP active layer 16. InGaAsP layer・17. InP
Cladding layer 18. InGaAsP cap layer 19. A high-resistance InP buried layer 15 is formed in the same manner as in the embodiment described above. In this case as well, it is more effective in reducing the threshold value than the conventional method of mass transport and embedding.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、半導体装置の能動層の両側面を高抵抗
InP層で容易に埋込むことができる6
According to the present invention, both sides of the active layer of a semiconductor device can be easily filled with a high-resistance InP layer6.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例に係るマストランスポートの方
法を示した図、第2図から第6図は進行波型光増器の活
性層両サイドに高抵抗InP埋込層を形成するためのプ
ロセスを説明するため図。 第7図は本発明の方法を利用して半導体レーザの活性層
の両側面を埋込んだ構造を説明するための図である。 VJ  岬 ご 第2 l ¥J3図 ¥J 4 図
FIG. 1 shows a mass transport method according to an embodiment of the present invention, and FIGS. 2 to 6 show high resistance InP buried layers on both sides of the active layer of a traveling wave optical amplifier. Diagram to explain the process. FIG. 7 is a diagram for explaining a structure in which both sides of the active layer of a semiconductor laser are buried using the method of the present invention. VJ Misakigo 2nd l ¥J3 drawing¥J 4 drawing

Claims (1)

【特許請求の範囲】 1、III−V化合物半導体よりなる能動層とのヘテロ構
造を有する半導体装置の製造方法において、上記能動層
の両側面を高抵抗InPで埋め込むために、マストラン
スポートを用いたことを特徴とする半導体装置の製造方
法。 2、請求項1に記載の半導体装置の製造方法において、
Pを供給するガスと、InPを結合して半絶縁性を示す
ガスとを同時に流しながら前記マストランスポートを行
う半導体装置の製造方法。 3、請求項1に記載の半導体装置の製造方法において、
前記能動層が注入されたキャリアにより光を放出するた
めの活性層である半導体装置の製造方法。
[Claims] 1. In a method for manufacturing a semiconductor device having a heterostructure with an active layer made of a III-V compound semiconductor, mass transport is used to fill both sides of the active layer with high-resistance InP. A method for manufacturing a semiconductor device, characterized in that: 2. In the method for manufacturing a semiconductor device according to claim 1,
A method for manufacturing a semiconductor device in which the mass transport is performed while simultaneously flowing a gas that supplies P and a gas that combines InP and exhibits semi-insulating properties. 3. The method for manufacturing a semiconductor device according to claim 1,
A method for manufacturing a semiconductor device, wherein the active layer is an active layer for emitting light using injected carriers.
JP31400690A 1990-11-21 1990-11-21 Manufacture of semiconductor device Pending JPH04186787A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31400690A JPH04186787A (en) 1990-11-21 1990-11-21 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31400690A JPH04186787A (en) 1990-11-21 1990-11-21 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH04186787A true JPH04186787A (en) 1992-07-03

Family

ID=18048081

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31400690A Pending JPH04186787A (en) 1990-11-21 1990-11-21 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH04186787A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7230276B2 (en) 2002-11-11 2007-06-12 Electronics And Telecommunications Research Institute Semiconductor optical device having current-confined structure
JP2011035077A (en) * 2009-07-30 2011-02-17 Canon Inc Method for fabricating semiconductor element, and semiconductor element

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7230276B2 (en) 2002-11-11 2007-06-12 Electronics And Telecommunications Research Institute Semiconductor optical device having current-confined structure
US7394104B2 (en) 2002-11-11 2008-07-01 Electronics And Telecommunications Research Institute Semiconductor optical device having current-confined structure
JP2011035077A (en) * 2009-07-30 2011-02-17 Canon Inc Method for fabricating semiconductor element, and semiconductor element

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