JPH04185461A - Charactor pattern generator - Google Patents

Abstract

PURPOSE:To make it possible to decide whether dots are for printing or not for printing by means of an inexpensive hardware at high speed by providing an OR circuit wherein input from a first input terminal and output of a delay circuit are inputted and output is outputted to an AND circuit as other input. CONSTITUTION:There are provided a first input terminal 1 into which on-dot data is inputted, a second input terminal 2 into which off-dot data is inputted, an invertor 3 which reverses input of the terminal 2 and outputs said reversed input as output 11, an AND circuit 4 which takes in logical product of the output 11 of the invertor 3 and output 14 of an OR circuit 6 to output it as output 12, a delay circuit 5 which delays the output 12 of the circuit 4 to output it as output 13, the OR circuit 6 which takes in logical sum of the input of the terminal 1 and the output 15 of the circuit 5 to deliver it as output 14, and an output terminal 7 for outputting the output 12 of the circuit 4 as printing data.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a character pattern generator used in printers and the like that represents characters using character patterns that are collections of dots, and particularly relates to character pattern generators that represent characters using character patterns that are collections of dots. The present invention relates to a character pattern generator that sequentially outputs print data one dot at a time for each column.

[Conventional technology]

Conventionally, this type of character pattern generator has been available in bitmap format and outline font format.

Bitmap format stores character patterns by associating 1 dot with 1 bit, and outputs the stored character pattern as is.As the number of dots that make up one character increases, the amount of data to be stored increases. increases,
There is a drawback that when attempting to enlarge and print characters, the dots appear to be larger in size, making them difficult to see. Therefore, only the data of the outline of the character is memorized, and each time when printing, it is determined whether each dot making up the character pattern is a dot to be printed or a dot not to be printed, based on the data of the outline of the character. An outline font format that outputs patterns was devised.

[Problem to be solved by the invention]

Among the conventional character pattern generators mentioned above, those in the outline font format generate character patterns based on outline data, with each dot located inside the outline for printing. It takes time to determine whether the dot is a dot or a dot that is outside the outline and will not be printed, and when the printing speed is high, character pattern generation cannot keep up with it, and complex hardware is required to generate the character pattern. The disadvantage is that it is expensive.

An object of the present invention is to develop an inexpensive and high-speed character pattern generator by quickly determining whether each dot forming a character pattern is a dot for printing or a dot for not printing using inexpensive hardware. It is about providing.

[Means to solve the problem]

The character pattern generator of the present invention has a first input terminal that inputs "1" in response to a dot to be printed that replaces a non-printed dot among the dots in a row of dots parallel to the development direction of the character pattern. , a second input terminal that inputs "1" corresponding to the unprinted dot placed after the printed dot among the dots in the dot row; an output terminal; and inverts the input of the second input terminal. an inverter, a delay circuit that delays an input by a time corresponding to one ton of sequentially output print data and outputs the output; the output of the inverter is used as one input, and the output is output to the delay circuit and the output terminal. and an OR circuit that inputs the input from the first input terminal and the output of the delay circuit, and outputs the output to the AND circuit as the other input.

[Effect]

In the initial state, the first input terminal and the second input terminal have "
0" is input, and the output of the delay circuit is "0".Here, when the output of the first input terminal becomes "1", the output of the OR circuit and the output of the inverter both become "1", so the AND The output of the circuit becomes "1", and "l" is output to the output terminal and the input of the delay circuit.Next, even if the input of the first input terminal becomes "0", the output of the delay circuit is Since it is "1", the output of the OR circuit 6 is "1" and the output of the AND circuit is "1".
After that, when "1" is input to the second input terminal, the output of the inverter becomes O', the output of the AND circuit becomes "O", and the output terminal and the input of the delay circuit become O'. Even if the second input terminal becomes "0", the output of the OR circuit remains "O", so the AND circuit outputs "0".
” continues to be output. Therefore, “1” is output to the first input terminal.
The print data is "1" until "1" is input to the second input terminal after " is input."

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a character pattern generator according to an embodiment of the present invention, FIG. b) and (c) are the dots whose on-dot data and off-dot data are "1" when the characters r A J in Fig. 2 (a) are expanded from left to right, Fig. 2 (d), (e) are shown in Figure 2 (b),
When the on-dot data and off-dot data based on (c) are input to the first input terminal 1 and the second input terminal 2, the output from the output terminal 7 and the output 1 of the OR circuit 6, respectively.
A diagram showing a dot where 4 is "1", Figure 3 is similar to Figure 2 (a
) is a timing chart of this embodiment regarding the third dot row 21 from the bottom of the letter "A".

This embodiment includes a first input terminal 1 to which on-dot data is input from a memory (not shown), a second input terminal 2 to which off-dot data is input from a memory (not shown), and a second input terminal 2 to which off-dot data is input from a memory (not shown). An inverter 3 that inverts the input of the input terminal 2 and outputs it as an output 11, an output 11 of the inverter 3, and an OR circuit 6
an AND circuit 4 which performs an AND with the output 14 of the ant circuit 4 and outputs the result as an output 12; a delay circuit 5 which delays the output 12 of the ant circuit 4 and outputs the result as an output 13; and a first input terminal 1.
It consists of an OR circuit 6 which takes the logical sum of the input of the input and the output 13 of the delay circuit 5 and outputs the result as an output 14, and an output terminal 7 which outputs the output 2 of the AND circuit 4 as print data. The print data is "l" when printing dots for each dot row parallel to the development direction of the character pattern.
, is "0" when a dot is not printed, and is output one dot at a time. The delay circuit 5 delays the input data by a time corresponding to one bit of print data sequentially output from the output terminal 7 and outputs the delayed data from the output 13.

Here, on-dot data and off-dot data will be explained.

The on-dot data and the off-dot data are both stored in a memory and input to the first input terminal 1 and the second input terminal 2, respectively, in synchronization with a clock (not shown). The on-dot data is "1" at the timing when the print data corresponding to the dot to be printed next to the dot that is not printed among the dots parallel to the development direction of the character pattern is output, and is "0" at other times. be. Off-dot data is
It is "1" at the timing of outputting print data corresponding to the unprinted dot next to the printed dot among the dots in the previous dot row, and is "0" at other times.

FIG. 2(a) shows the letter "A" represented by a dot structure of 16 bits vertically and 15 bits horizontally. When the characters rAJ are expanded from left to right, the dots corresponding to the timings when the on-dot data becomes "1" for each horizontal dot row are shown in Figure 2 (
b)

Similarly, the dots corresponding to the timing when the off-dot data becomes "1" are shown in FIG. 2(C). In this example, since there are 16 vertical dots, 16 character pattern generators of this embodiment are provided corresponding to each of the 16 horizontal dot rows.

Next, the operation of this embodiment will be explained.

Here, regarding the character "rA" in Figure 2 (a),
The operation of the character pattern generator of this embodiment provided corresponding to the third dot row 21 from the bottom will be explained.

The on-dot data shown in Figure 2(b) is 3 from the bottom.
For the th dot row 21, r 010000000
000100 J, and are input to the first input terminal 1 in this order. The off-dot data shown in FIG. 2(C) is r00 for the third dot row 21 from the bottom.
0]00000000001J, and are input to the second input terminal 2 in this order.

In the initial state, the output I3 of the delay circuit 5 is "0".

Here, when the first data (both "0") of the on-dot data and off-dot data is input to the first input terminal 1 and the second input terminal 2, the output 11 of the inverter 3 becomes "1".
”, but since the output 14 of the OR circuit 6 is “0”,
The output 12 of the AND circuit 4 is "0", and "0" is output from the output terminal 7. However, the print data corresponding to the first dot is "0". "0" is input to the delay circuit 5. The second on-dot data and off-dot data are "1" and "0", respectively. When these are input to the first input terminal l and the second input terminal 2, the output 13 of the delay circuit 5 is "0", but since the input of the first input terminal 1 is "1°", the OR circuit 6 Output 14 of inverter 3 becomes "l", and output 11 of inverter 3 also becomes "l".
1", the output 12 of the AND circuit 4 becomes 1", the output terminal 7 outputs "1", and the delay circuit 5 receives "1". Therefore, the print data corresponding to the second dot is "1".The third on-dot data and off-dot data are both "0", and when these are input, the delay circuit is activated when the second data is input. Since 1" is input to 5, "1" is output from output 13, and even if the input of first input terminal 1 is @"0", output 1 of OR circuit 6
4 is 11", and since 8 and 11 of the inverter 3 are "1", the output of the AND circuit 6]2 is "1". Therefore, "1" is output to the output terminal 7, and the delay circuit "1" is input to 5, and the print data corresponding to the third dot is "1".The on-dot data and off-dot data input fourth are "0" and "1", respectively.

Since "1' is input to the delay circuit 5 at the time of the third data, the ratio 13 is "1", and the 8 factors 14 of the OR circuit 6
is "1". However, the input of the second input terminal 2 is "
1", the output 11 of the inverter 3 becomes "0", the output 12 of the AND circuit 4 becomes "0", the output terminal 7 outputs "0", and the delay circuit 5 outputs "0". Therefore, the print data corresponding to the 4th dot is "0". Both the on-dot data and the off-dot data of the 5th are "O". Since "0" is input, the output 13 of the delay circuit 5 is "0", and the stiffness is exactly the same as when the first data is input. Therefore, the output I2 of the ant circuit 6 is “0” and the output terminal 7 becomes “0”.
``, and the delay circuit 5 continues to input ``0''.

Therefore, the print data corresponding to the 5th dot is "
0".Hereafter, as long as both the on-dot data and off-dot data are "0", the same operation as that for the fifth dot is repeated, and the output terminal 7 outputs "0".
continues to be output, and the print data corresponding to up to the 12th dot remains "0". The 13th on-dot data and off-dot data are "1" and "0", respectively. At this time, the output [12] of the delay circuit 5 is "0", and the stiffness is in the same state as when the second data was input, so the output 12 of the AND circuit 4 is "1", and the output from the output terminal 7 is It outputs "1" and the delay circuit 5 inputs "!". Again, the above-described operation is repeated based on the values of the on-dot data and off-dot data. In the end, Figure 2(a)
When on-dot data and off-dot data corresponding to the third dot row 21 from the bottom of the letter "A" are input, the print data output from the output terminal 7 is r0110.
o0000000110 J There is. Regarding the dots in the third dot row 21 from the bottom of the letter AJ in Figure 2 (a), if the dots to be printed are ``1'' and the dots not to be printed are ``0'', then r from the left is 01100000000
0110 J, and the print data output from the output terminal 7 completely matches this. Note that the output 1 of the OR circuit 6
4 changes to r01]]00000000111 J, and assuming that it is printed based on the output 14 of the OR circuit 6, the dot will be 1 dot thicker than when it is printed based on the print data output from the output terminal 7. You can see that it is printed.

The above explanation is based on
This is the case of the th dot row 21, which is shown in Fig. 2 (a
) is applied to all 16 horizontal dot rows, and when the on-dot data and off-dot data shown in Fig. 2 (b) and (c) are input, the output from input terminal 7 of Sonezawa is as follows. The print data that shows the dot "I" is shown in Figure 2 (d), and based on this, the print data shown in Figure 2 (
The letters rAJ in a) are completely reproduced. Also, Fig. 2(e) shows the dots where the output 14 of each OR circuit 6 is "1", and if printed based on this, the dots shown in Fig. 2(a) will be "horizontal from AJ". It can be seen that the dot becomes 1 dot thicker.On-dot data and off-dot data are created so that the same dot does not become 1" at the same time, but when generating a character pattern for a reduced character,
When on-dot data and off-dot data for reduced characters are created by calculation from on-dot data and off-dot data for normal-sized characters, both may become "1" for the same dot at the same time. At this time, the output 11 of the inverter 3 becomes "o", so the output 12 of the AND circuit 4 becomes "O", and the output from the 8-power terminal 7 becomes "0".
will be output, and this dot will not be printed. At this time, the output 14 of the OR circuit 6 is.

Since the input of the first input terminal 1 is "1", it is "工", and when generating a character pattern of reduced characters,
Prints when output 14 of OR circuit 6 is “1” and “0”
By not printing when , it is possible to prevent characters from being blurred due to the necessary dots not being printed.

(Effects of the Invention) As explained above, the present invention inputs on-dot data and off-dot data, and converts the dot corresponding to the on-dot data that is "1" to the dot that corresponds to the off-dot data that is "1". By generating print data that prints up to the dot just before the dot, dot filling operations can be performed at high speed with simple hardware.
This method has the advantage of being able to generate character patterns at low cost and at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a character pattern generator according to an embodiment of the present invention, and FIG. b) and (c) are diagrams showing the dots whose on-dot data and off-dot data are "1" when the character rAJ in Figure 2(a) is expanded from left to right, and Figure 2(d) is ), (e) are shown in Figure 2 (b), (c
) based on on-dot data and off-dot data are the first
Figure 3 is a diagram showing a dot in which the output from the output terminal 7 and the output 14 of the OR circuit 6 are "1" when input to the input terminal l and the second input terminal 2, respectively. 12 is a timing chart of the present embodiment regarding the third dot row 21 from the bottom of the character "rA" in a). 1...First input terminal, 2...Second input terminal, 3...Inverter, 4...... Ant circuit, 5...Delay circuit, 6...OR circuit, 7...Output terminal, 11-14...Output, 21. ......Third row of dots from the bottom.

Claims (1)

[Claims] 1. A character is represented by a character pattern that is a set of dots,
For each dot row parallel to the development direction of the character pattern, print data is sequentially output one dot at a time, which is "1" for a dot to be printed and "0" for a dot not to be printed.
A character pattern generator used in a printer, etc., comprising: a first input terminal for inputting "1" corresponding to a dot to be printed placed next to a dot not to be printed among the dots in the dot row; a second input terminal that inputs "1" corresponding to a non-printed dot placed after a printed dot among the dots in the column; an output terminal; an inverter that inverts the input of the second input terminal; a delay circuit that outputs an input with a time delay corresponding to one dot of the print data that is sequentially output; and an AND circuit that uses the output of the inverter as one input and outputs the output to the delay circuit and the output terminal. , a character pattern generator having an OR circuit that receives an input from a first input terminal and an output of the delay circuit, and outputs the output to the AND circuit as the other input.