JPS61189952A - Apparatus for generating character pattern - Google Patents

Abstract

PURPOSE:To make it possible to perform a high speed printing by using a pattern with a half, by obtaining first data by taking a logical sum in adjasent printing timing and succeedingly performing thinning so as to obtain a dot interval. CONSTITUTION:A doubled speed printing character pattern generation apparatus 3 is constituted of a reversal circuit 3a taking the negation of one line in the longitudinal direction of pattern data constituting one character stored in a character generator 1, a first operation register 3b for storing the dot data from the reversal circuit 3a, an OR circuit 3c for parallelly taking the logical sum of two adjacent lines of the character generator 1, a second operation register 3d for storing OR output from the OR circuit 3c, an AND circuit 3e for taking AND of contents of the operation registers 3b, 3d in a parallel mode and a control circuit 3f. By this constitution, high speed printing for a draft can be realized in addition to high quality printing.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a character pattern generation device that generates character pattern data suitable for driving a dot matrix type serial printer to print at high speed.

(Prior art) A dot matrix serial printer has a print head consisting of dot generating mechanisms arranged in a line in the paper feed direction.
This is a device that performs printing by driving a dot generating mechanism at a location corresponding to a character while moving the platen in the axial direction.

By the way, the performance generally required of a printer is printing speed and printing quality, but in the above-mentioned dot matrix type serial printer, the dot density has a large effect on printing quality, so printing speed and printing quality conflict with each other. 1
It is in the SfI section.

For this reason, in printing where printing speed is more important than printing quality, such as printing for drafts, for example, Japanese Patent Laid-Open No. 58-160159 and Japanese Patent Laid-Open No. 59-1
As seen in Japanese Patent No. 48668, adjacent dots of the dots forming a character pattern are thinned out to generate a pattern with lower dot density, and this pattern is used as print data.

On the other hand, since it is also required to improve the print quality in the normal mode, as shown in FIG. The dots are arranged so that they are not adjacent to each other in the ascending line parallel to , L2...Ln, making it possible to effectively use the idle dot generation mechanism, thereby smoothly expressing diagonal lines, etc. A dot pattern (hereinafter referred to as a pattern with half) for high quality printing that can be printed has been adopted.

As mentioned above, the half pattern is created with the alignment position at approximately 1/2 of the response time of the dot generation mechanism, that is, the printing timing Tp, so even if the dots that are in contact with #1 are simply thinned out, the response of the dot generation mechanism will be reduced. Almost 1/2 of the time
There remains a possibility of generating a dot signal adjacent to the position of
Still, the print head can only be moved at the speed for normal printing, making high-speed printing impossible, and if this is ignored and the head feeding speed is increased, there is a problem that the dot generation mechanism will be damaged.

(Objective) In view of the above problems, it is an object of the present invention to provide a character data generation device that can perform high-speed printing using a half pattern.

That is, one feature of the present invention is that first data is obtained by performing a logical sum at adjacent print timings, and then thinning is performed to obtain the dot spacing.

(Structure) Therefore, details of the present invention will be described below based on illustrated embodiments.

FIG. 1 shows an embodiment of the present invention. In FIG. 1, group number 1 is a character generator that stores half pattern data.
Half pattern data composed of 2 bits is stored in a regularly addressed manner. 2 is a line buffer memory that stores character pattern data output from the character generator 1 or pattern data output from a double-speed character pattern generation device 3 to be described later.
After storing data for each line, it is output to the print head in synchronization with a print timing signal. Reference numeral 3 denotes a character pattern generator for double speed, which is an uninvented part of the # symbol, and generates one vertical column of pattern data constituting one character stored in the character generator 1, 12-bit data in this embodiment. The inversion circuit 3 & which takes negation stores the dot data from the inversion circuit 3a, which has a 12-bit suspicion in this embodiment for one column in the vertical direction of the pattern data constituting one character stored in the character generator l. The first arithmetic register 3b, the OR circuit 3C which once latches the data at the M-th address and the M+1-th address of the character generator l and calculates the OR of these in parallel, and one column of pattern data in the vertical direction, this embodiment Here, a second operation register 3d has a capacity of 12 bits and stores the logical sum output from the logical sum circuit 3c, and a logic circuit that logically ANDs the contents of the first and second calculation registers 3b and 3d in parallel format. A product circuit 3e and a control circuit 3f for controlling data input/output to these circuits 3a to 3e are also configured.

Next, the operation of the apparatus configured as described above will be explained based on the flowchart and operation diagram shown in FIG. 2.3.

From the host device (not shown), the first character, for example "F" (
3) is output, the character storage area of the character generator 1 that stores the dot pattern data of this character is selected.

When the character storage area is specified, the pointer of the character generator 1 is set to the initial address M=O of this character storage area, and the pointer of the line buffer memory 2 is set to the initial address N=O (a).Now, input character r
Since "F" comes at the beginning of the line (b), the control circuit 3f
sets the entire contents of the first calculation register 3b to 1, that is, ALL
Set to l.

Once these preparations have been completed, the first character storage area
Read the contents of the address M=O and the first address M=1, output them to the OR circuit 3C, take a logical OR, and store this OR output in the second operation register 3d (2), the first operation register 3b and the contents of the second arithmetic register 3d are output to the AND circuit 3e, and the logical product of both is taken, and this is stored in the first arithmetic register 3b (e), while it is output to the line buffer memory 2 and its contents are Store at initial address N=0 (see Figure 2) (Table 1, Step 1).

In this way, when the processing for the initial address of line buffer memory 2 is completed, the pointer of character generator 1 is advanced by two to the second address M=2, and the pointer of line buffer memory 2 is advanced by one. Specify the first address N=1 (g). Since the dot data that constitutes the character "F" still remains in the character storage area of the character generator l, further processing is necessary. (blood). Since the pointer of the line buffer memory 2 has moved away from the initial address due to the previous step (b), the contents of the address N=0, which is the one before the pointer of the line buffer memory 2 is moved, are read out and the contents are read out by the inverting circuit 3a. It is inverted and stored in the first calculation register 3b (c). Third address M=2 in character storage area
and the contents of the fourth address M=3 are read and the logical sum circuit 3C
and stores the OR output in the second arithmetic register 3d (2). The contents of the first and second arithmetic registers 3b and 3d are output to the AND circuit 3e, and the AND of the two is calculated.

By this calculation, M=2 columns of dots that may be adjacent on the same line are screened out. This calculation result is stored in the first calculation register 3b (e), while it is stored in the second address N=1 of the line buffer memory 2 (second
(see Figure) (Table 1 Step 2). As a result, the vertical line, which is a characteristic part to represent "F", that is, M=
The dots forming M3 columns are extracted, and at the same time M=2 columns of dots that may be adjacent on the same horizontal line are screened out.

When the processing for the first address N = 1 of the line buffer 7 memory 2 is completed, the pointer of the character generator] is advanced by two to the fifth address M = 4, and the pointer of the line buffer memory 2 is advanced by 1. dL to specify the third address N=2. Line buffer memory 2
The data stored immediately before, that is, address N=
Read the contents of 1, invert it, and write it to the first calculation register 3.
Store in b (c). The contents of the fifth address M=4 and the sixth address M=5 in the character storage area are read and output to the OR circuit 3C, and the OR output is stored in the second arithmetic register 3d (2).

The contents of the first and second rii arithmetic registers 3b and 3d are output to the AND circuit 3e, and the AND of the two is taken.
While storing in the y4 arithmetic register 3b, it is also stored in the third address N=2 of the line buffer memory 2 (to Figure 2) (
Table 1 Step 3) This eliminates the vertical lines added to improve print quality, that is, the dot data in M=5 columns.

Hereinafter, as long as the dot pattern data of the area accommodating the character rFJ exists in this way, as shown in FIG.
Processes from (h) to (h), that is, reading out the dot pattern data in the character pattern storage area two columns at a time, taking the logical sum of these, and inverting this logical sum and the data stored in the line buffer memory 2 one step before. Take the AND with the value,
Line buffer 7 memory 2 uses this logical product as print data.
(Table 1 Step 4)
through step 9), through this series of processes, "FJ
The dot data arranged in the upper and lower two tree lines, that is, the zeroth line and tenth line, which is another characteristic part for representing the character , is extracted.

As a result, out of the character pattern formed by the half pattern, all the dots that characterize the character are extracted, while the dots added for the purpose of improving printing quality are erased. Moreover, in tIL parallel to the head movement direction, a new concise pattern that is not adjacent is generated.

In this way, when the processing for the first character is completed,
host? Waits for the next character to be input from cR, and stores the initial address of the area where the dot pattern data constituting this character is stored and the initial addresses (b) to (b) of the second character storage area of the line buffer 7 memory 2. Repeat the process in h).

In this way, when one line of data is stored in the line buffer memory (No), a print command is output (
In printing in this double speed mode, the printing timing signal is used as a dot pitch setting signal, and the print head is main-scanned at twice the speed of the normal printing mode.

By the way, as mentioned above, the newly generated character pattern is formed by merging two adjacent rows of the half pattern into one row, so it is compressed to the length of the head in the head feeding direction. However, in the single-speed printing mode, the print head moves at twice the speed as in the normal printing mode, so no distortion occurs in the characters printed on the paper.

In this embodiment, each logical operation process is executed in parallel format, but it goes without saying that the same effect can be achieved even if the process is performed in serial format.

In addition, in this embodiment, f
1. Six registers,
It goes without saying that the present invention can be applied regardless of the number of character dots by replacing the arithmetic means such as a logic circuit with one having a capacity that at least covers the number of character bits.

(Effects) As described above, according to the present invention, the logical sum of two adjacent rows of dot pattern data is taken, and the logical fN of this and the inverted value of the immediately preceding printed dot data in the line buffer memory is calculated. As a result, the features of the basic pattern can be completely extracted through simple signal processing, and at the same time, dots added for the purpose of improving print quality can be removed, while dots that are adjacent to each other on a line parallel to the direction of head movement can be removed. It is possible to form a character pattern that is perfectly concise and to generate a character dot pattern that matches the dot spacing, and in addition to high-quality printing, high-speed printing for drafts can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an apparatus showing an embodiment of the present invention;
Figure 2 is a flowchart showing the operation of the same device; Figures 3 (A) and (C) are explanatory diagrams showing the processing process by the same device; Figure 4 shows an example of a half dot pattern. It is an explanatory diagram. 3...Double speed character pattern generator ν People screaming artificial presson Co., Ltd. Suwa Seikosha Co., Ltd. Figure 1 Photo immersion! Figure 2

Claims (1)

[Claims] Character generating means for accommodating a half-dot pattern, logical sum operation means for outputting the logical sum of two adjacent columns of the half-dot patterns, and inverting means for outputting an inverted value of the immediately preceding data stored in the lie buffer memory means. , a character pattern generating device comprising an AND operation means for logically multiplying the outputs from the logical sum operation means and the inversion means.