JPH0418458U - - Google Patents

Info

Publication number
JPH0418458U
JPH0418458U JP1990060361U JP6036190U JPH0418458U JP H0418458 U JPH0418458 U JP H0418458U JP 1990060361 U JP1990060361 U JP 1990060361U JP 6036190 U JP6036190 U JP 6036190U JP H0418458 U JPH0418458 U JP H0418458U
Authority
JP
Japan
Prior art keywords
lead
land
lead frame
wire
perforation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990060361U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990060361U priority Critical patent/JPH0418458U/ja
Publication of JPH0418458U publication Critical patent/JPH0418458U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49109Connecting at different heights outside the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第1図は本考案に係る第1の実施例を示す斜視
図、第2図は同じく断面図、第3図は本考案に係
る第2の実施例を示す斜視図、第4図は同じく断
面図である。第5図は従来のハイブリツドICの
斜視図、第6図は従来の半導体装置の斜視図、第
7図は従来の半導体装置をプリント基板に実装し
た際の断面図である。 9……リードフレーム、10……ランド部、1
1……半導体ペレツト、12……リード、13…
…ワイヤ、20……所定のリード、40……絶縁
板、41……穿孔部。

Claims (1)

  1. 【実用新案登録請求の範囲】 2枚のリードフレームの各ランド部にマウント
    した半導体ペレツトと各ランド部近傍に配置した
    リードとをワイヤにて接続し、各リードフレーム
    の裏面を絶縁板を介して対向させた半導体装置に
    おいて、 上記絶縁板のランド部とリードの基端部との間
    に穿孔部を設け、一方のリードフレーム上の半導
    体ペレツトと他のリードフレームのリードとを上
    記穿孔部を介してワイヤにて接続したことを特徴
    とする半導体装置。
JP1990060361U 1990-06-06 1990-06-06 Pending JPH0418458U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990060361U JPH0418458U (ja) 1990-06-06 1990-06-06

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990060361U JPH0418458U (ja) 1990-06-06 1990-06-06

Publications (1)

Publication Number Publication Date
JPH0418458U true JPH0418458U (ja) 1992-02-17

Family

ID=31587662

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990060361U Pending JPH0418458U (ja) 1990-06-06 1990-06-06

Country Status (1)

Country Link
JP (1) JPH0418458U (ja)

Similar Documents

Publication Publication Date Title
JPH0418458U (ja)
JPH0241329U (ja)
JPH0463147U (ja)
JPS6327053U (ja)
JPH031469U (ja)
JPH0476056U (ja)
JPH048468U (ja)
JPH0412680U (ja)
JPH0298651U (ja)
JPS59171350U (ja) 半導体素子の実装構造
JPH0444706U (ja)
JPS62168688U (ja)
JPH0474457U (ja)
JPS58128578U (ja) 接続端子装置
JPH0399443U (ja)
JPS63180938U (ja)
JPS61182077U (ja)
JPS62163939U (ja)
JPS62134274U (ja)
JPH0272554U (ja)
JPS5869980U (ja) 混成集積回路装置
JPS62149852U (ja)
JPS6390879U (ja)
JPS62191205U (ja)
JPS58180688U (ja) プリント基板取り付け装置