JPH04181594A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce initialization time by selecting a plurality of word lines simultaneously when initializing a semiconductor memory. CONSTITUTION:At the time of initialization, an initialization address generation circuit 8 allows two word lines to be selected simultaneously. In the circuit 8, an INIT signal is set to 'H' when initializing a memory and an output of a built-in inverter is connected to two word lines for simultaneous selection. Also, the signal is set to 'L' and an external address is connected to the word line directly. Then, this INIT signal is generated when the power is turned on and is turned off from a CPU when initialization is completed, thus enabling initialization time to be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor memories, and relates to reducing the initialization time of semiconductor memories.

[Conventional technology]

As is well known, a semiconductor memory capable of writing and reading operations is initialized after power is turned on. Initialization is an operation that writes the same data into memory cells of a semiconductor memory and determines the storage contents of the semiconductor memory after power is turned on.

FIG. 2 is a block diagram of a conventional semiconductor memory. The row decoder 2 selects one word line from the memory array 7 using the address from the row address buffer 1. Column decoder 4 selects a data line of memory array 7 using an address from column address buffer 3. Column I104 connects I10 buffer 5 and the data line selected by column decoder 4.

Next, a conventional memory initialization operation will be explained based on FIG. 2. One word line is selected by the row decoder 2 in accordance with the input address. Data is written into the memory cell selected by column decoder 4 from a plurality of memory cells connected to the selected word line. Initialization is performed by sequentially executing this operation from the first address to the last address of the memory.

[Problem to be solved by the invention]

The capacity of semiconductor memories is rapidly increasing, and the above-mentioned conventional technology requires a large amount of time for initialization, making it difficult to use systems using semiconductor memories.

An object of the present invention is to shorten the initialization time of a semiconductor memory in order to speed up the start of a system.

[Means to solve the problem]

In order to achieve the above object, the semiconductor memory of the present invention is configured such that a plurality of word lines can be selected simultaneously at the time of initialization.

[Effect]

In the semiconductor memory of the present invention, the word line n and the word line π corresponding to the external input address can be selected at the same time during initialization after the power is turned on, so it is possible to shorten the memory initialization time. Become.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a semiconductor memory according to an embodiment of the present invention. For a conventional semiconductor memory, by the initialization address generation circuit 8 at the time of initialization.

Two word lines can be selected simultaneously. In the initialization address generation circuit shown in FIG. 3, during memory initialization, the INIT signal is set to II H11, and the output of the inverter 10 is connected to the word line shoulder to select word lines n and i at the same time during normal operation. By setting the INIT signal to it L u, only word line n is selected.

The I-NIT signal may be generated when the power is turned on and erased from the CPU (not shown) when initialization is completed. Of course, it may be generated in other ways.

〔Effect of the invention〕

According to the present invention, a plurality of word lines can be selected simultaneously during an initialization operation in which the same data is written, so that the initialization time can be shortened.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a semiconductor memory according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional semiconductor memory, and FIG. 3 is a configuration diagram of an initialization address generation circuit. 1... Row address buffer, 2... Row decoder, 3... Column address buffer, 4... Column decoder, 5 - Engineering/○ buffer, 6... Column I10
．． 7...Memory array, 8...Initialization address generation circuit, 9...Tri-state gate, 1O...Inverter. Compilation I diagram

Claims (1)

[Claims] 1. It has memory cells arranged in an array in the row and column directions. Column selection is performed by selecting the bit line corresponding to the input address using a column decoder, and row selection is performed by selecting the bit line corresponding to the input address. A semiconductor memory capable of writing and reading operations performed by selecting lines with a row decoder, characterized in that the semiconductor memory is equipped with means for simultaneously selecting a plurality of word lines and writing the same data at the time of memory initialization.