JPH04180454A - Signal scanning circuit for close contact image sensor - Google Patents

Signal scanning circuit for close contact image sensor

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Publication number
JPH04180454A
JPH04180454A JP2307287A JP30728790A JPH04180454A JP H04180454 A JPH04180454 A JP H04180454A JP 2307287 A JP2307287 A JP 2307287A JP 30728790 A JP30728790 A JP 30728790A JP H04180454 A JPH04180454 A JP H04180454A
Authority
JP
Japan
Prior art keywords
level
scanning circuit
section
clock
signal scanning
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2307287A
Other languages
Japanese (ja)
Inventor
Seisaku Minamibayashi
南林 清作
Osamu Miura
修 三浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2307287A priority Critical patent/JPH04180454A/en
Publication of JPH04180454A publication Critical patent/JPH04180454A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To improve power efficient by adopting push-pull driver configuration for a signal scanning circuit and providing a ratio type inverter interrupting the conduction at a prescribed point of time to a master section so as to reduce power loss for an inactive output period. CONSTITUTION:When a shift clock phi1 is at a level of a power supply VDD, an input DIn is sent to a gate of a TR3. When the clock phi1 reaches a level G, a signal level is latched by a master section M by a capacitor C1. Simultaneously, when a clock phi2 reaches a level of the VDD, a ratio type inverter comprising TRs 5, 6 is acted and the output level stored in the C1 is sent to a slave section S. When the transfer is finished, the clock phi2 reaches the level G, the signal level is stored in a capacitor C2 and the conduction of a TR 2 of the section M is stopped and when the clock phi1 reaches the level of the VDD, the input is started. Then TRs 7, 8 form a push-pull driver interrupting DC conduction to ground and drives and outputs a scanning pulse. Thus, the DC power consumption in a register of the section M is not caused at pulse output and the power is consumed for a limited time only in registers of other stage.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は密着形イメージセンサの信号走査回路に関し、
特に信号走査回路をMO3薄膜トランジスタで形成した
シフトレジスタ走査形の信号走査回路に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a signal scanning circuit for a contact type image sensor.
In particular, the present invention relates to a shift register scanning type signal scanning circuit in which the signal scanning circuit is formed using MO3 thin film transistors.

[従来の技術] 従来、この種のMO5薄膜トランジスタで形成した密着
形イメージセンサの信号走査回路は、第4図に示すよう
にレシオ型EEインバータ(E E)を両方向性の伝送
ゲート(G)を通じ接続してマスタ部(M)とスレーブ
部(S)とする1段のレジスタを縦続接続したN段2相
(φ1φ2)ダイナミックシフトレジスタで構成されて
いた。なお。
[Prior Art] Conventionally, the signal scanning circuit of a contact type image sensor formed using this type of MO5 thin film transistor has been constructed by connecting a ratio type EE inverter (EE) through a bidirectional transmission gate (G), as shown in Fig. 4. It consisted of an N-stage two-phase (φ1φ2) dynamic shift register in which one-stage registers were connected in cascade to form a master section (M) and a slave section (S). In addition.

図においてDIPはレジスタの出力、Qoはレジスタの
出力、DRはスレレープ部Sに接続しているドライバ部
、φIG、はドライバの出力走査パルスIVDDは電源
である。また第5図はレシオ型インバータEEの構成を
示す図である。
In the figure, DIP is the output of the register, Qo is the output of the register, DR is the driver section connected to the slave section S, and φIG is the output scanning pulse IVDD of the driver is the power supply. Further, FIG. 5 is a diagram showing the configuration of a ratio type inverter EE.

[発明が解決しようとする課題] 上述した従来のMO5薄膜トランジスタで形成した密着
形イメージセンサの信号走査回路は、EE型インバータ
(E E)を両方向性の伝送ゲート(G)を通じ接続し
てマスタ部(M)とスレーブ部(S)とする1段のレジ
スタを縦続接続したN段2相(φ1.φ2)ダイナミッ
クシフトレジスタの構成となっているので、電源と接地
間の直流電流導通がN段シフトレジスタ中で走査能動パ
ルスを出力している1個所段のスレーブ回路のみならず
、走査パルスが能動出力されていない(N−1)個所段
でもマスタ回路で生しており、走査パルスの非能動出力
期間での電力損失か著しく大であって電力効率が悪いと
いう問題点がある。
[Problems to be Solved by the Invention] The signal scanning circuit of the contact type image sensor formed using the conventional MO5 thin film transistor described above has a master section that connects an EE type inverter (EE) through a bidirectional transmission gate (G). The structure is an N-stage 2-phase (φ1, φ2) dynamic shift register in which a single-stage register (M) and a slave section (S) are connected in cascade, so that the DC current conduction between the power supply and ground is reduced to In the shift register, not only the slave circuit at one stage outputting the scan active pulse, but also the master circuit at the stage (N-1) where the scan pulse is not actively output, There is a problem in that the power loss during the active output period is extremely large and the power efficiency is poor.

本発明は従来のもののこのような課題を解決し電流効率
の良い密着型イメージセンサの信号走査回路を提供する
ものである。
The present invention provides a signal scanning circuit for a contact type image sensor that solves the problems of the conventional circuit and has good current efficiency.

[課題を解決するための手段] 本発明のMO5薄膜トランジスタで形成した密着形イメ
ージセンサの信号走査回路は、信号走査回路が薄膜で形
成された密着型イメージセンサに於いて、MO5薄膜ト
ランジスタで形成する信号走査回路を、第1のシフトパ
ルスを受ける両方向性の伝送ゲートと電源から接地への
直流導通を1/2動作時間とするレシオ型ダイナミック
インバータを含むマスタ部と、第2のシフトパルスを受
ける両方向性の伝送ゲートとレシオ型EEインバータと
を含むスレーブ部と、スレーブ部のインバータからの反
相クロックを受け直流電流導通か生じないブツシュプル
構成としたドライバ部とを具備する1段のレジスタとを
縦続接続してなるN段2相ダイナミックシフトレジスタ
とで構成される。
[Means for Solving the Problems] A signal scanning circuit of a contact type image sensor formed with an MO5 thin film transistor of the present invention is a signal scanning circuit of a contact type image sensor formed with an MO5 thin film transistor of the present invention. The scanning circuit includes a master section including a bidirectional transmission gate that receives a first shift pulse and a ratio dynamic inverter whose DC conduction time is 1/2 from the power supply to ground, and a bidirectional transmission gate that receives a second shift pulse. A single-stage register is connected in cascade, and includes a slave section including a transmission gate and a ratio type EE inverter, and a driver section that receives an anti-phase clock from the inverter of the slave section and has a push-pull configuration that does not cause direct current conduction. It is composed of an N-stage two-phase dynamic shift register connected to each other.

[実施例] 次に1本発明について図面を参照して説明する。[Example] Next, one embodiment of the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例の密着形イメージセンサの信
号走査回路の一要素を示す構成図、第2図は第1図での
信号走査回路を縦続に接続して得られる密着形イメージ
センサでの全体の構成概念図、第3図は第1図及び第2
図での回路動作におけるクロック信号のタイミングの一
例である。
FIG. 1 is a configuration diagram showing one element of a signal scanning circuit of a contact type image sensor according to an embodiment of the present invention, and FIG. 2 is an image of a contact type image sensor obtained by cascading the signal scanning circuits shown in FIG. 1. A conceptual diagram of the overall configuration of the sensor, Figure 3 is similar to Figures 1 and 2.
It is an example of the timing of the clock signal in the circuit operation in the figure.

本実施例は、光電変換素子(P、)(1<n<N)を転
送ゲート(TG□)と走査パルス(φTG、)により1
個所づつ順次にラインL、とR2間で導通させて、光電
変換信号を読み出すタイプのイメージセンサの信号走査
回路に関し、かつ。
In this example, a photoelectric conversion element (P,) (1<n<N) is transferred to 1 by a transfer gate (TG□) and a scanning pulse (φTG,).
The present invention relates to a signal scanning circuit for an image sensor of a type that reads out a photoelectric conversion signal by sequentially connecting lines L and R2 at each location.

電力損失を低減化するMO8薄膜トランジスタ(以降、
MOSTFTと呼ぶ)で形成するシフトレジスタ走査形
の信号走査回路である。
MO8 thin film transistor (hereinafter referred to as
This is a shift register scanning type signal scanning circuit formed using MOSTFT.

第1図に、密着形イメージセンサの内、光電変換素子(
P、)を含むセンサ要素(R6)と、この要素に含むM
OSTFTである転送ゲート(TG、)と走査パルス(
φTGゎ)を出力する信号走査回路のレジスタ要素(R
,)を示し、更には。
Figure 1 shows the photoelectric conversion element (
P, ) and a sensor element (R6) containing M
The transfer gate (TG, ) which is OSTFT and the scan pulse (
The register element (R
), and furthermore.

レジスタ要素(R6)内の回路要素の構成をも示す。The configuration of circuit elements within the register element (R6) is also shown.

一段のレジスタ(R,)はMOS T F Tから成る
TRI、TR2,TR3を主要素とするマスタ部(M)
とMOSTFTから成るTR4,TR5゜TR6を主要
素とするスレーブ部(S)およびMOSTFTのTR7
,TR8から成る転送ゲート(TG、)を駆動するドラ
イバ部(DR)を具備する。
The first stage register (R,) is a master section (M) whose main elements are TRI, TR2, and TR3, which are made up of MOS T F T.
and MOSTFT, TR4, TR5゜Slave section (S) whose main elements are TR6 and MOSTFT TR7
, TR8.

レジスタ要素(R,)(1<n<N)は外部から共通的
に電源VDDと地気(G)、及び2相のシフトクロック
φ、φ2の供給を受ける。
The register elements (R,) (1<n<N) are commonly supplied with a power supply VDD, a ground voltage (G), and two-phase shift clocks φ and φ2 from the outside.

次に、第1図のセンサ要素(Ee )  (1< n 
<N)を縦続して得られる密着形イメージセンサでの全
体の構成および走査概念を示す第2図と、第1図と第2
図での動作におけるクロック信号のタイミングを示す第
3図をもとにして、動作を説明する。
Next, the sensor element (Ee) (1< n
Fig. 2 shows the overall configuration and scanning concept of a contact type image sensor obtained by cascading images of <N), and Fig. 1 and Fig. 2
The operation will be explained based on FIG. 3 showing the timing of the clock signal in the operation shown in the figure.

なお、動作説明を便宜上NMOS T F Tで回路形
成されているとして説明を行う。PMO5TPTでの回
路形成である場合は、VDDの地気(G)に対する電位
が負のVDDと読み換えることでなされる。
For convenience, the operation will be explained assuming that the circuit is formed of NMOS TFTs. When a circuit is formed using PMO5TPT, the potential of VDD with respect to the earth (G) is read as negative VDD.

スタートパルスSPは先ず最初の走査パルス(φTGI
)を能動にする外部よりのクロックであり、レジスタ走
査(R1)の入力(DI+)をレベルGとする。シフト
クロックφ1がレベルV■であれば両方向性の伝送ゲー
ト(TRI)が導通状態にあり、入力(Dl、)のレベ
ルはTR3のゲートに伝送される。伝送が完了した後に
クロックφ、がレベルGになると、TR3のゲートでの
信号レベルは容jic1でマスタ部に保持される。
The start pulse SP is the first scanning pulse (φTGI
) is an external clock that activates the register scan (R1) input (DI+) to level G. When the shift clock φ1 is at level V■, the bidirectional transmission gate (TRI) is in a conductive state, and the level of the input (Dl,) is transmitted to the gate of TR3. When the clock φ becomes level G after the transmission is completed, the signal level at the gate of TR3 is held at jic1 in the master section.

これと同時にクロックφ2がレベルVDDとなりTR2
が導通となり、マスタ部でのレシオ形インバータが機能
し始めて容量C1での保持レベルに応じてマスタ部出力
レベルが確定され、導通状態にある伝送ゲー)TR4を
通じスレーブ内部に伝達される。
At the same time, clock φ2 becomes level VDD and TR2
becomes conductive, the ratio type inverter in the master section begins to function, and the master section output level is determined according to the level held in the capacitor C1, and is transmitted to the inside of the slave through the transmission gate TR4, which is in a conductive state.

スタートパルスSPのレベルGでの入力信号がレジスタ
R1のマスタ部では反転されたレベル(VDD  VT
)出力となり、スレーブへの伝達となる。
The input signal at the level G of the start pulse SP is inverted in the master section of the register R1 (VDD VT
) becomes the output and is transmitted to the slave.

ここに電位V7はTFTの閾値電圧である。Here, the potential V7 is the threshold voltage of the TFT.

TR5とTR6はTR5をMO5負荷するレシオ形EE
インバータであり、かつ、更にこのインバータの入力と
出力をドライバ部(DR)の一端子がVDDであるTR
7と、一端子が接地(G)であるTR8のそれぞれのゲ
ートに接続し、電源から接地へのDC導通を断つ構成を
とったプツシニブル・ドライバを構成して走査パルスを
駆動出力する。これと同時に、スレーブ部(S)で再度
の反転を受けたレジスタR,の出力Q、とじて出力され
1次段のレジスタRll+lの入力D I 、、、に伝
達される、 マスタ部(M)からスレーブ部(S)への信号転送が完
了した後、クロックφ2はレベルGとなり、TR6のゲ
ートでの信号レベルを容量C2て保持する。スレーブ部
(S)での保持と同時に。
TR5 and TR6 are ratio type EEs that load TR5 with MO5.
It is an inverter, and furthermore, the input and output of this inverter are connected to a TR whose one terminal of the driver section (DR) is VDD.
7 and TR8, one terminal of which is grounded (G), are connected to the respective gates of TR8, and a pushinable driver configured to cut off DC conduction from the power supply to the ground is configured to drive and output scanning pulses. At the same time, the output Q of the register R, which has been inverted again in the slave part (S), is output and transmitted to the input D I of the register Rll+l in the first stage, the master part (M). After the signal transfer from the TR6 to the slave section (S) is completed, the clock φ2 becomes level G, and the signal level at the gate of TR6 is held by the capacitor C2. At the same time as holding in the slave section (S).

マスタ部(M)のレシオ形シンバータのTR2の導通が
止められる。これと同時に、また、マスタ部(M)では
クロックφ1がレベルVDDとなり新たな入力を開始す
る。
The conduction of TR2 of the ratio type symverter of the master section (M) is stopped. At the same time, in the master section (M), the clock φ1 becomes level VDD and a new input starts.

以上の第1図の信号走査回路の一要素の動作をもとにす
れば、第2図の実施例のごとく縦続接続された信号走査
回路にあっては、第3図に示すスタートパルスSPで走
査能動を受けた走査パルスφTGIが、シフトクロック
φ1とφ2によってシフトクロックの1サイクルごとに
、φTGI→φTG2→φTG3・・・→φTGNへと
シフトされて行き、光電変換信号を順次に読み出すこと
は明らかである。
Based on the above operation of one element of the signal scanning circuit shown in FIG. 1, in the signal scanning circuit connected in cascade as in the embodiment shown in FIG. The scanning pulse φTGI that has received the scan activation is shifted by the shift clocks φ1 and φ2 from φTGI → φTG2 → φTG3...→φTGN every cycle of the shift clock, and the photoelectric conversion signals are sequentially read out. it is obvious.

また1以上の動作から電力消費につき以下のことが明ら
かである。すなわち、走査パルス(φTG、)(1<n
<N)を1個所づつ順次に能動にし、充電変換信号を読
み出すイメージセンサの信号走査回路にあっては。
Furthermore, the following is clear regarding power consumption from one or more operations. That is, the scanning pulse (φTG, ) (1<n
<N) in a signal scanning circuit of an image sensor that sequentially activates one location at a time and reads out a charging conversion signal.

■走査能動パルスを出力している一個所段のレジスタ内
で、マスタ部ではレベル(VDD  Vt)の出力であ
り直流電力消費がなく、スレーブ部においてはレベルG
出力のための直流電流導通があると。
■In the one stage register that outputs scanning active pulses, the master section outputs level (VDD Vt) and consumes no DC power, and the slave section outputs level G.
With direct current conduction for output.

■一方他の(N−1)段のレジスタ内においては、マス
タ部ではレベルG出力であるもののTR2の導通がクロ
ックφ2のレベルG期間の遮断で1/2動作時間に制限
されたDc電力消費があること。
■On the other hand, in the other (N-1) stage registers, although the master section outputs level G, the conduction of TR2 is limited to 1/2 the operating time due to the interruption of the level G period of clock φ2. There must be.

スレーブ部では、Dc電力消費がないレベルCVoD 
VT)の出力にある。
In the slave section, level CVoD with no DC power consumption
VT) output.

ことが判る。I understand that.

[発明の効果コ 以上説明したように本発明は、MO8薄膜トランジスタ
で形成できて、 V!EM形イメージセンサのシフトレ
ジスタ形の信号走査回路を、概ね常に走査非能動レベル
Gを出力しているドライバ部にDC電流導通が生じない
プッシュプルのドライバ構成を、また、ドライバ部と同
相のレベルGを出力保持するマスタ部にクロックφ2で
の導通を遮断するレシオ形ダイナミックインバータを具
備することにより、電力消費を従前比的1/4に改善で
きる効果がある。
[Effects of the Invention] As explained above, the present invention can be formed using MO8 thin film transistors and has a V! The shift register type signal scanning circuit of the EM image sensor has a push-pull driver configuration in which DC current does not occur in the driver section, which almost always outputs the scan inactive level G, and also has a push-pull driver configuration that does not cause DC current conduction to the driver section, which outputs the scanning inactive level G at all times. By providing a ratio-type dynamic inverter that cuts off conduction at clock φ2 in the master section that holds G as an output, it is possible to improve power consumption to 1/4 of the conventional ratio.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の密着形イメージセンサの信号走査回路
の一実施例における信号走査回路の1/N段の一要素(
Effi)とレジスタ回路(R,)の回路図、第2図は
第1図での信号走査回路を縦続して得られる密着形イメ
ージセンサでの全体の一例の概念図、第3図は信号走査
回路での回路動作におけるクロック信号のタイミングの
一実施例の図、第4図は、従来例での信号走査回路のレ
ジスタ回路要素図、第5図は第4図におけるEE型イン
バータの構成を示す図である。 記号の説明、R,・・・レジスタ要素、E、・・・セン
サ要素1M・・・マスタ部、S・・・スレーブ部、DR
・・・ドライバ部。 1M1図 い En セッサ#素
FIG. 1 shows an element (1/N stage) of the signal scanning circuit in an embodiment of the signal scanning circuit of the contact type image sensor of the present invention
Effi) and the register circuit (R,), Figure 2 is a conceptual diagram of an example of the entire contact type image sensor obtained by cascading the signal scanning circuits in Figure 1, and Figure 3 is the signal scanning circuit. A diagram of an example of clock signal timing in circuit operation in a circuit, FIG. 4 is a register circuit element diagram of a signal scanning circuit in a conventional example, and FIG. 5 shows a configuration of an EE type inverter in FIG. 4. It is a diagram. Explanation of symbols: R,...Register element, E,...Sensor element 1M...Master section, S...Slave section, DR
...Driver section. 1M1 Figure En Sessa # element

Claims (2)

【特許請求の範囲】[Claims] (1)信号走査回路が薄膜で形成された密着型イメージ
センサに於いて、 MOS薄膜トランジスタで形成する信号走査回路を、第
1のシフトパルスを受ける両方向性の伝送ゲートと電源
から接地への直流導通を1/2動作時間とするレシオ型
ダイナミックインバータを含むマスタ部と、第2のシフ
トパルスを受ける両方向性の伝送ゲートとレシオ型EE
インバータとを含むスレーブ部と、スレーブ部のインバ
ータからの反相クロックを受け直流電流導通が生じない
プッシュプル構成としたドライバ部とを具備する1段の
レジスタを縦続接続してなるN段2相ダイナミックシフ
トレジスタで構成したことを特徴とする密着形イメージ
センサの信号走査回路。
(1) In a contact image sensor in which the signal scanning circuit is formed of a thin film, the signal scanning circuit formed of a MOS thin film transistor is connected to a bidirectional transmission gate that receives the first shift pulse and DC conduction from the power supply to the ground. a master section including a ratio type dynamic inverter with a 1/2 operation time, a bidirectional transmission gate receiving a second shift pulse, and a ratio type EE.
An N-stage 2-phase structure formed by cascading one stage of registers each including a slave part including an inverter and a driver part having a push-pull configuration that receives an anti-phase clock from the inverter of the slave part and has a push-pull configuration in which no direct current conduction occurs. A signal scanning circuit for a contact image sensor characterized by being configured with a dynamic shift register.
(2)第1と第2のシフトクロックパルスが相反パルス
であることを特徴とする請求項第(1)項記載の密着形
イメージセンサの信号走査回路。
(2) The signal scanning circuit for a contact image sensor according to claim (1), wherein the first and second shift clock pulses are opposite pulses.
JP2307287A 1990-11-15 1990-11-15 Signal scanning circuit for close contact image sensor Pending JPH04180454A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2307287A JPH04180454A (en) 1990-11-15 1990-11-15 Signal scanning circuit for close contact image sensor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2307287A JPH04180454A (en) 1990-11-15 1990-11-15 Signal scanning circuit for close contact image sensor

Publications (1)

Publication Number Publication Date
JPH04180454A true JPH04180454A (en) 1992-06-26

Family

ID=17967318

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2307287A Pending JPH04180454A (en) 1990-11-15 1990-11-15 Signal scanning circuit for close contact image sensor

Country Status (1)

Country Link
JP (1) JPH04180454A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7522317B2 (en) 2000-12-20 2009-04-21 Seiko Epson Corporation Image reading device
US10847568B2 (en) 2018-02-15 2020-11-24 Tianma Japan, Ltd. Image sensor and method of driving image sensor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7522317B2 (en) 2000-12-20 2009-04-21 Seiko Epson Corporation Image reading device
US10847568B2 (en) 2018-02-15 2020-11-24 Tianma Japan, Ltd. Image sensor and method of driving image sensor

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