TWI385626B - Shift register and liquid crystal display - Google Patents

Description

Displacement register and liquid crystal display

The invention relates to a displacement register and a liquid crystal display using the displacement register.

At present, Thin Film Transistor (TFT) liquid crystal displays have gradually become standard output devices for various digital products. However, it is necessary to design an appropriate driving circuit to ensure stable operation.

Generally, the liquid crystal display driving circuit includes a data driving circuit and a scan driving circuit. The data driving circuit is used to control the display luminance of each pixel unit, and the scan driving circuit is used to control the on and off of the thin film transistor. Both drive circuits use a displacement register as the core circuit unit. Generally, the displacement register is formed by connecting a plurality of displacement temporary storage units in series, and the output signal of the previous displacement temporary storage unit is an input signal of the latter displacement temporary storage unit.

Please refer to FIG. 1 , which is a circuit diagram of a displacement temporary storage unit of a prior art displacement register. The shift register unit 100 includes a first clock inverting circuit 110, a commutation circuit 120, and a second clock inverting circuit 130. Each circuit of the displacement temporary storage unit 100 is composed of a PMOS (P-channel Metal-Oxide Semiconductor) type transistor, and each PMOS type transistor includes a gate and a source. A bungee.

The first clocked inverter circuit 110 includes a first PMOS transistor P1, a second transistor P2, a third transistor P3, a fourth transistor P4, a first output terminal V1, and a second output. End V2. The gate of the first transistor P1 receives the output signal VS of a displacement temporary storage unit before the displacement temporary storage unit 100, and the source receives the high level signal VDD from the external circuit, and the drain thereof is connected to the second power The source of the crystal P2. The gate of the second transistor P2 and its drain receive a low level signal VSS from an external circuit. The gates of the third transistor P3 and the fourth transistor P4 receive inverted clock signals from an external circuit The drains of the two are respectively used as the first output terminal V1 and the second output terminal V2 of the first clocked inverter circuit 110, and the source of the third transistor P3 is connected to the drain of the first transistor P1. The source of the fourth transistor P4 is connected to the gate of the first transistor P1.

The converter circuit 120 includes a fifth transistor P5, a sixth transistor P6, and a signal output terminal V. The gate of the fifth transistor P5 is connected to the first output terminal V1, the source thereof receives the high level signal VDD from the external circuit, and the drain thereof is connected to the source of the sixth transistor P6. The gate of the sixth transistor P6 is connected to the second output terminal V2, and the drain thereof receives the low level signal VSS from the external circuit, and the source thereof is the signal output terminal V of the displacement temporary storage unit 100.

The second clock inverting circuit 130 includes a seventh transistor P7, an eighth transistor P8, a ninth transistor P9, and a tenth transistor P10. The gate of the seventh transistor P7 is connected to the signal output terminal V, the source thereof receives the high level signal VDD from the external circuit, and the drain thereof is connected to the source of the eighth transistor P8. The gate of the eighth transistor P8 and its drain receive a low level signal VSS from an external circuit. The source of the ninth transistor P9 is connected to the first output terminal V1, the gate thereof receives the clock signal TS from the external circuit, and the drain thereof is connected to the drain of the seventh transistor P7. The gate of the tenth transistor receives the clock signal TS of the external circuit, and the source thereof is connected to the second output end V2, whose drain is connected to the signal output terminal V.

Please refer to FIG. 2 together, which is a working sequence diagram of the displacement temporary storage unit 100. During the t1 period, the output signal VS of the previous displacement temporary storage unit is changed from a high level to a low level, and the inverted clock signal is inverted. When the low level jumps to the high level, the third transistor P3 and the fourth transistor P4 are turned off, and the first clock inverting circuit 110 is turned off. The clock signal TS is changed from a high level to a low level, so that the ninth transistor P9 and the tenth transistor P10 are turned on, and the second clock inverting circuit 130 is turned on, and the signal output terminal V is turned on. The sixth state of the initial state is passed through the tenth transistor P10, and the sixth transistor P6 is turned off, and the low level of the output of the eighth transistor P8 is passed through the ninth transistor P9 to make the fifth transistor P5. Turning on, and then outputting the high level signal VDD of the source to the signal output terminal V, the signal output terminal V maintains a high level output.

The inverted clock signal during the t2 period When the high level jumps to the low level, the third transistor P3 and the fourth transistor P4 are turned on, thereby turning on the first clock inverting circuit 110. When the clock signal TS is changed from a low level to a high level, the ninth transistor P9 and the tenth transistor P10 are turned off, and the second clocked inverter circuit 130 is turned off. When the input signal VS is changed from a high level to a low level, the first transistor P1 is turned on, and the high level VDD of the source thereof is turned off by the third transistor P3 through the third transistor P5, and the The low level of the input signal VS is turned on by the fourth transistor P4 to turn on the sixth transistor P6, so that the signal output terminal V outputs a low level.

The inverted clock signal during the t3 period When the low level jumps to the high level, the third transistor P3 and the fourth transistor P4 are turned off, and the first clock inverting circuit 110 is turned off. The clock signal TS transitions from a high level to a low level to turn on the ninth transistor P9 and the tenth transistor P10, thereby turning on the second clock inverting circuit 130. The low level of the signal output terminal V turns on the seventh transistor P7, and the high level of the source thereof is turned off by the ninth transistor P9 to the fifth transistor P5. At the same time, the low level of the signal output terminal V is also turned on by the tenth transistor P10 to turn on the sixth transistor P6, and the lower level of the sixth transistor P6 keeps the signal output terminal V low. Output.

The inverted clock signal during the t4 period When the high level jumps to the low level, the third transistor P3 and the fourth transistor P4 are turned on, thereby turning on the first clock inverting circuit 110. The clock signal TS transitions from a low level to a high level to turn off the ninth transistor P9 and the tenth transistor P10, thereby turning off the second clock inverting circuit 120. The high level of the input signal VS is turned off by the fourth transistor P4, and the second low level of the second transistor P2 is turned on by the third transistor P3. The high level of the source is output to the signal output terminal V, so that the output of the signal output terminal V changes from a low level to a high level.

It can be seen from the above working sequence that when the input temporary signal is transmitted to the subsequent displacement temporary storage unit, the externally provided clock signal TS and inverted clock signal are simultaneously received. The high level signal VGH and the low level signal VGL, so that the circuit layout of the displacement temporary storage unit 100 is complicated. Therefore, the circuit layout of the liquid crystal display using the displacement temporary storage unit 100 is also complicated.

In view of this, it is necessary to provide a displacement register with a simple circuit structure layout.

In addition, it is also necessary to provide a liquid crystal display with a simple circuit layout.

A displacement register includes a plurality of displacement temporary storage units, each of the displacement temporary storage units is controlled by two mutually inverted clock signals and a low level signal, and each of the displacement temporary storage units includes a signal output circuit, a signal input circuit, a first logic circuit and a second logic circuit; wherein the signal input circuit controls the first logic circuit to output a low level signal or a clock signal, and simultaneously controls the signal output circuit to output a clock signal; The second logic circuit controls the signal output circuit to output a low level signal.

A liquid crystal display comprising a liquid crystal display panel, a data driving circuit and a scan driving circuit, wherein the data driving circuit provides a data signal for the liquid crystal display panel, the scan driving circuit provides a scanning signal for the liquid crystal display panel, and the data driving The circuit and the scan driving circuit respectively comprise a shift register for controlling the output timing of the data signal and the scan signal, wherein the shift register comprises a plurality of shift temporary storage units, and each shift temporary storage unit is subjected to two mutually inverted clocks a signal and a low level signal control, each of the displacement temporary storage units includes a signal output circuit, a signal input circuit, a first logic circuit and a second logic circuit; wherein the signal input circuit controls the first The logic circuit outputs a low level signal or a clock signal, and controls the signal output circuit to output a clock signal; the second logic circuit controls the signal output circuit to output a low level signal.

Compared with the prior art, each displacement temporary storage unit of the displacement register only needs to receive the externally provided first clock signal, the second clock signal and the low level when outputting the input signal to the subsequent displacement temporary storage unit. The signal does not need to receive a high level signal, so there is no need to layout in the circuit structure of the displacement temporary storage unit. The circuit that transmits the high level signal, the circuit layout of the displacement register is simple.

Compared with the prior art, each displacement temporary storage unit of the displacement register of the liquid crystal display only needs to receive the externally provided first clock signal and second clock signal when outputting the input signal to the subsequent displacement temporary storage unit. And the low-level signal does not need to receive a high-level signal separately, so that the circuit structure of the displacement temporary storage unit does not need to lay out a line for transmitting a high-level signal, so the circuit layout structure of the displacement register is simple.

Please refer to FIG. 3, which is a structural frame diagram of a preferred embodiment of the displacement register of the present invention. The displacement register 20 includes a plurality of displacement temporary storage units having the same circuit structure. The plurality of displacement temporary storage units are sequentially connected in series, and each displacement temporary storage unit simultaneously receives the first clock signal CLK provided by the external circuit, and the first The clock signal is inverted by the second clock signal CLKB and the low level signal VGL. Each displacement temporary storage unit is composed of a plurality of NMOS type transistors, and each NMOS type transistor includes a gate, a source and a drain. The connection relationship between the displacement register 20 is described by taking the first displacement temporary storage unit 21 and the second displacement temporary storage unit 22 adjacent thereto as an example. The first displacement temporary storage unit 21 includes an input signal terminal STV and a The first output terminal VOUT1 and the second output terminal VOUT2. The second shift register unit 22 includes a signal input terminal VIN, a first output terminal VO1 and a second output terminal VO2. The output signal of the first output terminal VOUT1 of the first displacement temporary storage unit 21 is the input signal of the signal input terminal VIN of the second displacement temporary storage unit 22; and the first output terminal VO1 of the second displacement temporary storage unit 22 And the second output terminal VO2 can output the signal The number is fed back to the first displacement temporary storage unit 21. The second output terminal VOUT2 of the first displacement temporary storage unit 21 and the second output terminal VO2 of the second displacement temporary storage unit 22 are external signals (not shown) to provide signals.

Referring to FIG. 4 together, a circuit diagram of the first shift register unit 21 and the second shift register unit 22 shown in FIG. 3 is connected. The first shift register unit 21 includes a signal input circuit 211, a first logic circuit 213, a second logic circuit 215, a signal output circuit 217, a first node X1 and a second node X2. The first node X1 is formed by the intersection of the signal input circuit 211, the logic circuit 213 and the signal output circuit 217, and the second node X2 is formed by the intersection of the first logic circuit 213 and the second logic circuit 215.

The signal input circuit 211 includes a first transistor M1 and a second transistor M2. The gate of the first transistor M1 receives the second clock signal CLKB provided by the external circuit, the drain of the first transistor M1 is connected to the drain of the second transistor M2, and the source thereof is combined with the source of the second transistor M2. Connected to the first node X1. The gate of the second transistor M2 serves as the input signal terminal STV of the first shift register unit 21 to receive an externally supplied input signal.

The first logic circuit 213 includes a third transistor M3, a fourth transistor M4, and a fifth transistor M5. The gate of the third transistor M3 is connected to the first node X1, the source thereof receives an externally supplied low level signal VGL, and the drain thereof is connected to the sources of the fourth transistor M4 and the fifth transistor M5. The gate and the drain of the fourth transistor M4 both receive an externally provided second clock signal CLKB. The gate of the fifth transistor M5 receives the externally provided first clock signal CLK, and the drain thereof is connected to the first output terminal VO1 of the second displacement register unit 22.

The second logic circuit 215 includes a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The gate of the sixth transistor M6 is connected to the second node X2 together with the gates of the seventh transistor M7 and the eighth transistor M8, and the source of the sixth transistor M6 is externally provided low. The level signal VGL is connected to the first node X1. The sources of the seventh transistor M7 and the eighth transistor M8 each receive an externally supplied low level signal VGL, and the drains of the two are connected to the signal output circuit 217.

The signal output circuit 217 includes a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12. The ninth transistor M9 and the tenth transistor M10 are both the clock transistors of the signal output circuit 217, and the gates of the ninth transistor M9 and the tenth transistor M10 are connected to the first node X1. The drains of the two are connected to the first clock signal CLK, and the sources of the two are respectively connected to the drains of the seventh transistor M7 and the eighth transistor M8 of the second logic circuit 215, respectively. The first output terminal VOUT1 and the second output terminal VOUT2 of the first displacement temporary storage unit 21. The output signal of the first output terminal VOUT1 is output to the signal input terminal VIN of the second displacement temporary storage unit 22. The second output terminal VOUT2 outputs a signal to an external circuit. The eleventh transistor M11 is used as a clear transistor, and the gate thereof receives the signal outputted by the second signal output terminal VO2 of the second displacement temporary storage unit 22, and the source thereof receives the externally supplied low level signal VGL. The drain is connected to the second output terminal VOUT2. The twelfth transistor M12 functions as a voltage stabilizing transistor, and the gate receives the second clock signal CLKB, the source receives the external low level signal VGL, and the drain is connected to the second output terminal VOUT2.

The second displacement temporary storage unit 22 is different from the first displacement temporary storage unit 21 in that the second displacement temporary storage unit 22 receives the output signal of the first output terminal VOUT1 of the first displacement temporary storage unit 21 as a signal input. The input signal of the terminal VIN, the first output terminal VO1 is connected to the drain of the fifth transistor M5 of the first displacement temporary storage unit 21; the gates of the first transistor T1 and the twelfth transistor T12 are externally received. The first clock signal CLK is provided; the gate and the source of the fourth transistor T4, and the drains of the ninth transistor T9 and the tenth transistor T10 receive the second clock signal CLKB provided by the external circuit.

Please refer to FIG. 5 together, which is an operation timing diagram of the first displacement temporary storage unit 21 and the second displacement temporary storage unit 22. During the period of t1, the first clock signal CLK received by the first displacement temporary storage unit 21 maintains the low level signal VGL, and the second clock signal CLKB maintains the high level signal VGH; the input signal received by the signal receiving end STV is The low level signal VGL is followed by the high level signal VGH.

When the signal received by the signal receiving end STV of the first displacement temporary storage unit 21 is the low level signal VGL, the first transistor M1 of the signal input circuit 211 is turned on, and the second transistor M2 is turned off, the signal input circuit is turned on. 211 outputs a low level signal VGL to the first node X1, and the ninth transistor M9, the tenth transistor M10, and the third transistor M3 connected to the first node X1 are turned off. At the same time, the fourth transistor M4 of the first logic circuit 213 is turned on by the second clock signal CLKB, and outputs a second clock signal CLKB of the high level signal VGH to the second node X2. The second logic circuit 215 The sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are turned on, and the first output terminal VOUT1 of the signal output circuit 217 outputs a low level signal VGL to the first a second shift register unit 22, the second output terminal VOUT2 outputs a low level signal VGL to an external circuit, and the twelfth transistor M12 of the signal output circuit 217 is turned on by receiving the second clock signal CLKB, The second output terminal VOUT2 keeps outputting the low level signal VGL to the external circuit.

Then, after the signal received by the signal receiving end STV of the first displacement temporary storage unit 21 is changed from the low level signal VGL to the high level signal VGH, the second transistor M2 is turned on, and the signal input circuit 211 outputs the high. The ninth transistor M9 and the tenth transistor M10 are turned on, and the first output terminal VOUT1 and the second output terminal VOUT2 output the first clock signal CLK, that is, the level signal VGH to the first node X1. The first output terminal VOUT maintains the output low level signal VGL to the second displacement temporary storage unit 22, and the second output terminal VOUT2 maintains the output low level signal VGL to the external circuit. At the same time, the third transistor M3 of the first logic circuit 213 is turned on to pull down the signal output by the fourth transistor M4, and the first logic circuit 213 outputs a low level signal VGL to the second node X2, the second The sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 of the logic circuit 215 are turned off, and the first output terminal VOUT1 and the second output terminal VOUT2 output the first clock signal CLK without affecting.

During the period of t1, the first clock signal CLK received by the second displacement temporary storage unit 22 is a low level VGL, and the second clock signal CLKB is a high level signal VGH, and the first displacement of the signal receiving end VIN is temporarily stored. The output signal of unit 21 is always a low level signal VGL. Therefore, the first transistor T1 and the second transistor T2 of the second displacement temporary storage unit 22 are both kept in an off state, and the ninth transistor T9 and the tenth transistor T10 are also turned off, and the first output terminal VO1 is also turned off. And the second output terminal VO2 maintains the output low level signal VGL. At the same time, the third transistor T3 is also turned off, and the fourth transistor T4 is turned on by receiving the second clock signal CLKB, and the second clock signal CLKB, which is the high level signal VGH, is output to the sixth transistor T6. a gate of the seventh transistor T7 and the eighth transistor T8, such that the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 receive the external low level signal VGL to the first output terminal VO1 And the second output terminal VO2, ensuring that the low level signal VGL outputted by the first output terminal VO1 and the second output terminal VO2 is not affected by the second clock signal of the ninth transistor T9 and the tenth transistor T10 The effect of CLKB.

During the time period t2, the first clock signal CLK received by the first displacement temporary storage unit 21 maintains the high level signal VGH, and the second clock signal CLKB maintains the low level signal VGL. The input signal received by the STV of the signal receiving end is firstly a high level signal VGH, and then a low level signal VGL.

When the signal received by the signal receiving end STV of the first displacement temporary storage unit 21 is the high level signal VGH, the second transistor M2 of the signal input circuit 211 is turned on, and the high level signal VGH is outputted to the first node. X1. The ninth transistor M9 and the tenth transistor M10 connected to the first node X1 are turned on, and the first output terminal VOUT1 and the second output terminal VOUT2 of the signal output circuit 217 output the first clock signal CLK, that is, the The first signal output terminal VOUT1 outputs a high level signal VGH to the second displacement temporary storage unit 22, and the second output terminal VOUT2 outputs a high level signal VGH to an external circuit. At the same time, the third transistor M3 is turned on to receive the low level signal VGL, and the second node X2 is still at a low level, and the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are kept off.

After the signal received by the signal receiving end STV of the first displacement temporary storage unit 21 is converted from the high level signal VGH to the low level signal VGL, the second transistor M2 is turned off, and the first transistor M1 receives the first When the two clock signals CLKB remain off, the signal input circuit 211 has no signal output, the first node X1 maintains a high level, and the signal output circuit 217 maintains the output of the first clock signal CLK.

During the time period t2, the first clock signal CLK received by the second displacement temporary storage unit 22 maintains the high level signal VGH, the second clock signal CLKB maintains the low level signal VGL, and the signal receiving end VIN receives the first displacement. The output signal of the temporary storage unit 21 is always the high level signal VGH. Therefore, the first transistor T1 and the second transistor T2 of the second displacement temporary storage unit 22 are turned on, and output a high level signal VGH to the ninth transistor T9 and the tenth transistor T10, and the second displacement is temporarily suspended. The first output terminal VO1 and the second output terminal VO2 of the memory unit 22 both output the second clock signal CLKB, that is, output a low level signal VGL. The twelfth transistor T12 receives the first clock signal CLK and turns on the output low level to ensure that the second output terminal VO2 outputs the low level signal VGL to the external circuit. At the same time, the high-level signal VGH outputted by the first transistor T1 and the second transistor T2 turns on the third transistor T3, and the third transistor T3 outputs a low-level signal to turn off the sixth transistor T6, Seven transistor T7 and eighth transistor T8.

During the period of t3, the first clock signal CLK received by the first shift register unit 21 maintains the low level signal VGL, and the second clock signal CLKB maintains the high level signal VGH; the input signal received by the signal receiving end STV is always Low level signal VGL. Then the second electric crystal of the first displacement temporary storage unit 21 The body M2 remains off, the first transistor M1 outputs a low level signal VGL, the first node X1 is at a low level, and the ninth transistor M9 and the tenth transistor M10 are turned off. At the same time, the third transistor M3 of the first logic circuit 213 is turned off, the second transistor M4 receives and outputs the second clock signal CLKB, and the second node X2 is at a high level, the sixth transistor M6, The seventh transistor M7 and the eighth transistor M8 are turned on to rapidly lower the potential of the first output terminal VOUT1 and the second output terminal VOUT2 of the signal output circuit 217, and the first output terminal VOUT1 of the signal output circuit 217 and the first The two output terminals VOUT2 output a low level signal VGL to the second displacement temporary storage unit 22, and the second output terminal VOUT2 outputs a low level signal VGH to an external circuit.

During the time period t3, the first clock signal CLK received by the second displacement temporary storage unit 22 maintains the low level signal VGL, and the second clock signal CLKB maintains the high level signal VGH. The output signal of the signal receiving terminal VIN receiving the first displacement temporary storage unit 21 is always the low level signal VGL. Therefore, the first transistor T1 and the second transistor T2 of the second displacement temporary storage unit 22 are turned off, and the sources of the first transistor T1 and the second transistor T2 are kept at a high level, and the ninth transistor T9 The tenth transistor T10 is kept in an on state, and the first output terminal VO1 and the second output terminal VO2 output the second clock signal CLKB. At the same time, the third transistor T3 is also in an on state, and receives a low level signal to turn off the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8. Therefore, the first output terminal VO1 outputs a high level signal to the subsequent stage displacement register unit (not labeled), and outputs a high level signal VGH to the drain of the fifth transistor of the first displacement temporary storage unit 21, Since the fifth transistor M5 of the first shift register unit 21 receives the second clock signal CLKB, the second bit The high-level signal VGH outputted from the first output terminal VO1 of the temporary storage unit 2 turns on the transistors of the second logic circuit 215 of the first displacement temporary storage unit 21 to perform a clearing operation. The second output terminal VO2 of the second displacement temporary storage unit 22 outputs a high level signal VGH to the external circuit, and simultaneously outputs a high level signal VGH to the gate of the eleventh transistor M11 of the first displacement temporary storage unit 21. The eleventh transistor M11 is turned on to output a low level signal VGL, and the output of the second output terminal VOUT2 of the first displacement temporary storage unit 21 is maintained together with the eighth transistor M8 and the twelfth transistor M12. Level signal VGL to external circuit.

After the t3 time period, the signal receiving end STV of the first displacement temporary storage unit 21 maintains receiving the low level signal VGL, and the received first clock signal CLK and the second clock signal CLKB are still mutually inverted and periodically changed. . However, the receiving terminal STV maintains receiving the low level signal VGL, and the signal outputted by the signal input circuit 211 is only a low level signal, the first node X1 is kept at a low level, and the ninth transistor M9 and the first The ten transistor M10 continues to be turned off, and the first output terminal VOUT1 and the second output terminal VOUT2 maintain the output low level signal VGL. The twelfth transistor M12 receives the second clock signal CLKB periodically to ensure that the signal output by the second output terminal VOUT2 is not connected to the first clock of the ninth transistor M9 and the tenth transistor M10. The effect of the periodic change of the signal CLK smoothly outputs the low-level signal VGL to the external circuit.

After the t3 time period, the signal receiving end VIN of the second displacement temporary storage unit 22 receives the low level signal VGL outputted by the first displacement temporary storage unit 21, and receives the first clock signal CLK and the second clock. Signal CLKB Periodically change. The second transistor T2 is turned off because the signal receiving terminal VIN receives the low level signal VGL outputted by the first displacement temporary storage unit 21, and the first transistor T1 outputs a low level signal VGL to cut off the ninth power. The second clock signal CLKB is no longer output through the first output terminal VO1 and the second output terminal VO2, and the twelfth transistor T12 receives the first clock signal CLK. The second output terminal VO2 outputs a low level signal VGL. At the same time, the rear stage displacement register unit feedback signal turns on the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8, so that the first output terminal VO1 outputs the low level signal VGL. Therefore, after the t3 period, the second displacement temporary storage unit 22 maintains the output low level signal VGL.

Compared with the prior art, when the first shift register unit 21 of the present invention transmits the signal input by the signal input terminal STV to the second shift register unit 22, it only needs to receive the externally provided first clock signal CLK, The second clock signal CLKB and the low level signal VGL, so that the shift register 20 only needs to lay out the circuit for transmitting the first clock signal CLK, the second clock signal CLKB and the low level signal VGL, without layout The high level signal is transmitted to the circuit, so that the circuit layout of the shift register 20 is simple.

The second displacement temporary storage unit 22 is turned on when the ninth and tenth transistors M9 and M10 of the first displacement temporary storage unit 21 are turned on to output the first clock signal CLK in the t2 time period. The ninth and tenth transistors T9 and T10 are turned on, and output the second clock signal CLKB. Since the first clock signal CLK is inverted from the signal of the second clock signal CLKB, the first shift register unit 21 The signals output by the second displacement temporary storage unit 22 have no overlap. In addition, when the signal output by the second displacement temporary storage unit 22 is a high level signal VGH, the first shift register unit 21 can be cleared by the second logic circuit 215, and the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 are turned on to quickly pull down the The source potentials of the ninth transistor M9 and the tenth transistor M10 of the first displacement register unit ensure that the first output terminal VOUT1 and the second output terminal VOUT2 rapidly output the low level signal VGL.

In addition, the first clock signal CLK of the output of the ninth transistor M9 of the first displacement register unit 21 and the output of the tenth transistor M10 is converted from the high level signal VGH to the low level signal VGL, the first output. When the output signal of the terminal VOUT1 and the second output terminal VOUT2 is converted to the low level signal VGL by the high level signal VGH, the twelfth transistor M12 receives the second clock signal CLKB to be quickly turned on to output a low level signal. VGL to the second output terminal VOUT2, so that the first displacement temporary storage unit 21 quickly outputs the low level signal VGL.

Please refer to FIG. 6, which is a structural diagram of a liquid crystal display using the displacement register 20 shown in FIG. The liquid crystal display 30 includes a liquid crystal display panel 31, a data driving circuit 32, and a scan driving circuit 33. The liquid crystal display panel 31 includes an upper substrate (not shown), a lower substrate (not shown), and a liquid crystal layer (not shown) sandwiched between the upper substrate and the lower substrate, and the liquid crystal layer is adjacent to the lower substrate. A thin film transistor array (not shown) for controlling the twisting state of the liquid crystal molecules is disposed on one side. The scan driving circuit 33 outputs a scan signal to control the on and off states of the thin film transistor matrix of the liquid crystal display panel 31. The data driving circuit 32 outputs a data signal to control the liquid crystal display panel 31 to display a screen change. The scan driving circuit 33 and the data driving circuit 32 both control the output timing of the scanning signal and the data signal by using the shift register 20, thereby controlling The display of the liquid crystal display panel 31 is made. The displacement register 20 can be formed in the same process as the thin film transistor array of the liquid crystal display 30.

Compared with the prior art, the liquid crystal display 30 uses the first displacement temporary storage unit 21 of the displacement register 20 to transmit the signal input from the signal input terminal STV to the second displacement temporary storage unit 22, and only needs to receive the external Providing the first clock signal CLK, the second clock signal CLKB, and the low level signal VGL, so that the shift register 20 only needs to layout and transmit the first clock signal CLK, the second clock signal CLKB, and the low level signal. The circuit of VGL can be used, and no high-level signal is transmitted to the circuit, so that the circuit layout of the shift register 20 is simple. Therefore, the circuit layout structure of the liquid crystal display 30 of the displacement register 20 is also simple.

In addition, since there is no signal overlap phenomenon at the output of each stage of the displacement register unit of the displacement register 20, the liquid crystal display 30 using the displacement register 20 as the scan driving circuit 32 and the data driving circuit 33 is in the column. When scanning or column scanning, the output scan signal and data signal will not cause signal interference, thus avoiding chromatic aberration on the display screen.

In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above-mentioned embodiments are merely preferred embodiments of the present invention, and the scope of the present invention is not limited to the above-described embodiments, and those skilled in the art will be able to make equivalent modifications or variations in accordance with the spirit of the present invention. It should be covered by the following patent application.

20‧‧‧Displacement register

211‧‧‧Signal input circuit

213‧‧‧First logic circuit

215‧‧‧Second logic circuit

217‧‧‧Signal output circuit

STV, VIN‧‧‧ signal input

M1, T1‧‧‧ first transistor

M2, T2‧‧‧ second transistor

M3, T3‧‧‧ third transistor

M4, T4‧‧‧ fourth transistor

M5, T5‧‧‧ fifth transistor

M6, T6‧‧‧ sixth transistor

M7, T7‧‧‧ seventh transistor

M8, T8‧‧‧ eighth transistor

M9, T9‧‧‧ ninth transistor

M10, T10‧‧‧10th transistor

M11, T11‧‧‧ eleventh crystal

M12, T12‧‧‧ twelfth transistor

VGH‧‧‧ high level signal

VGL‧‧‧ low level signal

CLK‧‧‧ first clock signal

CLKB‧‧‧second clock signal

X1‧‧‧ first node

X2‧‧‧ second node

30‧‧‧LCD display

31‧‧‧LCD panel

32‧‧‧Scan drive circuit

33‧‧‧Data Drive Circuit

VOUTI, VO1‧‧‧ first output

VOUT2, VO2‧‧‧ second output

21‧‧‧First Displacement Unit

22‧‧‧Second displacement temporary storage unit

1 is a circuit diagram of a displacement temporary storage unit of a prior art shift register.

FIG. 2 is a timing chart of the operation of the displacement temporary storage unit shown in FIG. 1.

3 is a structural block diagram of a preferred embodiment of the displacement register of the present invention.

4 is a circuit diagram of the first shift register unit and the second shift register unit shown in FIG.

FIG. 5 is a timing chart showing the operation of the first displacement temporary storage unit and the second displacement temporary storage unit shown in FIG. 4.

FIG. 6 is a schematic structural view of a liquid crystal display to which the displacement register shown in FIG. 3 is applied.

20‧‧‧Displacement register

211‧‧‧Signal input circuit

213‧‧‧First logic circuit

215‧‧‧Second logic circuit

217‧‧‧Signal output circuit

STV, VIN‧‧‧ signal input

M1, T1‧‧‧ first transistor

M2, T2‧‧‧ second transistor

M3, T3‧‧‧ third transistor

M4, T4‧‧‧ fourth transistor

M5, T5‧‧‧ fifth transistor

M6, T6‧‧‧ sixth transistor

M7, T7‧‧‧ seventh transistor

M8, T8‧‧‧ eighth transistor

M9, T9‧‧‧ ninth transistor

M10, T10‧‧‧10th transistor

M11, T11‧‧‧ eleventh crystal

M12, T12‧‧‧ twelfth transistor

VGH‧‧‧ high level signal

VGL‧‧‧ low level signal

CLK‧‧‧ first clock signal

CLKB‧‧‧second clock signal

X1‧‧‧ first node

X2‧‧‧ second node

VOUT1, VO1‧‧‧ first output

VOUT2, VO2‧‧‧ second output

21‧‧‧First Displacement Unit

22‧‧‧Second displacement temporary storage unit

Claims (16)

A displacement register includes a plurality of displacement temporary storage units, each of the displacement temporary storage units is controlled by two mutually inverted clock signals and a low level signal, and each of the displacement temporary storage units includes a signal output circuit, a signal input circuit, a first logic circuit and a second logic circuit; wherein the signal input circuit controls the first logic circuit to output a low level signal or a clock signal, and simultaneously controls the signal output circuit to output a clock signal; The second logic circuit controls the signal output circuit to output a low level signal; the two inverted clock signals are respectively a first clock signal and a second clock signal; the first logic circuit and the second logic circuit meet to form a second node; And the first logic circuit includes a fifth transistor and receives an externally provided first clock signal, the gate of the fifth transistor receives an externally provided first clock signal, and a source thereof is coupled to the second node, The drain is connected to the latter displacement register unit. The displacement register according to claim 1, wherein the displacement temporary storage unit is composed of a plurality of NMOS type transistors. The shift register of claim 2, wherein the signal input circuit, the first logic circuit and the signal output circuit meet to form a first node. The shift register according to claim 3, wherein the signal input circuit comprises a first transistor and a second transistor, and the gate of the first transistor receives the second clock provided by the external circuit. The signal has a drain connected to the drain of the second transistor, and a source connected to the source of the second transistor to the first node. The displacement register of claim 1, wherein the first logic circuit further comprises a third transistor and a fourth transistor; the gate of the third transistor is connected to the first node, The source receives the externally supplied low level signal, and the drain is connected to the source of the fourth transistor; the gate and the drain of the fourth transistor both receive the externally provided second clock signal. The displacement register of claim 1, wherein the second logic circuit comprises a sixth transistor, a seventh transistor and an eighth transistor; and the gate of the sixth transistor The seventh transistor and the gate of the eighth transistor are connected to the second node, and the source of the sixth transistor receives an externally provided low level signal, the drain of which is connected to the first node; The sources of the seventh transistor and the eighth transistor each receive an externally supplied low level signal, and the drains of the two are connected to the signal output circuit. The shift register of the sixth aspect of the invention, wherein the clock transistor of the signal output circuit comprises a ninth transistor and a tenth transistor, the ninth transistor and the tenth transistor The gates are both connected to the first node, and the drains of the two receive the first clock signal provided externally, and the sources of the two are respectively connected with the seventh transistor and the eighth transistor of the second logic circuit. The poles are connected to respectively output signals to the subsequent shift register unit and the output signals to the external circuit. The shift register of claim 7, wherein the signal output circuit further comprises a clearing transistor and a voltage stabilizing transistor, wherein the clearing transistor comprises an eleventh transistor, the gate The pole receives the output signal of the rear displacement temporary storage unit, the source receives the externally provided low level signal, and the drain is connected to the source of the tenth transistor; the voltage stabilizing transistor includes A twelfth transistor, the gate of the twelfth transistor receives an externally provided second clock signal, the source of which receives an external low level signal, and the drain of which is coupled to the source of the tenth transistor. A liquid crystal display comprising a liquid crystal display panel, a data driving circuit and a scan driving circuit, wherein the data driving circuit provides a data signal for the liquid crystal display panel, the scan driving circuit provides a scanning signal for the liquid crystal display panel, and the data driving The circuit and the scan driving circuit respectively comprise a shift register for controlling the output timing of the data signal and the scan signal, the shift register comprises a plurality of displacement temporary storage units, and each of the displacement temporary storage units is subjected to two mutually inverted clock signals And a low level signal control, each of the displacement temporary storage units includes a signal output circuit, a signal input circuit, a first logic circuit and a second logic circuit; wherein the signal input circuit controls the first logic The circuit outputs a low-level signal or a clock signal, and controls the signal output circuit to output a clock signal; the second logic circuit controls the signal output circuit to output a low-level signal; the two inverted clock signals are respectively the first clock signal and a second clock signal; the first logic circuit and the second logic circuit meet to form a second And the first logic circuit includes a fifth transistor and receives an externally provided first clock signal, the gate of the fifth transistor receives an externally provided first clock signal, and a source thereof is coupled to the second node The drain is connected to the latter displacement temporary storage unit. The liquid crystal display according to claim 9, wherein the displacement temporary storage unit is composed of a plurality of NMOS type transistors. The liquid crystal display of claim 10, wherein the signal input circuit, the first logic circuit and the signal output circuit meet to form a liquid crystal display A first node. The liquid crystal display of claim 11, wherein the signal input circuit comprises a first transistor and a second transistor; the gate of the first transistor receives a second clock signal provided by an external circuit, The drain is connected to the drain of the second transistor, and the source is connected to the first node together with the source of the second transistor. The liquid crystal display of claim 9, wherein the first logic circuit further comprises a third transistor and a fourth transistor; the gate of the third transistor is connected to the first node, the source thereof The pole receives the externally supplied low level signal, and the drain is connected to the source of the fourth transistor; the gate and the drain of the fourth transistor both receive the externally provided second clock signal. The liquid crystal display of claim 9, wherein the second logic circuit comprises a sixth transistor, a seventh transistor and an eighth transistor; the gate of the sixth transistor and the first a seventh transistor and a gate of the eighth transistor are connected to the second node, the source of the sixth transistor receiving an externally provided low level signal, the drain of which is connected to the first node; The sources of the seven transistors and the eighth transistor each receive an externally supplied low level signal, and the drains of the two are connected to the signal output circuit. The liquid crystal display of claim 14, wherein the clock transistor of the signal output circuit comprises a ninth transistor and a tenth transistor, and the ninth transistor and the gate of the tenth transistor Connected to the first node, both of which receive the first clock signal provided externally, and the sources of the two are respectively connected to the drains of the seventh transistor and the eighth transistor of the second logic circuit. To output signals separately to the next shift register unit And output signals to external circuits. The liquid crystal display of claim 15, wherein the signal output circuit further comprises a clearing transistor and a voltage stabilizing transistor, the clearing transistor comprising an eleventh transistor, the gate receiving The signal of the output of the latter displacement register unit receives a low-level signal externally supplied from the source, and the drain is connected to the source of the tenth transistor; the stabilized transistor includes a twelfth transistor The gate of the twelfth transistor receives an externally provided second clock signal, the source of which receives an external low level signal, and the drain of which is coupled to the source of the tenth transistor.