JPH04179230A - Resin-sealed semiconductor device - Google Patents

Abstract

PURPOSE:To prevent that a crack, the dislocation of an interconnection and a layer short circuit are caused by a method wherein a conductor film is formed, via an insulating film, on the interconnection arranged near the peripheral edge part of a semiconductor chip in such a way that the interconnection is covered. CONSTITUTION:An element region is formed on one main face of a semiconductor substrate 1; a first-layer interconnection 3 is formed, via a first layer insulating film 7, near the peripheral edge part of a semiconductor chip; then, second- layer interconnections 4a, 4b and a bonding pad 11 are formed via a second layer insulating film 8. In addition, a conductor film 5 is formed via a third layer insulating film 9 so as to cover the interconnections 4a, 4b; it is covered with an insulating film 10 for protective use; after that, only a bonding region on the bonding pad 11 is etched and revealed. A stress is generated at the resin-sealed semiconductor chip from its peripheral edge toward the center; the stress is exerted directly on the conductor film 5 and the stress exerted on the interconnections 4a, 4b is relaxed. It is possible to prevent a crack and a layer short circuit from being caused in the layer insulating film 9 surrounding the interconnections 4a, 4b.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a resin-sealed semiconductor device.

[Conventional technology]

A conventional resin-sealed semiconductor device is shown in FIG. 3 (a).

, as shown in (b), a semiconductor element region 2 is formed on one main surface of a semiconductor substrate 1, and a first layer of wiring 3 is formed around the semiconductor chip using an aluminum layer or the like via a first interlayer insulating film 7. Next, a second layer of wiring 4 is formed around the semiconductor chip using an aluminum layer via a second interlayer insulating film 8.
a, 4b and punch ink pad] and covered with a protective insulating film 10 such as a phosphosilicate glass film (hereinafter referred to as PSG film) or a silicon nitride film, and then a protective ink pad 11" The insulating film 10 was selectively etched to expose the surface of the bonding pad 1.

[Invention or problem to be solved]

This conventional resin-sealed semiconductor device has an angle of +15°, for example.
When a temperature cycle test from C to -65°C is performed, stress is generated due to the expansion and contraction of the sealing resin, and particularly large stress is applied to the four corners of the semiconductor chip's periphery. The protective insulating film 10 surrounding the layer wiring 4, a, 4b and the wiring t! 4a and the first-layer wiring 3 at the peripheral edge of the semiconductor chip, a crack occurs in the second glabella insulating film 8, and furthermore, the wiring 4a at the peripheral edge of the semiconductor chip.

41], which caused problems such as the occurrence of displacement (movement), which reduced the reliability of the wiring. As the cracking progresses further, an interlayer short circuit occurs at the intersection of the wiring 4a and the wiring 3, and for example, the wiring 4b used as a power supply line and the wiring 4a used as a ground line are connected via the wiring 3. There was a problem in that it caused a short circuit.

[Means to solve the problem]

The resin-sealed semiconductor device of the present invention includes a semiconductor substrate, an element region formed on one main surface of the board, a wiring provided on the element region via an insulating film, and a semiconductor chip including the wiring. A resin-sealed semiconductor device having a sealed resin body includes a conductor film provided on the wiring arranged near the peripheral edge of the semiconductor chip so as to cover the wiring with an insulating film interposed therebetween.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line AA', showing a first embodiment of the present invention.

As shown in FIGS. 1(a) and (b), an element region 2 is formed on one main surface of a semiconductor substrate 1, and a first interlayer insulating film 7 such as a PSB film with a thickness of 1.0 μm is interposed therebetween. A first layer of wiring 3 such as an aluminum film with a thickness of 0.5 μm is formed around the peripheral edge of the semiconductor chip, and then a second interlayer insulating film 8 such as a plasma oxide film with a thickness of 1.0 μm is formed. A second layer of interconnections 4a, 4b and a bonding pad 11, such as an aluminum film with a film thickness of 1.0 μm, are then formed, and then a third interlayer insulating film 9, such as a plasma oxide film with a film thickness of 0 μm, is formed. A conductor 15 such as an aluminum film with a film thickness of 1.3 μm is connected to the wiring 4a through the
, 4b and covered with a protective insulating film 10 such as a PSG film or a silicon nitride film with a film thickness of 1.0 μm,
Only the bonding area on the bonding pad 11 is etched and exposed.

In a semiconductor chip sealed with resin, stress is generated from the periphery of the semiconductor chip toward the center of the semiconductor chip. At this time, the second layer wiring 4a is placed in a part of the corner of the semiconductor chip.
4b, direct stress is applied to the wirings 4a and 4b as shown by the arrows in the figure, causing cracks to occur in the protective insulating film 10 and the interlayer insulation film 8, and even to the wirings 4'a and 4b.
An interlayer short circuit may occur at the intersection between the wiring 4a and the wiring 3. Therefore, as in this embodiment, a conductive film 5 is provided on the wirings 4a, 4b disposed at the peripheral edge of the semiconductor chip to cover the wirings 4a, 4b with the third glabella insulating film 9 interposed therebetween. The stress caused by the resin stopper is directly applied to the conductor film 5, and the stress applied to the wiring lines 4a, 4b was approximately 38 kg/mm2 before application, but after application, it was reduced to approximately 30% to approximately 27 kg/mm2. This makes it possible to prevent cracks in the glabellar insulating film 9 surrounding the wirings 4a and 4b, as well as glabellar short circuits.

FIGS. 2(a) and 2(b) are a plan view and a sectional view taken along the line B-B' showing a second embodiment of the present invention.

As shown in FIGS. 2(a) and 2(b), an element region 2 is formed on one main surface of a semiconductor substrate 1, and a film thickness is Wires 15 and bonding pads 11 at the periphery of the semiconductor chip are formed using a 1.0 μm thick aluminum film or the like, and then a 13 μm thick film is formed via a second interlayer insulating film 8 such as a 1.0 μm thick plasma oxide film. After forming a conductor film 5 such as an aluminum film to cover the wiring 15 and covering it with a protective insulating film 10 such as a PSG film or a silicon nitride film to a thickness of 1.0 μm, a bonding area on the bonding pad 11 is formed. Only the etched portion is exposed by etching, and the same effect as in the first embodiment is obtained.

〔Effect of the invention〕

As explained above, the present invention provides a conductive film that covers the wiring via an insulating film on the wiring disposed at the periphery including the four corners of the semiconductor substrate, thereby reducing the stress caused by the sealing resin body. By directly applying it to this conductor film, the stress applied to the wiring can be alleviated, preventing cracks in the insulating film surrounding the wiring, misalignment of the wiring, and interlayer short circuits, and significantly improving the reliability of the wiring. It has this effect.

61

[Brief explanation of the drawing]

FIGS. 1(a) and (b) are a plan view and a sectional view taken along line A- and F' showing a first embodiment of the present invention, and FIGS. 2(a) and (b) are a plan view and a cross-sectional view showing a second embodiment of the present invention FIG. 3(a) is a plan view and a sectional view taken along the line B-B' showing the embodiment. (1) is a plan view and a sectional view taken along the line C-C' showing an example of a conventional resin-sealed semiconductor device. 1 Semiconductor substrate, 2... Element region, 3... First layer wiring,... 1a,, 4b, Second layer wiring, 5. Conductor film, 6
Field I/Oxide film, 7 First interlayer insulating film, 8/Second interlayer insulating film, 9 Third interlayer insulating film, 10...Protective insulating film,]] 1-Punch ink pad 13...Through Paul,] 5. Wiring.

Claims (1)

[Claims] A resin-sealed semiconductor having an element region formed on one main surface of a semiconductor substrate, wiring provided on the element region via an insulating film, and a resin body sealing a semiconductor chip including the wiring. 1. A resin-sealed semiconductor device comprising: a conductor film provided on a wiring disposed near a peripheral edge of the semiconductor chip so as to cover the wiring with an insulating film interposed therebetween.