JPH04177472A - Automatic wiring method - Google Patents

Abstract

PURPOSE:To efficiently perform peeling/rewiring processing, to speed up the processing, and to reduce memory capacity in use by connecting route retrieval algorithm to the wiring order of a pin pair organically. CONSTITUTION:In pre-processing, supplied pin pair groups 1, 2, 3, and 4 targeted to connect are rearranged in the order of the one near to the arbitrary direction of a wiring area 5. In first processing, a route is retrieved along the above direction as near as possible in the order rearranged by the pre-processing. In second processing, the retrieval of the route that fails the retrieval is executed again as peeling the pin pairs 1, 2, 3, and 4 connected until then when the route fails the retrieval in the first processing. In third processing, the retrieval of the route is repeated as increasing the quantity of the pin pairs 1, 2, 3, and 4 to be peeled when the another execution by the second processing fails. In fouth processing, the order of wiring is changed locally according to the increment of the quantity of the pin pairs 1, 2, 3, and 4 to be peeled by the third processing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an automatic wiring method, particularly to an automatic wiring method for optimal wiring layout in CAD for printed circuit boards, hybrid ICs, LSIs, etc.

[Conventional technology]

Conventionally, in this type of automatic wiring method, for a group of pin pairs to be connected, the pin pairs are first arranged in order of shortest distance or longest distance, and a route search is performed in accordance with that order. If the route search fails for a certain pin pair, the connection of that pin pair is given up at that point, and processing proceeds to the connection of the next pin pair.

On the other hand, there is also a method that does not immediately give up on failed pin pairs. When a route search for a certain pin pair fails, analyze the circumstances under which the failure occurred, and in order to connect the failed pin pair, which pin pair should be removed from the pin pairs that have already been wired to connect the failed pin pair. Determine whether there is a high possibility of wiring. This is a wiring method in which the pin pair with a high possibility of failure is removed, the pin pair for which the route search failed is rewired, and the pin pair that was removed earlier is rerouted. This type of automatic wiring method is called a rip-up router.

For example, as shown in FIG. 13, if six pin pairs 6, 7, 8, 9, 10, and 11 to be connected are already connected in the wiring area 5, the pin pair 12 cannot be connected. Therefore, it is calculated which pin pair among pin pairs 6 to 11 should be peeled off. The calculation method is to search for existing wiring so as to spread ripples from pins 13 and 14 of pin pair 12 that cannot be connected, and to make a determination based on the search results. FIG. 14 shows the case where ripples are spread from the pin 13, and the position where the ripples reach the existing wiring is marked with an X. Furthermore, area 15 represents a region of expanded ripples. On the other hand, FIG. 15 shows the case where ripples are spread from the pin 14, and the position where the ripples reach the existing wiring is marked with a circle. Furthermore, area 16 represents the area of expanded ripples.

Next, the following calculation formula is calculated for each existing wiring.

P(w)=min (A-a, B-b) where, mi
n () represents the smaller value in parentheses.

Further, W is a value for identifying each existing wiring.

Further, A represents the number of x's in the existing wiring, and B represents the number of ○'s.

For example, from Figures 14 and 15, pin pair 6 A and B
The values of are 2 and 5, respectively.

Further, a and b are set to 0 if the two pins at the end points of the existing wiring are in the same area or on the boundary with respect to the area where the ripples are spread, and are set to 1 if they are in different areas. For example, in pin pair 6 in FIG. 14, pin 17 is within area 15, but pin 18 is outside area 15, so the value of a is l. On the other hand, in pin pair 6 in FIG. 15, both pin 17 and pin 18 are outside area 16, so the value of b is 0. From the above definition, the value of the formula for pin pair 6 is as follows:
It is calculated as follows.

P(6)=min (2-1,5-0)=min (
1, 5) = 1.

The above calculations are performed for all existing wiring that the ripples have reached. When similarly calculated for the six existing wirings in FIG. 13, the results are as follows.

P(6)=min (2-1,5-0) =:min
(1, 5) = IP (7) = min (7-0, 0-0
) =min (7,O) =OF(8)=min (
4-1, 2-1) = min (3, 1) = IP(9
)==min (5-1, 3-0) =m:n (4,
3) =3P(10)min (2-0,5-0) =
min (2, 5) = 2 A calculated value of 0 means that it is not possible to rewire the failed pin pair even if removed, and the more the existing wiring with a larger calculated value is removed, the faster the rewiring will be. It means there is a high chance of success. Therefore, in this case, it is understood that pin pair 9 having the maximum value of 3 should be removed.

From this conclusion, we peeled off pin pair 9 and failed pin pair 1.
FIG. 16 is a diagram showing the rewiring of the pin pair 9 that was removed by rewiring the pin pair 9.

In the above example, only one existing wiring was removed, but if the failed pin pair cannot be rewired, multiple pins with the highest calculated value are removed at once, or in sequence. There is a way.

[Problem to be solved by the invention]

In the conventional rip-up router method described above, the initial pin pair connection order is not particularly limited, and when an unconnected wire occurs, it searches for a candidate for an existing wire to be ripped out, so it is not possible to perform stripping efficiently. There is a problem. Also,
When searching for candidates to peel off, the process takes a long time to spread out the ripples, and at a stage where there are relatively few existing wiring lines, the ripples may spread over the entire surface of the board, resulting in an enormous amount of processing time. . Further, there is no guarantee that the rewiring of the pin pair that failed after being torn off will be successful, and even if the failed pin pair can be rewired, there is no guarantee that the torn out pin pair will be restored. Therefore, there is a problem in that it is easy to end up unable to increase the interconnection rate after spending a lot of processing time.

Furthermore, the problem of deciding how many pin pairs to separate requires the introduction of empirical elements, making it difficult to formulate a uniform algorithm. Another problem is that a considerable amount of memory table is used to calculate the optimal existing wiring to be removed.

In addition, since the method of connecting each pin pair is no more than repeating the conventional route search, there are cases where the connection becomes impossible no matter how much you try to separate the pins.

For example, when making the connection as shown in Figure 2, pin pair L
If wiring is attempted in the order of 2.3.4, the connection will fail at pin pair 3 as shown in FIG. Here, after tearing off pin pair 2 and rewiring pin pair 3 according to the conventional method, when trying to connect pin pair 2 again and then connecting pin pair 4, the wiring fails as shown in FIG. 12. As described above, the conventional method has the problem that the previously connected wiring blocks the wiring channel, and no matter how much it is removed, it is not successful.

An object of the present invention is to organically link the initial pin pair connection order and the route search method for each pin pair, to efficiently perform peeling processing, and to incorporate the number of pins to be peeled into the peeling algorithm itself. To provide a uniform automatic wiring method by providing a pointer for storing wiring rearrangement information when rewiring is successful so as not to fall into an infinite loop process.

[Means to solve the problem]

The automatic wiring method of the present invention includes a preprocessing that arranges a given group of pin pairs to be connected in the order of those closest to an arbitrary direction of the wiring area, and a route that follows the above direction as much as possible in the order rearranged by this preprocessing. a first process that searches for a route, a second process that re-executes the failed route search while tearing off the pin pair that has been connected when the route search fails in the first process; If the second execution fails, the route search is repeated while gradually increasing the number of pin pairs to be torn out, and the third process locally changes the order of wiring as the number of pin pairs to be torn out increases. a fourth process for changing the wiring order; a fifth process for providing a pointer indicating a situation in which the order has been swapped when the connection of the pin pair is locally successful due to the change in the wiring order by the fourth process; The present invention includes a sixth process in which the pointer is traced when the order of wiring is changed by the process in step 4, and the connection is abandoned if a loop state occurs.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a flowchart of an SPD format according to an embodiment of the present invention. In accordance with the algorithm shown in the flowchart of FIG. 1, the explanation will be centered on the process of increasing the peeling level and the process of rearranging the wiring order. Now, let's take the case where a group of pin pairs as shown in FIG. 2 is given as an example. Pin pair 1.
2. Attempt wiring in the order of 3.4 (step ■, @~[phase]). If the search for the connection route is carried out as downward as possible (steps 2 to 2, 2), the connection will fail at pin pair 4 as shown in FIG. 3 (steps 2, 2, o). At this point, remove pin pair 3 and proceed to step 0. ■~@), after wiring pin pair 4, rewire pin pair 3 (step 0). However, as shown in Figure 4, rewiring fails (step @
, @, e). So this time, we increased the level of peeling (step e).

■), Peel off pin pair 2 and step ■, C ~ @)
, attempts to connect pin pairs in the order of pin pairs 1.4.3.2 as shown in FIG. 5 (step 0). However, here again pin pair 2
The connection fails (step C20). Therefore, the wiring order is rearranged for the three pin pairs 4 and 3.2 (step O), and the wiring is performed in the order of pin pairs 3, 2, and 4 as shown in FIG. 6 (step 2, [phase] to 0). Here, connection fails with pin pair 4 (steps @, @, e), so raise the level of stripping again and strip pin pair 1. 7 Connect pin pairs in the order of 3.2.4.1 as shown in Figure 7 (Step o)
. Here too, pin pair 1 fails (step @, @
), rearrange the order with pin pair 2.4.1, 3 (step O), reconnect the wires (step C2C~0), and the 8th
Wiring is completed as shown in the diagram (step @, 0-@l)
. Finally, shape the wires connected as downward as possible (Steps ■ to ■) to create the final wiring shape as shown in Figure 9 (
Step ■.

■～■,■).

Also, in order to avoid falling into an infinite loop, when the pin pairs are successfully rearranged (step @, 0), a pointer to the pin pair that caused the connection failure is given to each pin pair (step Q), and the pointer is used to Remember the context of the connections. If this pointer enters a loop state (steps ■, @), it will be possible to decide to interrupt the process, since even if the above steps are repeated, it will end up in an infinite loop (steps ■, @). ).

FIG. 10 is a diagram for explaining a structure for suppressing infinite loops. Now, there are three pin pairs A, B, and C. As shown in (a), when A is connected, B cannot be connected, and B
Suppose that there is a three-way situation in which C cannot be connected when C is connected, and A cannot be connected when C is connected. Here, the relationship that gives the unconnectable state to other pin pairs is shown by solid arrows. If the initial connection order is ABC, the connection fails at B as shown in FIG. Therefore, if the connection order is set to BAC according to the above pin pair recombination rule, the connection of B will be successful as shown in (c), so from B to A.
A pointer indicating that A is the cause of B's failure is given to B. This pointer is indicated by a dotted arrow.

However, since the connection fails at C, the connection order is changed from CBA. (d) As shown in the figure, the connection of C is successful and a failure cause pointer is provided from C to B. However, connection fails again at A.

Next, as shown in (e), the wiring order is rearranged to ACB, and in this wiring process, a failure cause pointer is given from A to C. If B fails here, the failure cause pointer will form a loop from B and return to B, so it will be found that it will fall into an infinite loop process, and the pin pair of B will be abandoned and the automatic wiring will proceed further. It will be possible to go.

〔Effect of the invention〕

As explained above, the automatic wiring method of the present invention organically links the route search algorithm and the connection order of pin pairs, and can efficiently perform tear-off and re-wiring processes, making it possible to perform peel-off and re-wiring processes more efficiently than conventional rip-up. It can process faster than a router. In addition, the amount of memory used is considerably less than that of the conventional method.

Furthermore, with a conventional rip-up router, a group of pin pairs that failed even after stripping and rewiring could be reconnected by a procedure of gradually increasing the stripping level and a procedure of rearranging the stripped pin pairs and attempting to connect them. It has the effect of increasing the possibility of success. In addition, providing a failure cause pointer when attempting rewiring has the effect of preventing an infinite loop and making it possible to stop the rewiring attempt with minimal processing.

[Brief explanation of drawings]

FIG. 1 is a flowchart of an embodiment of the present invention, FIG. 2 is a diagram showing an example of four pin pairs and wiring areas to be connected, and FIGS. 3 to 9 show an example of the embodiment of FIG. 1. 2 is a wiring diagram showing the processing process when applied to the wiring connection, FIG. 10 is a diagram for explaining the mechanism for suppressing the infinite loop of the present invention, and FIGS. 11 and 12 are diagrams showing the process in the conventional automatic wiring method. 13 to 16 are diagrams illustrating failure examples and are diagrams for explaining the algorithm of the conventional climb-up method. 1.4,6. ~12...Pin pair, 5...
...Wiring area, 13, 14, 17.18...Pin, 15.16...Ripple arrival area. Agent Patent Attorney Uchihara Oto No. 1 Figure (a-) Figure 1 (b) 1977 (C) Figure 1 (4) Figure 1 (e) Ip 2) 3) 4: Pin Father A No. 2
Figure 3: Figure 4: Figure 5: Figure 7: Figure 8: Figure q (C): BAC Taku lθ Ward

Claims (1)

[Claims] A pre-processing process that arranges a given group of pin pairs to be connected in order of those closest to a given direction in the wiring area, and a first process that searches for a route along the aforementioned direction as much as possible in the order that is rearranged by this pre-processing process. When the route search fails in this first process, the second process re-executes the failed route search while tearing off the pin pair that has been connected so far, and if the second process also fails. a third process in which the route search is repeated while gradually increasing the number of pin pairs to be torn off; and a fourth process in which the order of wiring is locally changed as the number of pin pairs to be torn out increases through this third process. , a fifth process for providing a pointer indicating a situation in which the order has been swapped, if the connection of the pin pair is locally successful due to the change in the wiring order by the fourth process;
An automatic wiring method characterized by comprising a sixth process of tracing a pointer when changing the order of wiring in the fourth process and abandoning the connection if a loop state occurs.