JPH04176295A - Magnetic recording and reproducing device - Google Patents

Abstract

PURPOSE:To stably make the phases of a decode sub carrier and an encode sub carrier match and to obtain a composite picture signal with high picture quality by controlling the phase of the decode sub carrier information and the amount of shift by a clock unit according to the intensity of phase comparison error voltage. CONSTITUTION:Phase shifters 29 and 31 shift the phases of the first timing signal separated from the reproduction luminance signal and the second timing signal separated from a reproduction color difference signal continuously according to the phase comparison error voltage between the sub carrier information and the encode sub carrier information separated respectively in the reproduction systems. Writing clocks to a time axis correction device 17 of the reproduction luminance signal and the reproduction color signal respectively synchronized with these shift-phased first and second timing signals are prepared. By this operation, the picture signal to be read out from the time axis correction device 17 is continuously phase-shifted. A writing start signal to write the picture signal in the time axis correction device 17 by means of the first and second delay means is delayed by a clock unit, and the amount of delay can be varied according to the phase comparison error voltage which is currently supplied.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides a method for converting a composite video signal into component video signals, such as a luminance signal (Y signal) and a color difference signal (B-Y signal).
The present invention relates to a magnetic recording and reproducing apparatus that converts the magnetic field signal into a magnetic field signal, R-Y signal, and records and reproduces the converted signal on a magnetic tape or the like.

Conventional technology In recent years, composite video signals have been
- Decode to Y signal, compress both color difference signals in time axis,
There are many magnetic recording and reproducing devices that convert the Y signal and CTCM signal into one channel multiplexed signal (referred to as a CTCM signal) and record and reproduce the Y signal and CTCM signal using separate magnetic heads. Since an ideal decoder cannot be realized in these magnetic recording/reproducing devices, either a color signal component remains in the Y signal, or a Y signal component remains in the color signal, mainly at the edge portions. Therefore, when encoding into the original composite video signal, if the phases of the decoded and encoded subcarriers do not match, image quality will deteriorate. Conventionally, in order to prevent this image quality deterioration,
The phase of the read clock and read start signal of the time axis corrector is controlled to match the phases of the decode/encode subcarriers. The operation will be explained below using the drawings.

FIG. 3 is a block diagram of a recording system of a conventional magnetic recording/reproducing apparatus. The composite video signal inputted from the input terminal 1 is converted into Y, B-Y by the decoder 2.

It is converted into an RY signal. The Y signal is supplied to a superimposition device 3, and decoded subcarrier information (referred to as a VISC signal) is superimposed on the 15th line of the vertical blanking period. FIG. 4(a) is a waveform diagram of the VISC signal. VISC
The phase of the signal is in the −U axis direction, that is, in phase with the burst signal. The Y signal on which the VISC signal has been superimposed is supplied to a first timing signal adder 4, and a timing signal for creating a write clock and a write start signal to the time axis corrector during reproduction is added. FIG. 4(b) shows the Y signal to which a timing signal is added. In this conventional example, the timing signal is a 2.25 MHz burst signal that is added to the horizontal blanking period. On the other hand, the decoded B-Y and R-Y signals are supplied to a second timing signal adder 5, and, like the Y signal, a timing signal for creating a write clock and a write start signal is added. The RY signal includes a horizontal synchronization signal and 2. 25/
2MHz burst signal, 2.25/2 for B-Y signal
MHz burst signals are added and supplied to the time-base compression multiplexer 6, respectively. In the time axis compression multiplexer 6, R-Y
, the time axis of the B-Y signal is compressed in half and converted into a CTCM signal multiplexed into one channel. FIG. 4(c) is a waveform diagram of the CTCM signal.

The above-mentioned Y signal and CTCM signal are each sent to the modulator 7. It is supplied to a modulator 8, frequency modulated, and then applied to a magnetic head 9.
10, it is recorded onto the magnetic tape.

FIG. 5 is a block diagram of a reproducing system of a conventional magnetic recording/reproducing apparatus. During reproduction, the signals reproduced by the magnetic heads 9.10 are respectively supplied to the demodulators 11.12 and frequency demodulated to obtain a reproduced Y signal and a reproduced CTCM signal. The reproduced Y signal is supplied to a timing signal separator 13, where the timing signal added in the recording system is separated to create a write start signal. The write start signal is supplied to a write clock generation circuit 15, which generates a write clock synchronized with the jitter of the reproduced Y signal. write start signal,
The reproduced Y signal is sent to the time axis corrector 17 by the write clock.
written to internal memory.

Similarly, the reproduced CTCM signal is transmitted to the timing signal separator 1
The write start signal generated in step 4 and the write clock generated by the write clock generator 16 are used to write to the memory in the time axis corrector 17. The frequency of the write clock is 13.6 MHz in both cases.

The time axis corrector 17 removes jitter and expands the time axis of the CTCM signal to obtain Y, RY, and BY signals. The read clock for reading from the memory in the time axis corrector 17 is a 13.5 MH clock generated by the reference clock generator 19 based on the reference video signal from the input terminal 28.
z clock is supplied via phase chic 20. Further, the read start signal is generated by the read reference signal generator 18 based on the reference video signal from the input terminal 28 and the read clock from the phase shifter 20, and is supplied via the shift register 27 which is delayed in clock units. .

The Y signal from the time axis corrector 17 is supplied to a separator 21, and the VISC signal superimposed in the recording system is separated. The separated VI SC signal is sent to a phase discriminator 22 and a phase comparator 2.
3. In addition, the input terminal 2 to the phase discriminator 22
The U-axis and V-axis encode subcarriers generated by the encode subcarrier generator 26 are supplied by the burst signal of the reference video signal from 8, and the vector plane composed of the U-axis and V-axis is The VISC signal is divided into regions, and it is determined in which region the separated VISC signal exists. Figure 6 is a vector plan view divided into four areas, x
, y, z, and w are the four regions. Supplying the discrimination result of the phase discriminator 22 to the shift register 27,
The amount of delay of the output signal of the read reference signal generator 18 is controlled. In other words, the read timing from the memory is controlled in clock units.

For example, if the VISC signal exists within the X region in FIG. 6, the video signal is read out at the current read timing. If it exists in the X area, 1 of the 13°5MHz clock
Read with clock delay timing. If it exists in the Z area, it is read out at a timing delayed by two clocks. If it exists in the W area, it is read out at a timing that is one crotch ahead.

By shifting the 13.5MHz clock by one clock,
(3,58M/13.5M)X360' ≠95
The °VISC signal rotates on the vector plane.

By controlling the delay Mk in the shift register 27 as described above, the VISO signal converges within the X region.

The phase comparator 23 is supplied with the VISC signal from the separator 21 and the U-axis subcarrier from the encode subcarrier generator 26, and the U-axis subcarrier is inverted by an inverter and compared in phase with the vISC signal. The phase comparison error voltage at phase comparator 23 is supplied to phase shifter 20 to shift the phase of the 13.5 MHz clock from reference clock generator 19. The phases of the read start signal and the read clock are shifted by the amount shifted by the phase shifter 20, and the timing of the video signal read from the memory is shifted. This operation shifts the phase of the VISC signal, and a new phase comparison error voltage is applied to the phase comparator 2.
3 and is supplied to the phase shifter 20. and,
It becomes stable at the point where the vISO signal and the encoded subcarrier of the −U axis match in phase. Since the VISC signal is the -UU axis code subcarrier of the recorded composite signal, the decoding axis and the encoding axis coincide.

Note that the control of the phase shifter 20 operates only when the VI SC signal exists within the X region. In other words, when the VISC signal exists in a region other than the X region, the VISC signal is digitally converged in the X region in clock units, and then analogically matched in the -U axis direction.

According to the above operation, the Y, R-Y, B-Y signals read out from the time axis corrector 17 are supplied to the encoder 24 and encoded, converted into the original composite video signal without image quality deterioration, and output to the output terminal. It is output from 25.

Problems to be Solved by the Invention However, in the above configuration, the VISC signal is read out from the time axis corrector using a memory dedicated to the vISO signal and a dedicated readout clock that does not phase shift.
Since the phase of the signal is not determined, when tape editing a composite video signal with different 5CH (phase relationship between the subcarrier of the composite video signal and the horizontal synchronization signal), the editing point will be changed from -10 to the phase comparison error voltage. The subsequent vr sc multiplied signal phase determination may not be performed correctly, and the phase shift of the read clock may cause a malfunction. For example, if you edit three composite video signals: (1) SCH=35', (2) SCH=70°, (3) SCH=105°, (1)
For the signal , the VISC signal is controlled so that it coincides with the point A in FIG. 6 in the -U axis direction. At this time, a control voltage for shifting by 35° is supplied to the phase shifter 20 from the phase comparator 23. From this state, the signal (2) is reproduced after the editing point. Phase shifter 2
Since the control voltage to 0 cannot change instantaneously, the VISC signal for the signal in (2) does not appear in the W region, but appears again near point A in the X region. Therefore,
Controlled by the phase shifter 20, they are matched in the -U axis direction. At this time, a control voltage for shifting by 70° is supplied to the phase shifter 20.

II- From this state, the signal (3) is reproduced after the next editing point. Similarly, since the control voltage cannot change instantaneously, the vISC signal for the signal in (3) does not appear in the 2 region, but also appears near point A in the X region.

For this purpose, a control voltage is supplied to the phase shifter 20 for a total shift of 105°. If this operation is repeated, the control range of the phase comparator 239 and phase shifter 20 will be exceeded, causing malfunction.

VISC with no phase shift due to phase comparison error voltage
When obtaining a signal, determining the phase of the VISC signal that has not been phase-shifted, and controlling the delay amount of the shift register based on the determination result, a memory dedicated to the vISC signal, a dedicated read clock generator, and other circuits are required. , circuit scale,
There is a problem of increased costs.

In addition, the time axis corrector 17 uses digital memory, and the time axis corrected video signal is converted into "CCIR Recommendation 6".
When outputting digital data according to specifications such as "01", there is a problem that the phase of the digital output clock, that is, the readout clock of the time axis corrector 17 changes with respect to the reference video signal.

The present invention solves the above-mentioned problems, and allows composite video of any SCH to be processed without changing the phase of the readout clock of the time axis corrector and without requiring a dedicated clock generator. It is an object of the present invention to provide a magnetic recording and reproducing device that can stably match the phases of a decoded subcarrier and an encoded subcarrier and obtain a high-quality composite video signal without malfunctioning even when a signal is edited. .

Means for Solving the Problems The present invention provides demodulating means for demodulating a reproduced luminance signal and a reproduced color difference signal from a reproduced signal, a time axis correction means for time axis correcting the output of said demodulating means, said reproduced luminance signal, From the reproduced color difference signal, the first. A timing signal separation means for separating the second timing signal, a separation means for separating subcarrier information from the reproduced luminance signal that has passed through the time axis correction means, and a phase comparison between the separated subcarrier information and the encoded subcarrier. , a phase comparison means for obtaining a phase comparison error, a phase discrimination means for discriminating the phase of the separated subcarrier information on a vector plane constituted by the U-axis and V-axis encoded subcarriers, and the phase comparison error. and a reference potential; a second comparator that detects that the phase comparison error is within a predetermined voltage; an arithmetic unit that performs an operation based on the output of the second comparator and the discrimination result of the phase discrimination means; The first timing signal shifts the phase of the second timing signal. a second phase shift means;
a first write clock generation means for creating a write clock for the time axis correction means of the reproduced luminance signal synchronized with the phase of the output signal of the first phase shift means; a second write clock generation means for creating a write clock for the reproduction color difference signal to the time axis correction means synchronized with the phase of the output signal; a first delay means for delaying the output signal of the phase shift means by the write clock of the reproduced luminance signal to obtain a write start signal for the reproduced luminance signal to the time axis corrector; and a delay amount controlled according to the output of the arithmetic unit. and second delay means for delaying the output signal of the second phase shift means by the write clock of the reproduced color difference signal to obtain a write start signal for the reproduced color difference signal to the time axis corrector. It is a playback device.

Effect of the present invention With the above-described configuration, the first phase shift means and the second phase shift means are supplied with a phase comparison error voltage between the subcarrier information separated in the reproduction system and the encoded subcarrier, and this error is The phases of the first timing signal separated from the reproduced luminance signal and the second timing signal separated from the reproduced color difference signal are continuously shifted in accordance with the voltage. A clock for writing the reproduced luminance signal into the time axis correction means in synchronization with the phase-shifted first timing signal is created. Similarly, the phase-shifted second
A write clock for the reproduced color signal is created in synchronization with the timing signal. Due to this operation, the phase of the video signal read out from the time axis correction means is continuously shifted.

Also, 1st. The write start signal for writing the video signal to the time axis correction means is delayed by the second delay means in clock units. By this operation, the video signal read out by the time axis correction means is shifted in clock units. The amount of delay is determined by the result of the phase discrimination means that detects the position of the subcarrier information added by the recording system on the encoded subcarrier plane, the magnitude of the phase comparison error voltage in the current steady state, and the first reference voltage. It is controlled by the result of calculating the output of the first comparator that performs the comparison and the output of the second comparator that detects whether the newly generated phase comparison error voltage is within a predetermined voltage range.

For this purpose, the first . The delay amount of the second delay means can be varied, and as a result, the phase comparison error voltage between the subcarrier information separated from the shifted video signal and the encoded subcarrier is currently supplied. The phase comparison error voltage is shifted in a direction that cancels out the current phase comparison error voltage.

Further, if the phase comparison voltage exceeds a predetermined voltage range by the second comparator, the first. The second delay means shifts the video signal to bring it into a predetermined voltage range.

The above operation causes the first. The control range of the second phase shift means is not exceeded.

Further, in order to control the writing system of the time axis corrector, the time axis corrector uses a digital memory, and even if a digital output of the video signal is provided, the phase of the digital output clock does not change.

Embodiment FIG. 1 shows a block diagram of a reproducing system of a magnetic recording/reproducing apparatus according to an embodiment of the present invention.

In addition, in the figure, the same reference numerals are given to the parts that operate in the same way as in the conventional example (Figure i6). Furthermore, the configuration of the recording system is the same as the conventional one. The configuration and operation will be explained below using the drawings.

The reproduced luminance signal obtained from the demodulator 11 is supplied to a timing signal separator 13 and a time axis corrector 17. The timing signal separator 13 separates the timing signal (FIG. 4b) superimposed in the recording system and supplies it to the phase shifter 29. The output signal of the phase shifter 29 is output from the write clock generator 15.
and is supplied to the shift register 30. The write clock generator 15 generates a write clock to the time axis corrector 17 that follows the jitter of the reproduced luminance signal. In the shift register 30, the delay amounts of the four timing signals are switched for each clock unit of the write clock. The amount of delay is controlled by the arithmetic unit 36. It is supplied to the time axis corrector 17 as a write start signal of the output reproduction luminance signal of the shift register 30. The reproduced luminance signal is written into the memory of the time axis corrector 17 using the write clock and the write start signal.

On the other hand, the reproduced CTCM signal from the demodulator 12 is supplied to the timing signal separator 14 and the time base corrector 17, and the timing signal separator 14 receives the timing signal superimposed in the recording system (FIG. 4C). is separated and supplied to the phase shifter 31. The output signal of phase shifter 31 is provided to write clock generator 16 and shift register 32.

The write clock generator 16 generates a write clock for the CTCM signal to the time axis corrector 17 that follows the jitter of the reproduced CTCM signal. As the write clock, a positive phase clock and a reverse phase clock are created. In the shift register 32,
The timing signal is delayed in 1/2 clock units using the positive phase and reverse phase write clocks, and four different signals are switched in 1/2 clock units to obtain a write start signal and supply it to the time axis corrector 17. . The amount of delay is controlled by the arithmetic unit 36. Note that the frequency of the write clock is 13.5 MHz. Since the time axis of the CTCM signal is doubled by the time axis corrector 17, the amount of shift in the phase shifter 31 is 1/1/2 of the amount of shift in the phase shifter 29.
It is 2. Similarly, the shift amount in the shift register 32 is also 1/2 of the shift amount in the shift register 30.

The reference video signal from the input terminal 28 is sent to the readout reference signal generator 18. The signals are supplied to the reference clock generator 19, which generates a read start signal and a read clock, respectively, and then supplied to the time axis corrector 17.

The frequency of the read clock is 13.5 MHz. According to the above-mentioned signals, the time axis corrector 17 removes jitter and expands the time axis of the CTCM signal.
Obtain Y signal.

The Y signal from the time axis corrector 17 is supplied to the divider 21, where the VISC signal (FIG. 4a) is separated. The separated VISC signal is supplied to a phase discriminator 34 and a phase comparator 23. The phase comparator 23 is supplied with the U-axis subcarrier generated by the encode subcarrier generator 26 from the burst signal of the reference video signal from the input terminal 28, and as in the conventional example, the VI SC signal and the -UU axis subcarrier are Perform phase comparison with The phase comparison error voltage which is the output of the phase comparator 23 is supplied to the phase shifters 29 and 31, and controls the phase shift amount of the phase shifters 29 and 31.

When the error voltage is a positive voltage, the output signal of the phase shifter is shifted in the direction of delay, and when it is a negative voltage, it is shifted in the direction of advance. Timing signal separator 1 with phase shifters 29 and 31
If the phase of the output signal of 3.14 is shifted, the phases of the write clock and write start signal will be shifted. Furthermore, if the write start signal is shifted in the backward direction, the video signal output from the time axis corrector 17 is shifted in the forward direction. Therefore, the phase of the VISC signal separated by the separator 21 advances.

The phase comparison error voltage is applied to comparators 33, 35, and 37.
The potential is also supplied to the comparator 33 and compared with the reference potential. In the case of this example, the reference potential is the ground potential (
Ov). In the comparator 35, the phase comparison error voltage changes the phase of the vrsc signal from the separator 21 to +
It is detected whether the voltage is within the voltage range shifted by 90° (advanced by 90°). In other words, the phase shifters 29, 31
The upper limit of the direction of delay is determined. The comparator 37 shifts the phase of the VISC signal by 90° (
90゛ Delay) Detect whether it is within the voltage range. In other words, the upper limit of the advancing direction of the phase shifter 29.degree. 31 is determined.

A phase discriminator 34 detects where the phase of the VI SC signal exists on a vector plane composed of U-axis and V-axis encoded subcarriers.

In this example, one region is the left half plane in the U-axis direction with the V-axis as the boundary, and the right-hand plane is divided into two regions with the U-axis as the boundary. Determine whether Figure 2 is a vector plan view divided into three areas, areas P and Q.

R is three regions.

The control of the amount of delay in the shift register 30 differs depending on the current phase comparison error voltage when the phase of the VDC signal exists in regions Q and R in FIG. In region Q, when the phase comparison voltage (Va) is larger than the reference voltage (Vref) (Va>Vref), 2 clocks, Va<V
When it is ref, it is delayed by one clock. Va in area R
When Va<Vref, advance by 1 clock, and when Va<Vref, advance by 2 clocks = 22-. The amount of delay in the shift register 32 is 1/2 of the above. A comparator 33 compares Va and Vref. Through the above operation, the VISC signal converges to region P, and the phase shifter 29 is controlled by the newly formed phase comparison error voltage to shift the phase of the VISO signal to -
Match the phase of the U-axis encoded subcarrier. The newly formed phase comparison error voltage at this time is generated in a direction that cancels out the error voltage before being shifted by the shift register 30. In other words, the error voltage is not added under the control of the shift register 30.

For example, when tape-editing signals of different SCHs, it is assumed that Va>Vre f due to control before the editing point. When the VISC signal after the edit point appears at point B in the second figure, the shift amount in the shift register 30 is delayed by two clocks, and when it appears at point C in the second figure, the arithmetic unit 36 controls it so that it is advanced by one clock. . By this operation, both are shifted to the second figure point D. Since the phase comparison error voltage with respect to the point is a voltage advanced by the phase shifter 29, that is, a negative voltage, it cancels out the error voltage before the editing point.

Therefore, the newly formed phase comparison error voltage is not added. When Va<Vref, if the delay amount is controlled to the value indicated in 1, the error voltage will be added in the same way as when Va>Vref, and the control range will not be exceeded.

Furthermore, if the newly formed phase comparison error voltage is within the predetermined voltage range when it exists in the region P of FIG. By controlling the phase thick 29 and 31 using the phase comparison error voltage at 23, the phase of the VI SC signal of the separator 21 is made to match the phase of the encoded subcarrier of the -U axis.

If the voltage exceeds the voltage range determined by the comparator 35, the delay amount in the shift register 30 is set to one clock delay. Further, if the voltage exceeds the voltage range determined by the comparator 37, the delay amount in the shift register 30 is advanced by one clock.

For example, when tape-editing signals of different SCHs and after controlling point E in Figure 2 and reproducing the signal at point F in Figure 2, the phase comparison error voltage of the phase comparator 23 changes instantaneously. Therefore, the vrsc of the output of the separator 21
The signal appears at point G in region P of FIG. The phase comparison error voltage supplied to the phase shifter 29.degree. 31 at this time is the sum of the error voltage at point E and the error voltage for drawing from point G in the -U axis direction. Therefore, point E and point G
The angle required to shift is over 90°. Therefore, in accordance with the output of the comparator 35, the arithmetic unit 36 controls the shift register 30 to delay by one clock. Due to this operation, the VISC signal appears at point H in the second figure, and a phase comparison error voltage for point H is formed. This voltage is at point E
Since the voltage is in the direction of canceling out all error voltages, the phase comparison error voltages do not add up and exceed the control range as in the conventional case. Also, if the arithmetic unit 36 controls the shift register 3o to advance by one clock when the phase comparison error voltage exceeds -90° (exceeds the voltage determined by the comparator 37), the same operation as above can be performed. The phase comparison error voltage does not add up and exceed the control range.

Y read out from the time axis corrector 17 by the above control,
The R-Y and B-Y signals are supplied to the encoder 24, converted into the original composite video signal, and outputted from the output terminal 25.

According to this embodiment, the phase discrimination result of the VTSC signal by the phase discriminator 34, the magnitude discrimination result of the phase comparison error voltage and the reference voltage by the comparator 33, and the result of the phase discrimination by the comparator 33,
5 and 37 is within the ±90° shift voltage range.
By calculating the amount of delay in the soft registers 30 and 32, the control range of the phase shifter 29 will not be exceeded even if video signals of different SCHs are edited.

Furthermore, a dedicated write clock generator for Memo 1 is not required.

In addition, since the phase of the write clock and write start signal is controlled, the phase of the output clock will not fluctuate even if a digital output of the video signal from the time axis corrector is provided.

Note that the magnetic recording and reproducing apparatus of this embodiment records and reproduces decoded color signals by time-axis compression multiplexing.
When recording and reproducing the decoded Y, R-Y, B-Y signals using a 3-channel head without time-base compression multiplexing, a timing signal adder and another channel of modulator are installed in the recording system, and the reproducing system A timing signal separator, a phase shifter that shifts the phase based on the phase comparison error voltage of the phase comparator 23, a write clock generator that creates a clock synchronized with the output signal of the phase shifter, and a phase discriminator 34.
Another channel of shift register is provided to control the delay finger according to the detection result of , and the shift amount of phase shifter 29.31 and the newly provided phase shifter are all the same, and shift register 30.32 and the newly provided shift register are It is sufficient to make all the delays ■ the same.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, the shift amount in clock units can be controlled according to the phase of decoded subcarrier information and the magnitude of the phase comparison error voltage.
Even if you edit an H composite video signal, the phase comparison error voltage will be added to the signal after the editing point, causing malfunctions. Video signals can be obtained. Further, there is no need to provide a dedicated memory, a dedicated clock generator, etc. for obtaining decoded subcarrier information that does not undergo phase shift under control using the phase comparison error voltage. Further, since the writing system of the time axis corrector is controlled, even if a digital output of the video signal is provided, the phase of the digital output clock will not fluctuate, and this has a great practical effect.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of a reproducing system of a magnetic recording/reproducing apparatus according to an embodiment of the present invention, Fig. 2 is a vector plan view for explaining the operation of the embodiment, and Fig. 3 is a conventional magnetic Block diagram showing the configuration of the recording system of the recording/reproducing device, No. 4
The figure is a waveform diagram for explaining a conventional magnetic recording and reproducing device, FIG. 5 is a block-28= diagram showing the configuration of a reproducing system of a conventional magnetic recording and reproducing device, and FIG. 6 is an explanation of the operation of the conventional example. FIG. 13.14...Timing signal separator, 15°16.
...Write clock generator, 17...Time axis corrector, 21...Separator, 23...Phase comparator,
24...Encoder, 29.31...Phase shifter, 30.32...Shift register, 33. 3
5. 37... Comparator, 34... Phase discriminator, 36... Arithmetic unit.

Claims (1)

[Scope of Claims] Demodulating means for demodulating a reproduced luminance signal and a reproduced color difference signal from a reproduced signal; time axis correction means for time axis correcting the output of the demodulating means; timing signal separation means for separating the first and second timing signals; separation means for separating subcarrier information from the reproduced luminance signal that has passed through the time axis correction means; and separation means for separating subcarrier information from the separated subcarrier information and encoded subcarriers. a phase comparing means for performing a phase comparison and obtaining a phase comparison error; a phase determining means for determining the phase of the separated subcarrier information on a vector plane constituted by U-axis and V-axis encoded subcarriers; a first comparator that compares a phase comparison error with a reference potential; a second comparator that detects that the phase comparison error is within a predetermined voltage; and outputs of the first and second comparators and the phase. an arithmetic unit that operates based on the discrimination result of the discrimination means; first and second phase shift means that shift the phases of the first and second timing signals according to the phase comparison error; first write clock generation means for generating a write clock for the time axis correction means of the reproduced luminance signal synchronized with the phase of the output signal of the phase shift means; a second write clock generation means for generating a write clock for the reproduction color difference signal to the time axis correction means in synchronization with the reproduction color difference signal;
a first delay means that delays the output signal of the phase shift means according to the write clock of the reproduced luminance signal to obtain a write start signal of the reproduced luminance signal to the time axis correction means; amount is controlled and the second
a second delay means for delaying the output signal of the phase shift means by a write clock of the reproduced color difference signal to obtain a write start signal for writing the reproduced color difference signal to the time axis correction means.