JPH04176206A - Limiter circuit - Google Patents

Abstract

PURPOSE:To change a limit level by inserting a DC power supply in series with each of two diodes and controlling a voltage of the DC power supply externally. CONSTITUTION:An anode of a diode 109 and a cathode of a diode 110 are connected to an input of an amplifier 112. Moreover, a negative pole of a variable DC power supply 108 is connected to a cathode of the diode 109 and a positive pole of a variable DC power supply 111 is connected to an anode of the diode 110, and the positive pole of the variable DC power supply 108 and the negative pole of the variable DC power supply 111 are connected to a positive terminal of a bias power supply 105. The DC voltage of the variable DC power supplies 108, 111 is controlled by a signal inputted from a limit level input terminal 102. Since the variable DC power supplies 108, 111 are subject to voltage control so that the variable output voltage is equal to each other, the positive and the negative limit levels are set symmetrically.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal processing circuit for a television receiver or the like, and particularly to a circuit for reducing noise present in a television signal.

[Conventional technology]

Conventionally, noise reduction circuits have been proposed for television receivers that reduce noise present in brightness signals and color signals. This type of noise reduction circuit is described in "Noise Suppression Circuit" described in JP-A-1-185287.

Figure 3 shows the main parts of the noise suppression circuit.
101 is an input terminal, 107 is a resistor, 113 is an output terminal,
109 and 110 are diodes, and 3o1 is a capacitor.

Next, the circuit operation will be explained.

A signal input from input terminal 101 passes through resistor 107 and is output to output terminal 116. The output terminal 113 has
The anode of the diode 109 and the cathode of the diode 110 are connected, and the capacitor 301 is connected to the cathode of the diode 109 and the anode of the diode 110.

When the voltage at the output terminal 115 is lower than the voltage stored in the capacitor 301 by VeL, the diode 110 is turned on and the voltage at the output terminal 113 does not drop any further. Furthermore, when the voltage at the output terminal 113 is higher than the voltage stored in the capacitor 301 by Vcl, the diode 109 turns OFF and the voltage at the output terminal 115 does not rise any further.

In this way, the output terminal 113 has ±
A signal limited by Va is output.

[Problem to be solved by the invention]

In the above conventional technology, the limiting level is 10
Since it is determined by the forward voltage of 9 and 110, it was not possible to limit it to an arbitrary level. Further, there is an exponential relationship between the voltage characteristics and current characteristics of the diode, and the current changes rapidly near the forward voltage Vd. Therefore, as shown in FIG. 4, when the input voltage approaches Vd, the relationship between input and output is no longer linear, and signals near the limit level become distorted.

The purpose of the present invention is to enable the limit level of an input signal to be changed externally, and to increase the input signal level so as not to be distorted by the exponential relationship of the voltage-current characteristics of the diode. The purpose is to ensure that a predetermined limit is applied even at that time.

[Means to solve the problem]

In order to achieve the above object, the present invention has a DC power supply inserted in series with two diodes, and the voltage of the DC power supply is externally controlled.

[Effect]

The DC power supplies inserted in series are added to the forward voltage Va of the diode. At this time, since the voltage of the DC power supply can be controlled externally, it appears that the forward voltage Va of the diode is changed. This allows you to change the limit level.

~Still, by making the voltage of the two DC power supplies inserted in series with the diode higher than the forward voltage Va of the diode, the nonlinearity near the voltage at which the diode turns on can be made relatively small. I can do it.

〔Example〕

A first embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, 103 is a capacitor, 104 is a resistor,
106, 112 are amplifiers, 105 is a bias power supply, 10
B, 111 is a variable DC power supply, and 102 is a limit level input terminal.

Next, circuit operation will be explained.

The signal input from the input terminal 101 is transferred to the capacitor 10.
3, the DC component is cut and a new bias power supply 105 is applied.
A bias voltage of is applied via the resistor 104. A signal to which a bias voltage is applied is input to an amplifier 106 which has a voltage gain of 1 and a large current gain and is amplified. The amplified signal passes through resistor 107 and is input to amplifier 112.

The anode of the diode 109 and the cathode of the diode 110 are connected to the input of the amplifier 112. Further, a variable DC power supply 108 is connected to the cathode of the diode 109.
The negative pole of the variable DC power supply 111 is connected to the anode of the diode 110, and the positive pole of the variable DC power supply 111 is connected to the anode of the diode 110.
The positive electrode of the bias power source 105 and the negative electrode of the variable DC power source 111 are connected to the positive electrode of the bias power source 105. The DC voltages of the variable DC power supplies 108 and 111 are controlled by a signal input from the limit level input terminal 102.

Here, since the variable DC power supplies 108 and 111 are voltage controlled so that their variable voltage values are equal, the limit levels are symmetrically limited on the positive side and the negative side, as shown in FIG. As a result, when the voltage value of the variable DC power source is decreased, the limit characteristic shown by small in the figure is shown, and as the control voltage is increased, the limit characteristic changes from medium to small.

In the present invention, the DC voltage value is given from the bias power supply 105, but if the bias voltage input to the input terminal 101 is known in advance, the bias voltage value may be used instead of the bias power supply 105. May be used. If the bias voltage value of the input signal is suitable for the circuit shown in FIG. The positive pole of variable DC power supply 108 and the negative pole of variable DC power supply 111 are connected to the positive pole of bias power supply 10.5. The DC voltages of the variable DC power supplies 108 and 111 are controlled by a signal input from the limit level input terminal 102.

Here, since the variable DC power supplies 10B and 111 are voltage controlled so that their variable voltage values are equal, the limit levels are symmetrically limited on the positive side and the negative side, as shown in FIG. As a result, when the voltage value of the variable DC power source is decreased, a limit characteristic indicated by small in the figure is exhibited, and as the control voltage is increased, the limit 7) characteristic changes from medium to high.

In this invention, the DC voltage value is given from the bias power supply 105, but if the bias voltage input to the input terminal 101 is known in advance, the bias voltage value can be used as a substitute for the bias electric erosion 105. May be used for. Furthermore, if the bias voltage value of the input signal is appropriate for the circuit shown in FIG.
may be removed.

By configuring the limiter circuit in this way,
It has the effect of being able to change the limit level from the outside. Also, change the voltage value to the diode forward voltage V (
If l is made larger, the amplitude of the input signal can be increased, so that the influence of internally generated noise and distortion due to nonlinearity when the diode is turned on can be reduced.

Next, a specific circuit example of the present invention will be explained with reference to FIG.

FIG. 5 is a diagram showing the specific circuit configuration of the limiter circuit.
501,502,514,507,508゜513.5
19 is a PNP type transistor, 505°506.509
,517,518,51.9,520°522 is NPN
type transistor, 504,510°512.515,5
16 is a resistor, 503 is a variable current source, and 521 and 523 are constant current sources.

Next, circuit operation will be explained.

The variable current source 503 changes its current value according to a limit level control voltage input from the outside.

A circuit composed of PNP transistors 501, 502, and 514 constitutes a current mirror circuit, and PNP
A current equal to the current value flowing through the collector of NPN transistor 1 can be caused to flow through the collectors of PNP transistors 502 and 514. Furthermore, NPN transistors 509 and 517 also constitute a similar current mirror circuit. Therefore, a current equal to the current of variable current source 506 is
The current flows to the collector of the transistor 514 (PNP) and the collector of the transistor 517 (NPN).

Resistors 504 and 510 and transistors 505 and 506,
507. The circuit consisting of 508 is a circuit that generates a bias voltage, and the generated bias voltage is applied to the resistor 51.
2 and transistors 511 and 515.

The extracted bias voltage is coupled through resistor 515 and transistor 518, and resistor 516 and transistor 519. Here, since the base voltage of the transistors 518 and 519 is connected to the collector of the current mirror circuit, a voltage is generated at the resistors 515 and 516 depending on the current value, and as a result, the base voltage of the transistors 518 and 519 is You can change the voltage. That voltage is transistor 5
18 and 519 to the emitter.

Here, since the base-emitter voltage Vbe of the transistors 511 and 518 is temperature compensated by the transistors 505 and 506, there is no voltage fluctuation due to temperature or the like. Furthermore, since the transistors 516 and 519 are similarly temperature-compensated by the transistors 507 and 508, there is no fluctuation due to temperature or the like.

The transistor 520 and the constant current source 521 constitute an amplifier that only performs current amplification of the input signal. The transistor 522 and constant current source 523 also constitute a similar amplifier.

Here, when the level of the signal input to the input terminal 101 is input with an amplitude larger than the voltage that turns on the transistor 518 or 519, the transistor 518 or 519 turns on and limits the signal. By changing the voltage input to the limit level input terminal 102, the limit level of the signal input to the input terminal 101 can be changed.

Next, a second specific example of the limiter circuit will be explained using FIG. 6.

Fig. 6 shows the circuit configuration when the transistors shown in Fig. 5 are connected in Darlington.
04 is an NPN) transistor, and 605 is a constant current source. In this circuit configuration, since the transistor 604 is added to form a Turlington circuit, the transistor 601
and 602 are newly added.

This increases the input impedance of the input transistor 520, which has the effect of allowing a limit operation to be performed without adversely affecting the signal.

Next, a first example of a circuit to which the limiter circuit of the present invention is applied will be explained using FIG.

FIG. 7 shows a circuit for reducing noise in a luminance signal or demodulated color difference signal, where 701 is an input terminal, 702 is a subtracter, 703 is an output terminal, and 704 is a high-pass filter (HPF).
, 705 is a limiter circuit.

Next, the circuit operation will be explained using FIG. 9 as well.

It is assumed that the signal input from the input terminal 701 is a signal containing noise as shown in FIG. 9(a). When this signal is input to a high pass filter (HPF) 704, noise components included in the high frequency range and contour components of the signal are extracted. The extracted signal is limited by a limiter circuit 705, and noise components are extracted as shown in FIG. 9(b). The extracted noise component is input to a subtracter 702 and subtracted from the signal input from the other side. As a result, only the noise components contained in the input signal are removed and output to the output terminal 706.

In this way, even if noise is included in the luminance signal or the demodulated color difference signal, only that noise component can be removed. Here, since the limiter circuit 705 uses the circuit of the present invention, the range of the limit level can be changed depending on the limit level input from the outside, and the limit level can be adjusted to the optimum limit level. .

Next, a second application example will be explained using FIG. 8.

Figure 8 shows a noise reduction circuit using a cyclic filter.
Here, the case where it is used for a carrier color signal will be explained.

In FIG. 8, 801 is a 1.times. (1 horizontal scanning period) delay circuit, 802 is an adder, and 805 is a coefficient multiplier.

Next, the circuit operation will be explained with reference to FIG. 10.

The carrier color signal shown in FIG. 10(a) inputted from the input terminal 701 is inputted to the adder 802.

A signal obtained by delaying the output signal by 1H is input to one side of the adder 802 and added to the signal input from the input terminal 701. Since the signal input here is a carrier color signal, the phase is inverted every 1H. Therefore, the addition process in the adder 802 means subtraction, and the vertical contour and noise components are extracted. The obtained vertical contour and noise component are input to the limiter circuit 705 and are changed depending on the signal level input from the limit level input terminal 75.
As a result, the signal shown in FIG. 10(b) is obtained.

Vertical contour components are removed from the limited signal, and only noise components are extracted and input to a coefficient unit 803. Here, a predetermined coefficient is multiplied and input to the subtracter 702.

The signal input to the input terminal of the subtracter 702 is input to the other side, and the noise component multiplied by the coefficient is subtracted from the signal. As a result, the output terminal 703 has the first
A carrier color signal from which noise components have been removed as shown in FIG. 0 (C) is obtained.

In the present invention, as in the above invention, the limit level of the limiter circuit 705 can be controlled from the outside, so it is possible to adjust the limit level to the optimum limit level according to the level and noise of the input signal.

Next, a third application example of the limiter circuit of the present invention will be explained using FIG. 11.

Figure 11 shows the noise reduction circuit in Figure 10 with an automatic noise detection circuit added, 901 is a noise detection, wave circuit, 90
2 is an integrating circuit, and 905 is a noise sample pulse input terminal.

Next, the circuit operation will be explained with reference to FIG. 13.

The signal output from the high pass filter (HPF) 704 is input to the noise detection circuit 901. Noise detection circuit 901
When the high-frequency component of FIG. 13(a) is input as an input signal, and the noise sample pulse of FIG. 15(c) is input as a control signal from the noise sample pulse input terminal 905, the noise The noise component of the input signal is detected and output only during the period when the sample pulse is Hlgh. Since the detected noise component is a horizontal synchronization signal period in which there is no video signal, by detecting this period, the average noise level can be detected.

This detection result is input to an integration circuit 902, and is integrated using a predetermined integration constant to avoid the influence of impulse noise and the like. By controlling the limiter circuit 705 with the output, the signal can be limited to the average noise level contained in the input signal, and the noise reduction circuit can be automatically operated. There is no need to adjust the limit level of the circuit.

Figure 12 shows an automatic noise reduction circuit added to the noise reduction circuit in Figure 8, and its operation is similar to that of the noise reduction circuit in Figure 6 and the automatic noise detection circuit in Figure 11. Equal to the combination.

Here, noise removal is performed on the carrier color signal, so
The carrier color signal shown in FIG. 13(b) is input to the input terminal 701, and the noise sample pulse shown in FIG. 15(0) is input to the input terminal 905 to operate.

By configuring a noise detection circuit as shown in Figure 12, the limit level is automatically set depending on the noise level of the input signal, so the limit level of the limiter circuit can be set externally. There is no need to adjust.

In the explanation of the operation of the circuits shown in FIGS. 11 and 12,
Although the operation in the horizontal scanning period shown in the figure has been described, the operation in the vertical scanning period as shown in FIG. 14 can also be performed. In this case, the input signal is the luminance signal shown in FIG.
The carrier color signal shown in FIG. 16B is the signal shown in FIG. 16, and the noise sample pulse is the signal shown in FIG.
The limit level of the limiter circuit can be automatically controlled accordingly.

〔Effect of the invention〕

According to the present invention, the limit level of the limiter circuit can be adjusted to an arbitrary level, so the level can be set according to the noise level of the input signal.

Further, according to the present invention, since the amplitude of the input signal can be increased and inputted, internally generated noise and distortion during limiting can be reduced.

Furthermore, according to the present invention, the noise level of the input signal can be detected during the non-video signal period and the limit level of the limit circuit can be automatically set, so that the limit level can be adjusted to the optimum limit level. can.

[Brief explanation of the drawing]

Fig. 1 is a limiter circuit diagram of an embodiment of the present invention, Fig. 2 is a characteristic diagram showing the operation of the limiter circuit of Fig. 1, Fig. 3 is a circuit diagram showing a conventional limiter circuit, and Fig. 4 is a conventional limiter circuit. 5 is a first specific circuit diagram of the limiter circuit of the present invention, FIG. 6 is a second specific circuit diagram of the limiter circuit of the present invention, and FIG. 7 is a characteristic diagram showing the operation of the limiter circuit of the present invention. FIG. 8 is a circuit diagram showing a first noise reduction circuit applying the limiter circuit of the present invention, FIG. 8 is a circuit diagram showing a second noise reduction circuit applying the limiter circuit of the present invention, and FIGS. 9 and 10 are A waveform diagram for explaining the operation of the first and second noise reduction circuits, FIG. 11 is a circuit diagram showing a third noise reduction circuit to which the limiter circuit of the present invention is applied, and FIG. 12 is a circuit diagram of the limiter circuit of the present invention. Circuit diagram showing the fourth noise reduction circuit applying the circuit, 1st
3 and 14 are waveform diagrams for explaining the operations of the third and fourth noise reduction circuits. 101... Input terminal, 102... Limit level input terminal, 106, 112... Amplifier, 104°10
7...Resistor, 105...Bias power supply, 1o8゜1
11... Variable DC power supply, 109, 110... Diode, 113... Output terminal. (Required procedural amendment (voluntary) Immediately with the person who amends the indication of the case / lf'Pl Patent applicant name (510) Manufactured by Hitachi Co., Ltd.
Subject of amendment by the author's agent Detailed explanation of the invention in the specification.

Claims (1)

[Claims] 1. An amplifier that amplifies an input television signal;
a first resistor connected to the output of the amplifier; a first diode having an anode connected to the first resistor; a second diode having a cathode connected to the first resistor; a first variable DC power supply connected to the cathode of the first diode; a second variable DC power supply connected to the anode of the second diode; the first variable DC power supply and the second variable DC power supply; A bias power source connected to a power source, a second resistor that supplies the bias voltage supplied from the bias power source to the amplifier, and a capacitor coupled to the input, and the first and second variable direct current A limiter circuit characterized in that a limit level is set by means of controlling a power supply. 2. A variable current source that varies the current value depending on the input limit level, two pairs of current mirror circuits that are connected to the variable current source and supply a current equal to the current value of the variable current source, and a limit bias. a limit bias voltage source that supplies a voltage, two limit transistors whose emitters are connected to each other, a resistor that connects the bases of the two limit transistors to the limit bias voltage source, and a bias voltage source from the limit bias voltage source. It consists of a second resistor that supplies a voltage, and an amplifier to which the input signal and the second resistor are connected, the emitters of the two limit transistors are connected to the output of the amplifier, and the two pairs of current mirrors are connected to each other. A circuit is connected to the two resistors, and includes a limit means for limiting the input signal when the input signal is higher than a level at which the two limit transistors are turned on, and a limit means for controlling the current value of the variable current source. 1. A limiter circuit comprising a limit level control means for controlling a voltage to be limited. 3. The limiter circuit according to claim 1 or 2, wherein the amplifier is a Darlington connection in which two transistors are connected. 4. Claim 1 or 2, comprising: a high-pass filter for detecting high-frequency components of an input signal; a limiter circuit for limiting the output signal of the high-pass filter at a predetermined level; and an output of the limiter circuit. A noise reduction circuit that uses a limiter circuit of the noise reduction circuit, which is composed of a subtracter that subtracts from an input signal. 5. Claim 1 or 2, further comprising: a 1H delay circuit that delays the output signal by one horizontal scanning period; an adder that adds the output of the 1H delay circuit and the input signal; A limiter circuit that limits based on level,
A coefficient multiplier that multiplies the output of the limiter circuit by a coefficient, a subtracter that subtracts the output of the coefficient multiplier from an input signal, and a noise reduction circuit in which the output of the subtracter is connected to the input of the 1H delay circuit. Noise reduction circuit. 6. In claim 4, there is provided a detector that detects the output of the high-pass filter during a non-video signal period, an integrator that integrates the output of the detector for a predetermined period, and an output of the integrator that detects the output of the limiter circuit. A noise reduction circuit with a means to control the limit level. 7. In claim 5, a detector detects noise in a non-video signal period using a noise sample pulse input from the noise sample pulse input terminal from the output of the adder, and integrates the output of the detector for a predetermined period. A noise reduction circuit comprising: an integrator; and means for controlling a limit level of the limiter circuit using an output of the integrator. 8. The noise reduction circuit according to claim 6 or 7, wherein the noise sample pulse is generated during a horizontal blanking period of a horizontal scanning period. 9. The noise reduction circuit according to claim 6 or 7, wherein the noise sample pulse is generated during a vertical blanking period of a vertical scanning period.