JPS61184056A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To stabilize the DC reproducing rate by detecting a mean video level of a video signal, multiplying an optional factor and the level together and adding the result to a pedestal period of the video signal. CONSTITUTION:The video signal IN is fed to a voltage adder circuit 33 via a capacitor 31 as one input and fed to an APL detection circuit 34. The circuit 34 detects the APL of the video signal IN at the pedestal period of the video signal IN and the voltage VAPL of the signal S1 corresponding to the detected APL is fed to a factor multiple circuit 35. The circuit 35 multiplies a factor betain response to the control voltage Vc fed to an external control terminal 36 with the voltage VAPL and the signal S2 having the attenuated betaVAPL is fed to the circuit 33 as other input. Thus, the betaVAPL is added at the pedestal period of the video signal IN in the circuit 33. The added video signal S3 is fed to a brightness amplifier circuit 38 via a contrast control circuit 37 and the DC recovery is applied and outputted from a terminal 39.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a video signal processing circuit built into a television receiver, a monitor receiver, etc. Concerning improvements in reproducing circuits.

[Technical Background of the Invention] In television receivers and the like, video signals have frequency components ranging from DC to several MH2. After such a video signal is AM demodulated, various signal processing such as amplification is normally performed by capacitive coupling before being supplied to the cathode ray tube. Therefore, the DC component of the video signal is lost during these signal processing steps. The black level in a video signal is determined by the level of a DC period called a pedestal period, and in general video signal processing circuits, a circuit called a DC reproduction is added to control the DC level during the pedestal period to a constant level. . The brightness of the television is adjusted by changing this DC level.

By the way, on a screen with sufficient contrast, the average level of the video signal, that is, the average video level (AVeraQ
e Picture 1 level (hereinafter referred to as APL) is high or the imaging width of the video signal is large, so the brightness is set to a low voltage. However, if a video signal with a low APL is processed while the bright voltage remains low, the screen will visually appear darker. Also, even when there is no signal, it feels very dark.

Therefore, conventionally, in order to reduce the effect of DC reproduction in such a case, the DC level during the pedestal period is changed in accordance with the APL of the video signal. In this way, the screen becomes visually easy to view.

FIG. 4 shows a block diagram of a conventional video signal processing circuit that performs the above-described processing. In this conventional video signal processing circuit, in order to change the DC level during the pedestal period according to the APL of the video signal, the video signal is superimposed on the DC reference voltage at a constant ratio and supplied as a clamp input to the bright amplifier circuit. ing.

That is, the video signal IN is supplied to the contrast control circuit 12 by capacitive coupling via the capacitor 11.

Therefore, the DC component of the video signal IN is lost in the contrast control circuit 12. Therefore, next, DC reproduction is performed by the bright amplification circuit 13. For the reason mentioned above, in order to reduce the DC reproduction, the output signal from the contrast control circuit 12 is bright amplified by capacitive coupling via the capacitor 14. Signal input terminal 1 of circuit 13
5 as an input, and the bright amplification circuit 13
A DC reference voltage E is supplied to the clamp voltage input terminal 16 of the parenthesis.The output signal from the contrast control circuit 12 is connected to the clamp voltage input terminal 16 of the parenthesis.
It is divided and supplied according to the following. Note that the contrast control circuit 12 and the bright amplification circuit 13
is integrated circuit, and the above contrast control circuit 1
The bright amplifier circuit 13 is provided with an external terminal 21 for output in addition to the input terminals 15 and 16. The capacitors and resistors described above are externally attached to the outside of the integrated circuit.

FIG. 5 is a waveform diagram showing an example of the operation of the conventional circuit. 5 shows the waveform of the signal supplied to the signal input terminal 15 of the bright amplifier circuit 13. In FIG. Since this signal waveform is divided by the two resistors 17 and 18, the AC component of the signal waveform supplied to the clamp voltage input terminal 16 of the bright amplifier circuit 13 becomes b in FIG. Since the DC reference voltage E is supplied to this clamp voltage input terminal 16, the bright amplifier circuit 13 generates a signal obtained by superimposing a video signal on this DC reference voltage E at a ratio corresponding to the resistance ratio of the resistor 17.18. Clamp the input video signal based on. As a result, as shown in waveform C in FIG. 5, the DC level from the output external terminal 21 of the bright amplifier circuit 13 during the pedestal period (t in FIG. 5) has a value corresponding to the APL. A video output signal 0IJT is output. Note that the DC regeneration rate α in this circuit is given by the following equation, assuming that the resistance values of the resistors 17.18 are R1 and R2.

Problems with IC Background Art By the way, the conventional circuit described above requires a large number of external components such as capacitors and resistors in addition to the integrated circuit, and has the disadvantage of being expensive to manufacture.

Since the resistor for roughly dividing the video signal is a discrete resistor, variations in the division ratio tend to occur, which also has the disadvantage of increasing the variation in the DC reproduction rate.

Furthermore, since the conventional circuit has as many external terminals as five terminals, the chip size becomes large when integrated into a circuit, which also has the drawback of increasing manufacturing cost.

[Object of the invention] This invention was made in consideration of the above circumstances, and its purpose is to provide a video signal processing circuit that can stabilize the DC reproduction rate and can be manufactured at low cost. It is about providing.

[Summary of the Invention] In order to achieve the above object, the video signal processing circuit of the present invention detects the average video level of the video signal, and multiplies this level by an arbitrary coefficient to the pedestal period of the video signal. The video signals after the addition are added are subjected to DC reproduction.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a video signal processing circuit according to the present invention, and FIG. 2 is a waveform diagram showing voltage waveforms of each part of the circuit according to the embodiment.

The video signal IN is transmitted via the capacitor 31 and external terminal 32.
The signal is supplied to the voltage adder circuit section 33 as one input, and is also supplied to the APL detection circuit section 34 .

This APL detection circuit section 34 detects the average level of the input video signal IN, that is, the APL (average video level) during the pedestal period of the input video signal IN. The voltage VAPL of the signal $1 corresponding to the detected APL is supplied to the coefficient multiplier circuit section 35. The coefficient multiplier circuit section 35 multiplies the voltage VAPL by a coefficient β corresponding to the control voltage Vc supplied to the external control terminal 36 to attenuate the voltage VAPL, and the signal S2 having the attenuated value βVAPL is It is supplied to the voltage adder circuit section 33 as the other input. Therefore, in the voltage adding circuit section 33, the voltage βVAPL is increased for the pedestal period of the input video signal IN.
is added. After the addition, the video signal S3 is subjected to contrast adjustment in a contrast control circuit 37 having the same configuration as the conventional one, and is further supplied to the bright amplification circuit 38 having the same configuration as the conventional one, where it is subjected to DC reproduction. is performed and output from the external terminal 39 for output. A DC reference voltage Va is supplied to an external terminal 40 for inputting a clamp voltage of the bright amplifier circuit 38.

Here, the bright amplifier circuit 38 operates to clamp the DC level during the pedestal period to the DC reference voltage VB supplied to the external terminal 40 for clamp voltage input. Therefore, the output signal OUT obtained at the output terminal 39 has a waveform such that the DC level of the voltage βVAPL added during the pedestal period matches the DC reference voltage VB, as shown in FIG.

Therefore, the DC voltage level during the pedestal period of the output signal 0tJT in FIG. 2 is equal to the APL of the input video signal.
It corresponds to the voltage VAPL, and if the value of the control a lightning voltage c supplied to the coefficient multiplier circuit section 35 is changed to change the coefficient β, the DC voltage level during the pedestal period of the signal OUT can be arbitrarily adjusted. be able to.

The number of external terminals required to integrate this example circuit is four terminals 32, 36, 39 and 40, which is a reduction of one terminal compared to the five terminals of the conventional circuit, so the chip The size can be reduced.

FIG. 3 shows the voltage adder circuit section 33, AP
FIG. 3 is a circuit diagram specifically showing a circuit portion that implements an L detection circuit section 34 and a coefficient multiplier circuit section 35; In this circuit, a pair of npn type transistors 41 and 42 and 4, respectively, whose emitters are connected in common and constitute a differential pair.
3 and 44 are provided. The collectors of the transistors 41 and 43 are connected in common, and this collector common connection point 45 is connected to the positive power supply voltage V through a load resistor 46.
Connected to the cc application point. Further, the collectors of the transistors 42 and 44 are also connected in common, and this common connection point 47 is directly connected to the power supply voltage Vcc application point.

Emitter common connection point 48 of the transistors 41 and 42
is connected to the collector of an npn type transistor 49 for supplying an operating current to the differential pair consisting of both transistors 41 and 42. The emitter of this transistor 49 is connected to the ground power supply voltage Vss application point via a resistor 50, and the base is connected to the external terminal 32. A common emitter connection point 51 of the transistors 43 and 44 is connected to the collector of an npn type transistor 52 for supplying an operating current to the differential pair consisting of the transistors 43 and 44. This transistor 5
The emitter of 2 is connected to the ground power supply voltage Vs through a resistor 53.
It is connected to the s application point.

The collector of an npn type transistor 54 is connected to the collector common connection point 45, and the emitter of this transistor 54 is connected to the emitter common connection point 48. The collector of an npn type transistor 55 is connected to the power supply voltage Vss application point, and the emitter of this transistor 55 is connected to the emitter common connection point 51.
It is connected to the. In addition, both the transistors 54 and 5
5 are connected in common, and this common base is supplied with a pulse signal Vρ which is set to an O level in terms of the pedestal period. The transistors 41 and 44
A predetermined bias voltage Ve1 formed by means not shown is supplied to the base of the transistor. The control voltage V of the terminal 36 is applied to the bases of the transistors 42 and 43.
c is supplied. A predetermined bias voltage VB2 formed by means not shown is supplied to the base of the transistor 49 via a resistor 56, and a predetermined bias voltage VB2 is supplied to the base of the transistor 52.
2 is supplied via a resistor 57. Further, the inverted signal S3 of the addition output signal s3 is obtained from the collector common connection point 45.

In this configuration, since transistors 54 and 55 are turned on except during the pedestal period, the collector currents of transistors 49 and 52 flow through these transistors 54 and 55.

Here, since the collector of the transistor 55 is connected to the power supply Vcc, the collector current of the transistor 55 does not contribute to the output signal ■, and only the collector current of the transistor 55 contributes. Therefore, the video signal current component flows through this transistor 54, and an inverted signal of the input video signal is output from the connection point 45.

On the other hand, within the pedestal period, the pulse signal Vp is
When set to I level, transistors 54 and 55 are turned off, and the video signal current component and the APL component of the video signal, which is the collector current of transistor 52, are applied to the two differential pair transistors 41 and 43, and the control voltage is It flows in a state where it is added according to the value of Vc. Here, if the value of the above-mentioned control wJ voltage Vc is set to the maximum value, the transistor 42
Since transistors 42 and 43 are on, the APL component added to the video signal current component becomes maximum, and when the value of Vc is set to the minimum, transistors 42 and 43 are off, so the APL component is added to the video signal current component. The APL component is minimized.

That is, by changing the value of Vc, the β
You can change the value of

In this manner, this embodiment circuit can reduce the number of external components compared to the conventional circuit, and thus the manufacturing cost is reduced. Furthermore, when integrated circuits are implemented, there is no need to control the DC regeneration rate using an external resistor as in the past, and everything can be configured within the integrated circuit, resulting in less variation in the DC regeneration rate and stability. Further, for the same reason as above, stability against temperature changes is also sufficiently ensured.

It goes without saying that the present invention is not limited to the above-mentioned embodiments, and that various modifications can be made. For example, the voltage adder circuit section 33, the APL detection circuit section 34, and the coefficient multiplier circuit section 35 may have a configuration other than that shown in FIG. 3.

[Effects of the Invention] As explained above, in the video signal processing circuit of the present invention, it is possible to stabilize the DC reproduction rate, and it is possible to provide a video signal processing circuit that can be manufactured at a low cost.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a video signal processing circuit according to the present invention, FIG. 2 is a waveform diagram thereof, and FIG. 3 is a circuit diagram specifically showing a part of the above embodiment circuit. FIG. 4 is a configuration diagram of a conventional circuit, and FIG. 5 is a waveform diagram thereof. 33... Voltage addition circuit section, 34... APL detection circuit section, 35... Coefficient multiplier circuit section, 37... Contrast control circuit, 38... Bright amplifier circuit. Applicant's agent Patent attorney Takehiko Suzue Figure 3 Vss Vss? MoO Figure 4 Figure 5

Claims (1)

[Claims] Adding means for detecting the average level of the video signal and adding the value multiplied by an arbitrary coefficient to the pedestal period of the video signal, and keeping the DC level constant during the pedestal period of the video signal after the level addition. A video signal processing circuit comprising a clamping means for clamping.