JPH04176172A - Manufacture of non-volatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To enable a semiconductor memory device adapted for high integration to be obtained by a method wherein a lower insulating film, a nitride film, and an upper insulating film are successively laminated covering a channel region between a source and a drain above a floating gate or a nitride film and an upper insulating are successively laminated to form a composite insulating film. CONSTITUTION:A channel region 11 containing an offset region 2a is provided between a source and a drain, an ONO film 35 is laminated on all the surface of an Si substrate 10 including a floating gate 1 to cover the channel region 11 including the offset region 2a. Then, a polysilicon film 6 is laminated on all the surface. At this point, a lower oxide film 32, a silicon nitride film (SiN) 33, and an upper oxide film 34 are successively laminated to form the composite insulating ONO film 35.

Description

Detailed Description of the Invention (a) Industrial Application Field The present invention relates to a method for manufacturing a non-volatile semiconductor f2 device suitable for high integration. The insulating film in the split gate structure includes a control gate disposed through a film, a train formed in a self-aligned manner with respect to the floating gate, and a source formed from the floating gate through an offset region. This relates to a method of forming.

(b) Problems to be Solved by the Prior Art and the Invention In the conventional split gate structure, after the floating gate is formed, an SiO2 film is laminated as the insulating film above the channel region between the source and the drain.

However, since it is necessary to thicken the 5iOz film to cover the offset region, it is difficult to achieve high integration.

(c) Means and action for solving the problem This invention includes:
A floating gate, a control gate disposed on the floating gate via an insulating film, a drain formed in self-alignment with the floating gate, and a source formed from the floating gate via an offset region. When forming a nonvolatile semiconductor memory device having a split gate structure, a lower insulating layer is placed above the floating gate and above the channel region between the source and drain before laminating a conductive film for forming the control gate. A method for manufacturing a nonvolatile semiconductor memory device, characterized in that a composite insulating film is formed by sequentially stacking a nitride film, a nitride film, and an upper insulating film, or by sequentially stacking a nitride film and an upper insulating film. be.

That is, the present invention provides a nonvolatile semiconductor memory device using a split gate structure in which a floating gate is
A layer of 5 iOz
A nitride film with a higher dielectric constant than the film, specifically 5i
By forming a composite insulating film containing NI (solicon nitride film), the effective film thickness can be reduced compared to the conventional method using only the thick 8102 film. As a result, the cells can be reduced and higher integration can be achieved.

In addition, the coupling capacitance can be increased by the effective film thickness or thinner, and as a result, the potential of the /'$ floating gate can be efficiently controlled.

Furthermore, since the SiN film is used, the retention characteristics of the electrolyte can be improved.

For example, as shown in FIG. 3, the composite insulating film in this invention includes a lower oxide film 32 on a poly-Si substrate 41.
, a three-film structure in which a Noricon nitride film (SiN film) 33 and an upper oxide film 34 are sequentially laminated [hereinafter referred to as
ONONo film, as shown in Figure 4, polyS
On the i-substrate 41, a silicon nitride film 42 and a
One example is a two-layer structure in which bipartite oxide films 43 are sequentially laminated (hereinafter referred to as the No film 44).

At this time, both the lower insulating film and the upper insulating film are formed by thermal oxidation or
Alternatively, it is a SiO2 film created using a well-known technique such as a CVD method. This is, for example, S i H4
, N, 0, and He by a CVD method.

Furthermore, a silicon nitride film (SiN film) having a higher dielectric constant than the 5iOz film is also formed using a well-known technique. For example, 5iHzC12 (Tsukulorunoran) and N
It is formed by a CVD method using a mixed gas of H3.

In this invention, the ONO film and the No film are formed thinner than the conventional 5rOt film by controlling the film thickness of the 5iOz film and the SiN film using the well-known technique described above.

That is, in the case of an ONO film, the thickness of the SiN film may be equal to or greater than the sum of the thicknesses of the upper and lower S + O films. From this point of view, the thickness of the upper oxide film (Si
Ox film)...-20 to 30 people SiN film ・
...Lower oxide film (SiOx film) of 80 Å or more...
The thickness is preferably 40 Å or more.

Further, in the case of the No film, it is formed to have a much thinner film thickness than the conventional 5iO7 film. Moreover, it is preferable that the SiN film is considerably thicker than the 5iOt film of the upper insulating film.

From this point of view, the film thickness is respectively upper oxide film (Sin, film)...20 to 30. Enter Si
N film: preferably 80 Å or more.

In addition, since this invention includes the ○NO film, No film, or SiN film, it can be erased by ultraviolet rays.

When used as M, it is necessary to remove a part of the SiN film covering the floating gate. For example, Fig. 5.6 shows an EPI film in which the ONO film on the floating gate protruding from the control gate is removed in a self-aligned manner using the control gate as a mask. QM
shows.

In FIG. 5.6, the EFROM is an ONON transistor that includes a polysilicon floating gate 53 and a SiN film 54 on a Si substrate 52 that has a LOCOS film 51 that is a field oxide film.
It mainly includes an O film, a polysilicon control gate 56, and an interlayer insulating film 57 such as PSG or BPSG. From FIG. 6, it can be seen that the SiN film 54 is removed from the portion of the floating gate 53 that protrudes from the control gate 56.

In FIG. 5, reference numeral 58 indicates a resist pattern for forming an offset region.

(d) Examples The present invention will be described in detail below based on embodiments shown in the figures.

Note that this invention is not limited by this.

As shown in FIG. 1(a), a resist pattern 2 for forming an offset region is used to form a floating gate 1 and a drain 3 formed in self-alignment with the floating gate.
Then, a split gate structure Si substrate 10 having a source 4 formed from a floating gate 1 via an offset region 2a is created.

At this time, a channel region 11 including an offset region 2a between the source and drain is formed.

[
See FIG. 1(b)].

Next, a polysilicon film 6 is laminated on the entire surface [Fig.
c) Reference.

Subsequently, the polysilicon film 6 is patterned and controlled to form a polysilicon film 6a, and an interlayer insulating film 8 is further laminated via the oxide film 7 [see FIG. 1(d)].

In this way, a non-volatile memory with a split gate structure is created.

In this example, before stacking the polysilicon film 6 for the control gate, the ONONo film was formed above the floating gate l and covering the channel region II between the source and the train. 6 on the offset area 2a
It is smaller than the conventional 5if2 film.

Further, since the ONO film is superior to the 5in2 film in terms of charge retention properties, the charge retention properties can be improved.

(E) Effects of the Invention As described above, according to the present invention, when forming an insulating film between a floating gate and a control gate in a nonvolatile semiconductor memory device using a split gate structure, Since the channel region including the offset region is covered with a composite insulating film consisting of an insulating film including a SiN film with a higher dielectric constant than an oxide film, SIO is used as the insulating film between both gates. The effective film thickness can be lowered compared to the conventional method using the method, thereby making it possible to reduce the cell size and obtain a semiconductor memory device that is more suitable for higher integration. Further, the scriving capacitance can be increased by the amount that the effective film thickness is reduced, and thereby the potential of the floating gate can be efficiently controlled.

Furthermore, since the SiN film is used, charge retention characteristics can be improved.

[Brief explanation of the drawing]

FIG. 1(a) to FIG. F(d) are manufacturing process explanatory diagrams for explaining one embodiment of the present invention, and FIG. 2 is a configuration explanatory diagram showing a specific manufacturing process in the above embodiment, The AA' line arrow view in FIG. 2 corresponds to FIG. 1(c). FIG. 3 is an explanatory diagram of the main part of the above embodiment, FIG. 4 is an explanatory diagram of the main part of another embodiment of the invention, and FIG. 5 is an explanatory diagram of the main part of the embodiment.
FIG. 6, which is an explanatory diagram of the structure of the FROM, is a view taken along the line BB' in FIG. 5. l... Floating gate, 2... Resist pattern for forming offset region, 2a
-...Offset area, 3...Drain, 4 ・
...source, 6...polysilicon film (conductive film for control gate formation)
, 6a...Control gate, 11...Channel region, 35...ONO film, 44...No film. ”8-J Next V knee

Claims (1)

[Claims] 1. A floating gate, a control gate disposed on the floating gate via an insulating film, a drain formed in self-alignment with the floating gate, and an offset region from the floating gate. When forming a non-volatile semiconductor memory device with a split gate structure having a source formed through a gate, a channel between a source and a drain is formed on the floating gate before laminating a conductive film for forming a control gate. A nonvolatile insulating film characterized by forming a composite insulating film by sequentially stacking a lower insulating film, a nitride film, and an upper insulating film, or by sequentially stacking a nitride film and an upper insulating film above the region. A method for manufacturing a semiconductor memory device.