JPH0417341A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0417341A
JPH0417341A JP2121635A JP12163590A JPH0417341A JP H0417341 A JPH0417341 A JP H0417341A JP 2121635 A JP2121635 A JP 2121635A JP 12163590 A JP12163590 A JP 12163590A JP H0417341 A JPH0417341 A JP H0417341A
Authority
JP
Japan
Prior art keywords
film
semiconductor region
sio2
gate insulation
ono
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2121635A
Other languages
Japanese (ja)
Inventor
Takahiro Yamada
隆博 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2121635A priority Critical patent/JPH0417341A/en
Publication of JPH0417341A publication Critical patent/JPH0417341A/en
Pending legal-status Critical Current

Links

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

PURPOSE:To obtain a semiconductor device in buried channel type CCD structure using a thin gate insulation film without losing a maximum transfer charge quantity by using an ONO film as a gate insulation film. CONSTITUTION:A title item has a first semiconductor region 101 of a first conductive type, a second semiconductor region 102 of a second conductive type which is formed on the first semiconductor region 101, a third semiconductor region 107 of first conductive type which is formed near a surface of the second semiconductor region 102, gate insulation films 103 and 105 in ONO (SiO2/Si3N4/SiO2) structure which is formed on a surface of the third semiconductor region 107, and gate electrodes 104 and 106 which are formed on the gate insulation films 103 and 105 as main entities. For example, an ONO (SiO2/Si3N4/ SiO2) film in three-layer structure using an SiO2 film with a film thickness where current constituents within film under a high electric field directly become tunnel current as gate insulation films 103 and 105 of charge transfer elements.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は ダイナミックレンジ特性(最大電荷転送量特
性)を損なうことなく、ゲート絶縁膜を微細化(スケー
リング)したCCDを実現する半導体装置の構造に関す
るものである。
[Detailed Description of the Invention] Industrial Field of Application The present invention relates to the structure of a semiconductor device that realizes a CCD in which the gate insulating film is scaled without impairing dynamic range characteristics (maximum charge transfer characteristics). It is.

従来の技術 民生用ビデオカメラに使用されている固体撮像素子の信
号電荷転送回路として、もっとも普及している埋め込み
チャネル型CCD (参考文献:C0H1シークイン 
(Sequin)  &  M、F、   トン7°セ
yト (Tompsett)。
Conventional technology Embedded channel CCD is the most popular signal charge transfer circuit for solid-state image sensors used in consumer video cameras (Reference: C0H1 Sequin
(Sequin) & M, F, Tompsett.

“チャージ゛ トランスファー テ゛ハ゛イス (Ch
arge  Transfer  Device)”、
  アカテゝミ7り 7°レス (Academic 
 Press)  1975)  LL第3図に示すよ
うにp基板301の上部に形成されたn領域302と、
厚さToxのゲート酸化膜(約1000人の5i02)
 303の上に形成された第1層のポリシリコン・ゲー
ト電極304と、ゲート酸化膜(SiOa)  305
を隔てて形成された第2層のポリシリコン・ゲート電極
306とで構成されるものが代表的である。
“Charge transfer device (Ch.
transfer device)”,
Akatemi 7ri 7°less (Academic
Press) 1975) LL As shown in FIG. 3, an n region 302 formed on the top of a p substrate 301,
Gate oxide film with thickness Tox (approximately 1000 5i02)
A first layer polysilicon gate electrode 304 formed on 303 and a gate oxide film (SiOa) 305
A typical example is a second layer of polysilicon gate electrode 306 formed at a distance from the second layer of polysilicon gate electrode 306 .

第3図のA−A’断面に沿った熱平衡状態(全ての電圧
を印加していない時の熱平衡状態)のエネルギー・バン
ド図を第4図(a)に示す。第3図のCCDの主動作状
態で(よ n領域301に対して正の電圧(15〜20
v)がn領域302に印加されるので、エネルギー・バ
ンド図は第4図(b)に示すようになる。この時、ポリ
シリコン・ゲート電極の電圧はOvである。このゲート
電極の電圧が正方向に増せば信号電荷の蓄積状態となり
、負方向に増せば信号電荷の非蓄積状態となる。
An energy band diagram in a thermal equilibrium state (thermal equilibrium state when no voltage is applied) along the AA' cross section in FIG. 3 is shown in FIG. 4(a). In the main operating state of the CCD in FIG. 3, a positive voltage (15 to 20
v) is applied to the n region 302, so the energy band diagram becomes as shown in FIG. 4(b). At this time, the voltage of the polysilicon gate electrode is Ov. If the voltage of the gate electrode increases in the positive direction, the signal charge is accumulated, and if it increases in the negative direction, the signal charge is not accumulated.

現時点でのCCD型撮像素子(信号電荷転送回路として
CCDを用いた撮像素子)の代表として1よ 民生用の
1/2インチ40万画素CCD、  業務用の2/3イ
ンチ40万画素CCDがある。
At present, representative CCD-type image sensors (image sensors that use a CCD as a signal charge transfer circuit) include the 1/2-inch 400,000-pixel CCD for consumer use and the 2/3-inch 400,000-pixel CCD for commercial use. .

−J、1990〜91年に打ち上げ予定の「放送衛星B
5−3  (3チヤネル)」から衛星放送が本格化り、
  1997年以降に打ち上げ予定の「放送衛星B5−
4  (8チヤネル)」で複数の民放が可能になると衛
星放送の比重が地上放送より大きくなることが予想され
ており、しかL はぼ同時期にハイビジョン放送の普及
が加速していくことを考虜して、 200万画素のCC
Dを用いたハイビジョン用ビデオカメラの開発が進めら
れている。
-J, "Broadcast Satellite B" scheduled to be launched in 1990-91
Satellite broadcasting began in earnest from ``5-3 (3 channels)''.
Broadcasting satellite B5- scheduled to be launched after 1997
It is expected that satellite broadcasting will become more important than terrestrial broadcasting if multiple commercial broadcasters become possible with ``4 (8 channels)''. Be captivated by 2 million pixel CC
Development of high-definition video cameras using D is progressing.

200万画素のCCDともなると、半導体メモリのDR
AMと同様に スケーリング(微細化)の適用が不可欠
となる。とりわ1す、ゲート絶縁膜厚の微細化(よ 第
5図の計算結果(絶縁膜の厚さdか1000人と500
人の時の最大転送電荷量N51gとゲート電極の電圧V
gの関係)に示すように同じダイナミック・レンジを取
り扱うのに絶縁膜厚の小さい方がゲート電極に印加する
駆動パルスの振幅は小さくて済へ 低電圧化に有利であ
ることがわかる。
When it comes to a 2 million pixel CCD, the DR of semiconductor memory
As with AM, the application of scaling (miniaturization) is essential. In particular, miniaturization of gate insulating film thickness (calculation result in Figure 5)
Maximum transfer charge amount N51g and gate electrode voltage V when human
As shown in (relationship g), it can be seen that the smaller the thickness of the insulating film, the smaller the amplitude of the drive pulse applied to the gate electrode while handling the same dynamic range, which is advantageous in lowering the voltage.

発明が解決しようとする課題 ところ力丈 薄いゲート酸化膜(SiC2)ではよく知
られた現象として、 Si○2膜中で発生する正電荷(
正孔)がゲート電極−8iOa界面の電界を強嵌 その
結果としてFowler−Nordheim )ンネル
電流(キャリアがトンネル効果でゲート酸化膜に注入し
た後、ゲート酸化膜中を電界に従って流れることにより
生じる電流)を増加させ、この増加した電流が再びトラ
ップされた正電荷(正孔)を増加させるという正帰還作
用を引き起こすため番ミ10v以下でも絶縁破壊が生じ
る。このた敢 第5図で示された500人の薄いSiC
2は使用することができない。
Problems to be Solved by the Invention A well-known phenomenon in thin gate oxide films (SiC2) is that positive charges (
As a result, Fowler-Nordheim) tunnel current (current generated when carriers flow in the gate oxide film according to the electric field after being injected into the gate oxide film by the tunnel effect) This increased current causes a positive feedback effect in which the trapped positive charges (holes) increase again, so that dielectric breakdown occurs even at voltages below 10 V. 500 thin SiC people shown in Figure 5
2 cannot be used.

従って、スケーリング・ドライバーであるDRAMなど
では薄いSiC2より絶縁破壊特性が優れているON○
膜(Si○2/S i*N−/S ioa構成の三層膜
)が使用されている。
Therefore, in DRAM, etc., which is a scaling driver, ON○ has better dielectric breakdown characteristics than thin SiC2.
A film (three-layer film with Si○2/Si*N-/Sioa configuration) is used.

そこで、第4図(a)の5iOaを500人の薄い5i
02膜相当のONO膜に置き換えた場合の熱平衡状態(
電圧は印加していない時の熱平衡状態)のエネルギー・
バンド図を第6図(a)に示す。
Therefore, 5iOa in Figure 4(a) is
Thermal equilibrium state when replacing with ONO film equivalent to 02 film (
The energy in the thermal equilibrium state when no voltage is applied
A band diagram is shown in FIG. 6(a).

CCDが主動作状態にあり、しかもゲート電極の印加電
圧がOvの場合のエネルギー・バンド図を第6図(b)
に示す。
Figure 6(b) shows the energy band diagram when the CCD is in the main operating state and the voltage applied to the gate electrode is Ov.
Shown below.

第6図(b)に示すように n形シリコン側から下部5
i02膜601へ直接トンネリング(キャリアがゲート
酸化膜を突き抜けるような、トンネル効果現象)により
注入された正孔1;!、5isNa膜中をPoole−
Frenkel電流(窒化膜の伝導帯または価電子帯の
キャリアがトラップ準位との間を往来しなから電界に従
・って流れる電流)となって流れ 薄い上部5i02膜
603を直接トンネリングでゲート電極604側へ抜け
る。この結Jun形シリコンの表面はよりn形になろう
とするたぬ ゲート電極604の電圧を負方向に変化さ
せてもシリコン側からゲート電極へ正孔が大量に流れて
行くだけであり、蓄積状態から非蓄積状態へは変化させ
ることができなl、%  こうした現象のために ただ
単に薄いONO膜をゲート絶縁膜として採用するだけで
はCCDの最大転送電荷量が減少してしまう。
As shown in Figure 6(b), the lower part 5 from the n-type silicon side
Holes 1 injected into the i02 film 601 by direct tunneling (a tunnel effect phenomenon in which carriers penetrate through a gate oxide film);! , Poole- in the 5isNa film
Flows as a Frenkel current (a current that flows according to the electric field because carriers in the conduction band or valence band of the nitride film do not move back and forth between the trap level and the trap level) and directly tunnels through the thin upper 5i02 film 603 to form the gate electrode. Exit to the 604 side. In this case, the surface of the Jun-type silicon tends to become more n-type.Even if the voltage of the gate electrode 604 is changed in the negative direction, a large amount of holes only flow from the silicon side to the gate electrode, and the accumulation state Because of this phenomenon, simply using a thin ONO film as the gate insulating film will reduce the maximum transfer charge amount of the CCD.

本発明ζよ この様な課題に注目し 最大転送電荷量(
ダイナミック性能)を損なう事なく、薄いゲート絶縁膜
を用いた埋め込みチャネル型CCD構造の半導体装置の
提供を目的とする。
The present invention ζ focuses on these issues and aims to improve the maximum transfer charge amount (
The purpose of the present invention is to provide a semiconductor device having a buried channel type CCD structure using a thin gate insulating film without impairing dynamic performance.

課題を解決するための手段 本発明(よ 上記目的を達成するために 電荷転送領域
となるシリコン上部のn型領域の表面に正孔の蓄積領域
を形成した上で、薄い○No膜をゲート絶縁膜として用
いた埋め込みチャネル形CCD構造とする。
Means for Solving the Problems The present invention (in order to achieve the above objects) After forming a hole accumulation region on the surface of the n-type region on the upper part of silicon, which will serve as a charge transfer region, a thin ○No film is used as gate insulator. A buried channel type CCD structure is used as a film.

作用 本発明(よ 前記した構造により、CCDの主要特性の
最大転送電荷量に悪影響を与えずに薄いゲート絶縁膜と
してONO膜を採用することで、CCDのシリコン表面
のゲート絶縁膜をスケーリングすることが可能になる。
Effects of the present invention (According to the above-described structure, the gate insulating film on the silicon surface of the CCD can be scaled by using an ONO film as a thin gate insulating film without adversely affecting the maximum transfer charge amount, which is the main characteristic of the CCD. becomes possible.

実施例 以下に本発明の実施例を、図面に基づいて説明する。Example Embodiments of the present invention will be described below based on the drawings.

第1図は 本発明の実施例の半導体装置の構造を示すも
のである。図から判るようににp基板101の上部に形
成されたn領域102と、n領域102の上部表面に形
成されたp+領域107と、ゲート絶縁膜となる厚さT
 onoの○No膜103の上に形成された第1層のポ
リシリコン・ゲート電極104と、酸化膜(SiO2)
または○NO膜105を隔てて形成された第2層のポリ
シリコン・ゲート電極106とで構成される。構造上の
特徴はp十領域107がシリコン表面に形成されたこと
である。
FIG. 1 shows the structure of a semiconductor device according to an embodiment of the present invention. As can be seen from the figure, there is an n region 102 formed on the upper part of the p substrate 101, a p+ region 107 formed on the upper surface of the n region 102, and a thickness T which becomes the gate insulating film.
A first layer polysilicon gate electrode 104 formed on the ono ○No film 103 and an oxide film (SiO2)
Alternatively, it is composed of a second layer polysilicon gate electrode 106 formed with a NO film 105 in between. The structural feature is that a p-domain region 107 is formed on the silicon surface.

第1図のA−A’ 断面に沿った熱平衡状態(全ての電
圧を印加していない時の熱平衡状態)のエネルギー・バ
ンド図を第2図(a)に示す。第1図のCCDの主動作
状態では n領域101に対して正の電圧(15〜20
V)かn領域102に印加されるのて エネルギー・バ
ンド図は第4図(b)に示すようになる。この時、ポリ
シリコン・ゲート電極の電圧はOvである。p十領域1
07の存在によりシリコン表面のエネルギーはあまり高
くならないた厭 ○NO膜の両端の電界は同等の厚さの
酸化膜に比べて小さくなる。従って、厚いゲート酸化膜
の場合と同様に ゲート電極の電圧を正方向に増せば信
号電荷の蓄積状態となり、負方向に増せば信号電荷の非
蓄積状態となる。
FIG. 2(a) shows an energy band diagram in a thermal equilibrium state (thermal equilibrium state when no voltage is applied) along the AA' cross section in FIG. 1. In the main operating state of the CCD in FIG. 1, a positive voltage (15 to 20
When V) is applied to the n region 102, the energy band diagram becomes as shown in FIG. 4(b). At this time, the voltage of the polysilicon gate electrode is Ov. p ten area 1
Due to the presence of 07, the energy on the silicon surface does not become very high. ○The electric field at both ends of the NO film is smaller than that of an oxide film of equivalent thickness. Therefore, as in the case of a thick gate oxide film, if the voltage of the gate electrode is increased in the positive direction, the signal charge will be accumulated, and if it is increased in the negative direction, the signal charge will not be accumulated.

このように本発明の実施例が第4図の厚いゲート酸化膜
と同等な効果を示す理由は 窒化膜(Si3N4)  
202の価電子帯およびトラップ準位がp+領域107
の価電子帯より高いエネルギーにあるため正孔に対する
障壁となり、 p十領域(第1図の107)の正孔かO
NO膜中ヘトンネル注入されないことによる。
The reason why the embodiment of the present invention exhibits the same effect as the thick gate oxide film shown in FIG. 4 is because the nitride film (Si3N4)
The valence band and trap level of 202 are in the p+ region 107
Since the energy is higher than the valence band of
This is due to the lack of tunnel injection into the NO film.

な耘 ゲート絶縁膜としての○No膜を構成するSiO
2層に正孔が捕獲されると低電圧での絶縁破壊の原因と
なるので、SiO2両端の印加電界の増加とともにrF
owler−Nordheim トンネル電流」が流れ
るより前に「直接トンネル電流」が流れるような膜厚を
設定することも有効である。
SiO constituting the ○No film as a gate insulating film
Since the trapping of holes in the two layers causes dielectric breakdown at low voltages, rF
It is also effective to set a film thickness such that a "direct tunnel current" flows before a "owler-Nordheim tunnel current" flows.

発明の効果 本発明によれζよ 電荷転送領域の動作性能である最大
転送電荷量に悪影響を与えずに薄いゲート絶縁膜として
ONO膜を採用することが可能になるた&  CCDの
シリコン表面のゲート絶縁膜をスケーリングすることが
可能になる。この結果CCDの絶縁膜がより薄くなると
共に転送パルスの振幅も小さくなり、高画素化のための
設計指針であるスケーリングから帰結される電源電圧の
低減も可能になり、本発明がもたらす実用的な効果は極
めて太き℃も
Effects of the Invention The present invention makes it possible to use an ONO film as a thin gate insulating film without adversely affecting the maximum amount of transferred charge, which is the operating performance of the charge transfer region. It becomes possible to scale the insulating film. As a result, the insulating film of the CCD becomes thinner and the amplitude of the transfer pulse becomes smaller, making it possible to reduce the power supply voltage resulting from scaling, which is a design guideline for increasing the number of pixels. The effect is extremely strong

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例のCCD型半導体装置の構造
を示す断面医 第2図は第1図の実施例のA−A’ 断
面に沿うエネルギー・バンドは第3図は従来のCCD型
半導体装置の構造を示す断面医 第4図は第3図の従来
例のA−A’断面に沿うエネルギー・バンド図 第5図
は絶縁膜の厚さの大小がゲート電圧と最大転送電荷量の
関係に及ぼす影響を計算した結果を示すグラフ医 第6
図は薄い酸化膜と等価な○NO膜を用いた場合の第3図
の従来例のA−A’断面に沿うエネルギー・バンド図を
示す。 p基板・101、301.n領域・102、302、p
十領域・・・107、ゲート絶縁膜・・川03.104
.303.304、第1層ポリシリコン・ゲート電極・
・・104.304、第2層ポリシリコン・ゲート電極
・・・106.306゜代理人の氏名 弁理士 粟野重
孝 はか1名第 図 第 図 第 図 r−Sム (a−) 九−3t iOz alyst N S/ f (tt −,500) φ−−−(d−Sρの N5il (洸−/りρO) φ、(ダ籐lρρρ)
FIG. 1 is a cross-sectional diagram showing the structure of a CCD type semiconductor device according to an embodiment of the present invention. FIG. Figure 4 is an energy band diagram along the A-A' cross section of the conventional example in Figure 3. Figure 5 shows that the thickness of the insulating film depends on the gate voltage and the maximum amount of transferred charge. Graph doctor showing the results of calculating the influence on the relationship of
The figure shows an energy band diagram along the AA' cross section of the conventional example of FIG. 3 when a NO film equivalent to a thin oxide film is used. p-substrate・101, 301. n area・102, 302, p
Ten areas...107, Gate insulating film...River 03.104
.. 303.304, first layer polysilicon gate electrode
...104.304, second layer polysilicon gate electrode...106.306゜Name of agent: Patent attorney Shigetaka Awano iOz alyst N S/ f (tt −, 500) φ−−−(d−Sρ’s N5il (Ko−/riρO) φ, (Da rattan lρρρ)

Claims (2)

【特許請求の範囲】[Claims] (1)第1導電型の第1の半導体領域と、前記第1の半
導体領域の上部に形成された第2導電型の第2の半導体
領域と、前記第2の半導体領域の表面近傍に形成された
第1導電型の第3の半導体領域と、前記第3の半導体領
域の表面上に形成されたONO(SiO_2/Si_3
N_4/SiO_2)構造のゲート絶縁膜と、前記ゲー
ト絶縁膜上に形成されたゲート電極を主な構成要素とし
て有することを特徴とする半導体装置
(1) A first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type formed above the first semiconductor region, and a second semiconductor region formed near the surface of the second semiconductor region. a third semiconductor region of the first conductivity type, and an ONO (SiO_2/Si_3) formed on the surface of the third semiconductor region.
A semiconductor device comprising, as main components, a gate insulating film having a N_4/SiO_2) structure and a gate electrode formed on the gate insulating film.
(2)高電界下での膜内電流成分が直接トンネル電流と
なるような膜厚のSiO_2膜を用いた三層構造のON
O(SiO_2/Si_3N_4/SiO_2)膜を電
荷転送素子のゲート絶縁膜として用いることを特徴とす
る請求項1に記載の半導体装置
(2) Three-layer ON using a SiO_2 film with a thickness such that the current component in the film under a high electric field becomes a direct tunnel current
2. The semiconductor device according to claim 1, wherein an O (SiO_2/Si_3N_4/SiO_2) film is used as a gate insulating film of a charge transfer element.
JP2121635A 1990-05-11 1990-05-11 Semiconductor device Pending JPH0417341A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2121635A JPH0417341A (en) 1990-05-11 1990-05-11 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2121635A JPH0417341A (en) 1990-05-11 1990-05-11 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0417341A true JPH0417341A (en) 1992-01-22

Family

ID=14816146

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2121635A Pending JPH0417341A (en) 1990-05-11 1990-05-11 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0417341A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5302545A (en) * 1990-11-26 1994-04-12 Matsushita Electronics Corporation Method of making charge-coupled device and solid-state imaging device having an ONO transfer gate insulating film
WO2006070598A1 (en) * 2004-12-28 2006-07-06 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for manufacturing same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5302545A (en) * 1990-11-26 1994-04-12 Matsushita Electronics Corporation Method of making charge-coupled device and solid-state imaging device having an ONO transfer gate insulating film
WO2006070598A1 (en) * 2004-12-28 2006-07-06 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for manufacturing same
US7948048B2 (en) 2004-12-28 2011-05-24 Panasonic Corporation Semiconductor device and method for manufacturing same

Similar Documents

Publication Publication Date Title
JPH0458700B2 (en)
JP2724702B2 (en) Method for manufacturing charge-coupled semiconductor device
JPH0982932A (en) Solid state image sensing element
JP2002518843A (en) Lateral thin film SOI device in which the upper oxide film and the drift region are inclined
JP2816063B2 (en) Charge transfer device
JPH0417341A (en) Semiconductor device
US4809048A (en) Charge-coupled device having channel region with alternately changing potential in a direction perpendicular to charge transfer
JPS58220574A (en) Solid-state image pickup device
EP0566117A1 (en) charge transfer image pick-up device
US6891243B2 (en) Solid-state image pick-up device
JPS6259466B2 (en)
JP2996567B2 (en) Method for manufacturing solid-state imaging device
JP2909158B2 (en) Charge coupled device
JPS58161367A (en) Charge coupling element and solid-state image pickup element therewith
Kitano et al. A 1.75μm Square Pixel IT-CCD Having a Gate Oxide Insulator Composed by Single-Layer Electrode Structure
JPH10150184A (en) Charge transfer device and its manufacture
JPH0661469A (en) Ccd imaging element
JPS6351545B2 (en)
JPH04115575A (en) Solid state image pickup device
JPH0423331A (en) Semiconductor device
JPS5936833B2 (en) semiconductor equipment
JPH0425033A (en) Semiconductor device and manufacture thereof
JPH0513470A (en) Charge coupled device
JP3302189B2 (en) Charge-coupled device
JP3303384B2 (en) Solid-state imaging device and driving method thereof