JPH04171823A - Wiring structure and manufacture thereof - Google Patents
Wiring structure and manufacture thereofInfo
- Publication number
- JPH04171823A JPH04171823A JP29950090A JP29950090A JPH04171823A JP H04171823 A JPH04171823 A JP H04171823A JP 29950090 A JP29950090 A JP 29950090A JP 29950090 A JP29950090 A JP 29950090A JP H04171823 A JPH04171823 A JP H04171823A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- conductor
- line
- present
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000004020 conductor Substances 0.000 claims abstract description 73
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 17
- 239000010931 gold Substances 0.000 claims description 17
- 229910052737 gold Inorganic materials 0.000 claims description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 238000007747 plating Methods 0.000 claims description 8
- 238000009713 electroplating Methods 0.000 claims description 4
- 230000005540 biological transmission Effects 0.000 abstract description 7
- YTCQFLFGFXZUSN-BAQGIRSFSA-N microline Chemical group OC12OC3(C)COC2(O)C(C(/Cl)=C/C)=CC(=O)C21C3C2 YTCQFLFGFXZUSN-BAQGIRSFSA-N 0.000 description 16
- 238000000034 method Methods 0.000 description 10
- 239000000758 substrate Substances 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000004891 communication Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000000992 sputter etching Methods 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
Landscapes
- Electroplating Methods And Accessories (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は通信用混成ＩＣ等の半導体集積回路の配線の構
造およびその製法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a wiring structure of a semiconductor integrated circuit such as a communication hybrid IC and a method of manufacturing the same.
従来、通信用混成ＩＣ等の半導体集積回路の配線の構造
としてはストリップ形、コプレナ形、スロット形なとの
マイクロ線路による構造か知られている。これらのマイ
クロ線路による構造は、例えば、Ｒａｙｍｏｎｄ Ｓ、
Ｐｅｎｇｅｌｌｙ、 “Ｍｉｃｒｏｗａｖｅ Ｆｉｅ
ｌｄ−Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒｓ Ｔｈｅ
ｏｒｙ、 Ｄｅｓｉｇｎ ａｎｄ Ａｐｐｌｉｃａ−ｔ
ｉｏｎｓ”、 Ｒｅ５ｅａｒｃｈ ５ｔｕｄｉｅｓ Ｐ
ｒｅｓｓ、 Ａ Ｄｉｖｉｓｉｏｎ ｏｆＪｏｈｎ Ｗ
ｉｌｅｙ ＆ ５ｏｎｓ Ｌｔｄ、 １９８４．に記載
されている通りである。これらは共に−様な厚さの金属
導体をパタン化することによって形成されていた。2. Description of the Related Art Hitherto, known wiring structures for semiconductor integrated circuits such as communication hybrid ICs include strip-type, coplanar-type, and slot-type micro-line structures. These micro-line structures are, for example, Raymond S.
Pengelly, “Microwave Fie.
ld-Effect Transistors The
ory, Design and Application
ions”, Re5earch 5tudies P
ress, A Division of John W
iley & 5ons Ltd, 1984. As stated in Both of these were formed by patterning metal conductors of varying thicknesses.
しかし、従来の配線では配線ないしそのグランド線の各
々対向する導体端に電流が集中し、実効的な配線抵抗の
増大および伝送損失の増大を招いていた。However, in conventional wiring, current concentrates on opposing conductor ends of each wiring or its ground line, resulting in an increase in effective wiring resistance and an increase in transmission loss.
このため、特に配線の幅を大きくしても、導体端への電
流集中効果のため抵抗低減効果は比較的小さく、伝送損
失の低減を阻んでいた。For this reason, even if the width of the wiring is particularly increased, the effect of reducing resistance is relatively small due to the effect of current concentration at the conductor end, which hinders the reduction of transmission loss.
本発明の目的は、通信用混成ＧａＡｓ ＩＣ等の半導体
集積回路において配線抵抗および伝送損失を低コストに
低減し、高性能ないし低電力な、また高密度ないし小形
の回路を提供する配線構造およびその製法を提供するこ
とである。The object of the present invention is to provide a wiring structure and its wiring structure that can reduce wiring resistance and transmission loss at low cost in semiconductor integrated circuits such as hybrid GaAs ICs for communications, and provide high-performance, low-power, high-density, and small-sized circuits. The purpose is to provide a manufacturing method.
本発明は配線抵抗および伝送損失の低減を、特に配線内
で電流の集中する導体端での導体の厚みをそのほかの導
体部分より大きくすることによって実現することを特徴
とする。このことによって、通信用混成ＧａＡｓＩＣ等
の半導体集積回路の高性能化ないし低電力化を行なえる
。The present invention is characterized in that wiring resistance and transmission loss are reduced by making the thickness of the conductor larger, particularly at the conductor end where current is concentrated within the wiring, than at other conductor parts. This makes it possible to improve the performance and reduce the power consumption of semiconductor integrated circuits such as hybrid GaAs ICs for communications.
また、この配線の製法として導体端にのみ厚い金メッキ
を施す技術を用いることによって、導体全域に渡って金
メッキを施す場合に比べ配線抵抗の低減化を低コストに
図ることができる。更に、この配線抵抗低減に基づき配
線導体の幅を従来より小さくすることが可能であり、こ
れによって、回路の高密度化ないし小形化を図ることか
できる。また特に、インダクタの形成においてこの配線
抵抗の低減化に基づきより細い配線導体によって形成で
きることから小形のインダクタか実現できる。更に、低
抵抗のインダクタの実現によって、従来個別素子でしか
構成できなかったバンド・パス・フィルタをマイクロ・
チップ上に形成できる可能性かある。従って、本発明の
構成は下記に示す通りである。即ち、本発明は、配線の
端部を中央部分よりも厚くすることを特徴とする配線構
造に関するものであり、或いはまた、
パタン化された第１の導体配線を形成した後、全面に第
２の導体膜を付着させ、この上にフォト・レジストで第
１の導体配線の端部か穴となるようにパタン形成し、次
にこのレジストの穴のなかに電解メッキ法によって第２
の導体膜を電極として金を成長させ、この後、フォト・
レジストおよび第２の導体膜の金メッキ以外の部分を除
去することを特徴とする配線の製法としての構成を有す
るものである。Further, by using a technique for manufacturing this wiring in which thick gold plating is applied only to the ends of the conductor, it is possible to reduce the wiring resistance at a lower cost than when gold plating is applied to the entire conductor. Furthermore, based on this reduction in wiring resistance, it is possible to make the width of the wiring conductor smaller than in the past, thereby making it possible to increase the density or downsize the circuit. In particular, when forming an inductor, it is possible to form a smaller inductor because it can be formed using thinner wiring conductors based on this reduction in wiring resistance. Furthermore, by creating low-resistance inductors, band-pass filters that could previously only be constructed using individual elements can now be used as micro-band-pass filters.
There is a possibility that it can be formed on a chip. Therefore, the configuration of the present invention is as shown below. That is, the present invention relates to a wiring structure characterized in that the end portions of the wiring are made thicker than the central portion, or alternatively, after forming a patterned first conductor wiring, a second conductor wiring is formed on the entire surface. A conductor film is deposited on this film, a photoresist pattern is formed on this film to form the ends or holes of the first conductor wiring, and then a second conductor film is formed in the holes of this resist by electrolytic plating.
Gold is grown using the conductive film as an electrode, and then photo-coated.
This method is configured as a wiring manufacturing method characterized by removing the resist and the portions of the second conductor film other than the gold plating.
以下、実施例を用いて本発明による配線の構成および製
法を説明する。Hereinafter, the structure and manufacturing method of the wiring according to the present invention will be explained using Examples.
まず第６図に従来の配線の構造を示した。第６図は従来
のストリップ形マイクロ線路である。基板ｌ及び誘電体
膜２の上に形成された接地導体３に対して、誘電体膜４
を挟んで中心導体５か形成されている。ここで、中心導
体５は中心部と端部５ａ、５ｂの厚さが同じ平坦な導体
である。First, FIG. 6 shows a conventional wiring structure. FIG. 6 shows a conventional strip-type microline. A dielectric film 4 is connected to a ground conductor 3 formed on a substrate l and a dielectric film 2.
A center conductor 5 is formed with the center conductor 5 sandwiched therebetween. Here, the center conductor 5 is a flat conductor having the same thickness at the center and at the ends 5a, 5b.
第７図は第６図のストリップ形マイクロ線路におけるス
トリップ導体および接地導体の表面上の電流分布を示す
図である。図示されるように、中心導体５の電流は特に
中心部に比べ端部５ａおよび５ｂに集中する。FIG. 7 is a diagram showing the current distribution on the surfaces of the strip conductor and the ground conductor in the strip type microline of FIG. 6. As shown, the current in the center conductor 5 is particularly concentrated at the ends 5a and 5b compared to the center.
また、第８図に示されるマイクロ線路はコプレナ形マイ
クロ線路と呼ばれるもので、接地導体３（グランド）と
線路導体５を同一平面上に設け、この２種の導体間に電
界を加えて電磁波を伝搬させる。この線路は平面構造で
ある点、小形、軽量、経済的で半導体回路との適合性に
優れていることからマイクロ波混成回路では広く用いら
れている。The microline shown in Fig. 8 is called a coplanar microline, in which a ground conductor 3 (ground) and a line conductor 5 are provided on the same plane, and an electric field is applied between these two types of conductors to generate electromagnetic waves. Propagate. This line is widely used in microwave hybrid circuits because it has a planar structure, is small, lightweight, economical, and has excellent compatibility with semiconductor circuits.
また、第９図に示されるマイクロ線路は２つの対向する
導体膜６から成るスロット形マイクロ線路と呼ばれるも
のである。The microline shown in FIG. 9 is a so-called slot-type microline consisting of two opposing conductor films 6.
このようにマイクロ線路には種々の構造があるか、従来
のマイクロ線路では基本的に、線路ないしグランドが平
面的な導体から構成されている点では同じである。この
平面性のため、線路の幅を広くしても、第７図に示した
ように、線路内で電流は対向電極に近い導体端に集中し
てしまい、配線抵抗は主として線路の導体端の厚みで大
きく律則される。As described above, micro-lines have various structures, but conventional micro-lines are basically the same in that the line or ground is constructed from a planar conductor. Because of this flatness, even if the width of the line is widened, the current in the line will concentrate at the conductor end near the counter electrode, as shown in Figure 7, and the wiring resistance will mainly be at the conductor end of the line. It is largely determined by the thickness.
これに対し、本発明による配線の構造を第１図の実施例
にて説明する。In contrast, the wiring structure according to the present invention will be explained using the embodiment shown in FIG.
（実施例１）
第１図は本発明による配線の構成例であって、従来の第
７図の配線を改良したものである。第１図において、１
は基板、３は接地導体、５は中心導体、６は第１の電導
体膜、９は金（メッキ形成）である。すなわち、第７図
の配線で電流の集中する導体端のみを、他の領域に比べ
厚くしている。これによって、特に電流の集中する導体
端の配線抵抗が低減されるため、伝送損失は大きく低減
される。なお、ここではコプレナ形の線路を例として本
発明の配線の構成を示したが、前述したように、ストリ
ップ形やスロット形、更に両平面線路といった種々の線
路についても、同様の構造か可能である。（第２図、第
３図参照）
第２図は本発明による配線の第２の構造であって、第６
図の配線を改良したものである。第２図において１は基
板、２．４は誘電体膜、３は接地導体、５は中心導体、
９は金（メッキ形成）である。(Example 1) FIG. 1 shows an example of a wiring configuration according to the present invention, which is an improvement on the conventional wiring shown in FIG. 7. In Figure 1, 1
3 is a substrate, 3 is a ground conductor, 5 is a center conductor, 6 is a first conductor film, and 9 is gold (plated). That is, in the wiring shown in FIG. 7, only the conductor ends where current is concentrated are made thicker than other areas. This reduces the wiring resistance, particularly at the ends of the conductor where current is concentrated, and thus greatly reduces transmission loss. Although the wiring configuration of the present invention is shown here using a coplanar line as an example, as mentioned above, a similar structure is possible for various lines such as a strip type, a slot type, and even a double-plane line. be. (See FIGS. 2 and 3) FIG. 2 shows the second structure of the wiring according to the present invention.
This is an improved version of the wiring shown in the figure. In Fig. 2, 1 is a substrate, 2.4 is a dielectric film, 3 is a ground conductor, 5 is a center conductor,
9 is gold (plated).
第３図は本発明による配線の第３の構造であって第９図
の配線を改良したものである。第３図において１は基板
、６は第２の電導体膜、９は金（メッキ形成）である。FIG. 3 shows a third wiring structure according to the present invention, which is an improved version of the wiring shown in FIG. In FIG. 3, 1 is a substrate, 6 is a second conductor film, and 9 is gold (plated).
また、第４図はスパイラル・インダクタの配線に本発明
を適用した例であるが、この場合もインダクタ抵抗を低
減できることから、低抵抗のインダクタか実現できる。Further, FIG. 4 shows an example in which the present invention is applied to the wiring of a spiral inductor, and since the inductor resistance can also be reduced in this case, an inductor with low resistance can be realized.
第４図において１は基板、６は第２の電導体膜、９は金
（メッキ形成）である。更に、インダクタでは小形化を
図るため配線幅を小さくすると、通常は抵抗か増加して
しまうか、本発明を用いれば、抵抗の増大かなく小形化
を図ることかできる。In FIG. 4, 1 is a substrate, 6 is a second conductive film, and 9 is gold (plated). Furthermore, in an inductor, if the wiring width is reduced in order to reduce the size, the resistance usually increases, but by using the present invention, the size can be reduced without increasing the resistance.
更に、低抵抗、小形のインダクタを用いれば、従来、個
別素子でしか形成できず、各種素子のモノリシック化を
阻んでいたバンド・バス・フィルタを、マイクロ・チッ
プ上に形成できる可能性もある。Furthermore, by using low-resistance, small-sized inductors, it may be possible to form band bus filters on microchips, which could previously be formed only with individual elements, which prevented monolithicization of various elements.
第１図乃至４図に示した本発明による線路で、特に、線
路の導体端の厚み増加分りに着目すると、線路の導体中
心での厚みｔに比較して、マイクロ・ストリップ線路Ｉ
：は、ｈ＜２ ｔか、コプレナ形線路ないしスロット形
線路には、ｈ＞２ｔか、
スパイラル・インダクタには、ｈ〉〉ｔか、比較的効果
的な値である。In the line according to the present invention shown in Figs. 1 to 4, if we pay particular attention to the increase in thickness at the conductor end of the line, compared to the thickness t at the conductor center of the line, the microstrip line I
: is a relatively effective value: h<2t, h>2t for a coplanar line or slot line, and h>>t for a spiral inductor.
次に２本発明による、配線の製法について説明する。Next, two methods of manufacturing wiring according to the present invention will be explained.
（実施例２）
第５図（ａ）乃至（ｄ）は本発明による配線の製作工程
例を示したものである。第５図においてｌは基板、３は
接地導体、５は中心導体、６は第１の電導体膜、７は第
２の電導体膜、８はマスク（フォト・レジスト）、９は
金（メッキ形成）である。以下第５図（ａ）乃至（ｄ）
を参照して製作工程を詳述する。(Example 2) FIGS. 5(a) to 5(d) show an example of the manufacturing process of wiring according to the present invention. In Fig. 5, l is the substrate, 3 is the ground conductor, 5 is the center conductor, 6 is the first conductor film, 7 is the second conductor film, 8 is the mask (photoresist), and 9 is gold (plated). formation). Below, Figures 5 (a) to (d)
The manufacturing process will be explained in detail with reference to .
（ａ） リフトオフないしイオンミリングのプロセス技
術を用いてパタン化されたＩＥＩの導体配線６（接地導
体３および中心導体５を含む）を形成する。(a) Patterned IEI conductor wiring 6 (including ground conductor 3 and center conductor 5) is formed using lift-off or ion milling process technology.
（ｂ）全面に第２の導体膜７を付着させ、この上フォト
・レジスト８で第１の導体配線の端部か穴となるように
パタン形成する。この時のフォト・レジストとしては、
例えばシブレイ社のＴＦ−２０等の厚膜レジストを用い
ることによって、〜ｌＯμｍの厚みを持たせることがで
き、メッキ法によって形成する金の厚みを同程度とする
ことかできる。(b) A second conductor film 7 is deposited on the entire surface, and a photoresist 8 is formed on the second conductor film 7 to form a pattern so as to form a hole at the end of the first conductor wiring. The photoresist at this time was
For example, by using a thick film resist such as Sibley's TF-20, a thickness of ~10 μm can be obtained, and the thickness of gold formed by plating can be made to be approximately the same.
（Ｃ）このレジストの穴のなかに電解メッキ法によって
金９を厚く成長させ、
（ｄ）この後、フォト・レジストおよび第２の導体膜７
の穴パタン以外の部分を、ドライエツチングやイオン・
ミリング等によって除去する。(C) Gold 9 is grown thickly in the holes of this resist by electrolytic plating, (d) After this, the photoresist and second conductor film 7 are grown.
The area other than the hole pattern is dry-etched or ion-etched.
Remove by milling etc.
なお、（ｂ）において述へたメッキ用マスクとしては、
フォト・レジスト以外にも、Ｓ１０．やＳｉＮおよびポ
リイミドなどの絶縁膜をパタン形成して用いることも可
能である。In addition, as the plating mask mentioned in (b),
In addition to photoresist, S10. It is also possible to pattern and use an insulating film made of SiN, polyimide, or the like.
本発明の手法は配線の上の全域に金を付着ないし成長さ
せる場合と比較して、必要とする金の総体積が少ないの
て製作コストを下げることかてきる。Compared to the case where gold is deposited or grown over the entire area above the wiring, the method of the present invention requires less total volume of gold, thereby reducing manufacturing costs.
本発明は、配線抵抗を低減し、低コストで半導体集積回
路の性能を向上させ、回路を低電力化ないし高密度化な
いし小形化するにも有効である。The present invention is also effective in reducing wiring resistance, improving the performance of semiconductor integrated circuits at low cost, and reducing power consumption, high density, and miniaturization of circuits.
第１図は本発明による配線構造図、第２図は本発明によ
る別の配線構造例、第３図は本発明による更に別の配線
構造例、第４図は本発明によるスパイラル・インダクタ
の配線構造例であって、（ａ）は平面図、（ｂ）は断面
図。第５図（ａ）乃至（ｄ）は本発明による配線の製作
工程図であって、（ａ）第１の導体配線パタンの形成工
程（リフトオフないしイオンミリング）、（ｂ）第２の
導体膜の付着（全面）と、フォト・リソグラフィー工程
（第１の導体配線の端部か穴となるようレジスト・パタ
ン形成）、（Ｃ）電解メッキ法による全成長工程、（ｄ
）フォト・レジストおよび第２の導体膜の金メッキ以外
の部分をドライエツチングやイオン・ミリング等により
除去する工程、をそれぞれ表している。
第６図は従来の配線構造例（ストリップ形マイクロ線路
）、第７図は第６図のストリップ形マイクロ線路におけ
るストリップ導体および接地導体の表面上の電流分布を
示す図であり、
第８図は従来の別の配線構造例（コプレナ形マイクロ線
路）である。
第９図は従来の更に別の配線構造例（スリ・ノド形マイ
クロ線路）である。
Ｉ・・・・基板、２・・・・誘電体膜、３・・・・接地
導体、４・・・・誘電体膜、５・・・・中心導体、５ａ
、５ｂ・・・・中心導体の縁端部、６・・・・第１の電
導体膜、７・・・・第２の電導体膜、８・・・・マスク
（フォト・レジスト）、９・・・・金（メッキ形成）特
許出願人 日本電信電話株式会社
代 理 人 弁理士 玉蟲久五部
本発明による配線
第１図
本発明による別の配線
第２図
本発明による更に別の配線
第３図
第４図
本発明による配線の製作工程図
第５図
従来の配線構造例（ストリップ形マイクロ線路）第６図
第６図のストリｙブ形マイクロ線路におけるストリ・ノ
ブ導体および接地導体の表面上の電流分布を示す図
第７図
５中ル１導体 ３撞地導体
従来の別の配線構造例（コプレナ形マイクロ線路）第８
図
従来の更に別の配線構造例（スリント影マイクロ線路）
第９図FIG. 1 is a wiring structure diagram according to the present invention, FIG. 2 is another example of the wiring structure according to the invention, FIG. 3 is still another example of the wiring structure according to the invention, and FIG. 4 is the wiring of a spiral inductor according to the invention. A structural example, in which (a) is a plan view and (b) is a cross-sectional view. FIGS. 5(a) to 5(d) are process diagrams for manufacturing wiring according to the present invention, in which (a) forming a first conductor wiring pattern (lift-off or ion milling); (b) forming a second conductor film; (all over the surface), photolithography process (forming a resist pattern to form the end or hole of the first conductor wiring), (C) entire growth process using electrolytic plating method, (d
) The process of removing the photoresist and the portions of the second conductive film other than the gold plating by dry etching, ion milling, etc. FIG. 6 is an example of a conventional wiring structure (strip-type micro-line), FIG. 7 is a diagram showing the current distribution on the surface of the strip conductor and ground conductor in the strip-type micro-line of FIG. 6, and FIG. This is another example of a conventional wiring structure (coplanar micro line). FIG. 9 shows yet another example of a conventional wiring structure (slip throat type micro line). I...Substrate, 2...Dielectric film, 3...Ground conductor, 4...Dielectric film, 5...Center conductor, 5a
, 5b...Edge of center conductor, 6...First conductor film, 7...Second conductor film, 8...Mask (photoresist), 9 ...Gold (plating formation) Patent Applicant Nippon Telegraph and Telephone Co., Ltd. Representative Patent Attorney Gobu Tamamushi Wiring according to the present invention Figure 1 Another wiring according to the present invention Figure 2 Still another wiring according to the present invention Fig. 3 Fig. 4 Manufacturing process diagram of the wiring according to the present invention Fig. 5 Conventional wiring structure example (strip type micro line) Fig. 6 Surface of strip/knob conductor and ground conductor in the strip type micro line shown in Fig. 6 Figure 7 shows the current distribution above. Figure 5: 1 conductor, 3 twisted conductors, another conventional wiring structure example (coplanar micro line), No. 8
Figure: Another example of conventional wiring structure (slint shadow micro line)
Figure 9
Claims (2)
とする配線構造。(1) A wiring structure characterized by making the ends of the wiring thicker than the center.
面に第２の導体膜を付着させ、この上にフォト・レジス
トで第１の導体配線の端部が穴となるようにパタン形成
し、次にこのレジストの穴のなかに電解メッキ法によっ
て第２の導体膜を電極として金を成長させ、この後フォ
ト・レジストおよび第２の導体膜の金メッキ以外の部分
を除去することを特徴とする配線の製法。(2) After forming the patterned first conductor wiring, a second conductor film is attached to the entire surface, and patterned with photoresist on top of this so that the ends of the first conductor wiring become holes. Then, gold is grown in the holes of this resist by electrolytic plating using the second conductor film as an electrode, and then the photoresist and the parts of the second conductor film other than the gold plating are removed. Characteristic wiring manufacturing method.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29950090A JP2963189B2 (en) | 1990-11-05 | 1990-11-05 | Wiring structure of micro line and its manufacturing method |
| US07/787,136 US5281769A (en) | 1990-11-05 | 1991-11-04 | Dewall plating technique |
| US08/133,211 US5639686A (en) | 1990-11-05 | 1993-10-07 | Method of fabricating circuit elements on an insulating substrate |
| US08/449,277 US5550068A (en) | 1990-11-05 | 1995-05-24 | Process of fabricating a circuit element for transmitting microwave signals |
| US08/608,520 US5652157A (en) | 1990-11-05 | 1996-02-28 | Forming a gate electrode on a semiconductor substrate by using a T-shaped dummy gate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29950090A JP2963189B2 (en) | 1990-11-05 | 1990-11-05 | Wiring structure of micro line and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04171823A true JPH04171823A (en) | 1992-06-19 |
| JP2963189B2 JP2963189B2 (en) | 1999-10-12 |
Family
ID=17873384
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29950090A Expired - Lifetime JP2963189B2 (en) | 1990-11-05 | 1990-11-05 | Wiring structure of micro line and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2963189B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009152406A (en) * | 2007-12-20 | 2009-07-09 | Panasonic Corp | Inductor and method of manufacturing the same |
| US9698023B2 (en) | 2014-09-10 | 2017-07-04 | Sumitomo Electric Industries, Ltd. | Traveling-wave amplifier |
-
1990
- 1990-11-05 JP JP29950090A patent/JP2963189B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009152406A (en) * | 2007-12-20 | 2009-07-09 | Panasonic Corp | Inductor and method of manufacturing the same |
| US9698023B2 (en) | 2014-09-10 | 2017-07-04 | Sumitomo Electric Industries, Ltd. | Traveling-wave amplifier |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2963189B2 (en) | 1999-10-12 |
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