JPH04170788A - Memory - Google Patents

Abstract

PURPOSE:To balance capacities between normal bit lines by using only one bit line by forming bit lines to be provided at the ends of adjacent memory arrays as a pair, and forming a dummy bit line pair. CONSTITUTION:When dummy bit line pair 10 are formed of one bit line provided at the end of each of adjacent first, second, memory arrays having a plurality of bit line pairs 3, capacities 4 between the bit lines 3a and 3b of the bit line pairs 3 are balanced. With the configuration using the one bit line, increase in a layout area is suppressed, operation is stabilized, and operating margin is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a memory device, and in particular, in order to balance the parasitic capacitance between each bit line connected to a memory array, This is suitable for use in forming dummy bit line pairs.

<Summary of the Invention> The memory device of the present invention includes a dummy bit line pair provided at the end of each memory array in order to balance parasitic capacitance between bit lines connected to the memory array. By configuring the memory array with bit lines provided at the respective ends of one adjacent memory array and the other memory array, the layout area increases by providing a dummy bit line pair. This is a memory device that can maintain a good balance of capacitance of regular bit lines while minimizing the amount of noise.

<Prior Art> For example, a memory device such as a DRAM has a sense amplifier, an equalization circuit, a precharge circuit, a memory array, and a memory array.
It is composed of circuits such as column selectors. Connections between the memory array and other circuits are made by bit line pairs consisting of bit lines. Therefore, in such a memory device, a plurality of focus lines and bit lines are provided, and line capacitance is formed parasiticly in these bit lines and bit lines. Of course, it is better that the capacitances between the bit lines are smaller, but when considering the operating margin of the sense amplifier, it is desirable that the bit line capacitances be equal to each other.

However, as shown in the configuration diagram of a conventional memory device in FIG. 3, the size of the inter-bit line capacitance 4 is unbalanced depending on the position where the bit lines are wired. That is, the memory device of FIG. 3 has a first memory array 1, a second memory array 1,
A plurality of memory arrays such as memory array 2 are provided, and a plurality of precharge circuits A, sense amplifiers B, etc. are connected to each memory array via bit line pairs 3. In this case, the codes IB, IC, 2B, 2
In bit line pair 3 provided at the position marked C, there are always other bit lines on both sides of each bit line, so
The parasitic capacitances between the bit lines are equal to each other. However, a bit line pair, labeled IA, located at the end of each memory array.

In the case of bit line pair 3 arranged at the position marked 2A, there is no other bit line on one side, so the parasitic capacitance between the bit lines cannot be balanced, and the parasitic capacitance between the bit line and the bit line increases. will not be equal. For this reason, for example, when equalizing (shorting the bit lines) after sensing is completed, the %V
The voltage would be cc, but in this case, since the capacitance is not balanced, it becomes AVcc±α, which causes the disadvantage that the operating margin decreases.

In order to solve this problem, as shown in FIG. 4, a memory device may be constructed by arranging a dummy bit line pair 20 at the end.

<Problems to be Solved by the Invention> In the case of FIG. 4, since the dummy bit line pair 20 is provided at the end of each memory array 1.2, there are other bit lines on both sides of the regular focus line. will definitely exist. Therefore, in the case of the memory device of FIG. 4, it is possible to reliably balance the line capacitances of the regular bit lines, and it is possible to prevent the above-mentioned disadvantages such as a reduction in the operating margin. However, if the dummy bit line pairs 20 are arranged at the ends of the memory arrays in this way, two dummy bit line pairs 20 (four in terms of the number of bit lines) are always required between adjacent memory arrays. Therefore, there is an inconvenience that the layout area increases accordingly.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to minimize the increase in layout area due to dummy focus lines provided to balance the line capacitance of regular bit lines.

<Means for Solving the Problems> The memory device of the present invention has the following functions for retaining data:
In a memory device, a plurality of memory arrays configured by arranging memory cells in an array are provided, and a plurality of bit and bit lines for transmitting data are connected to the memory array, Among the bit lines connected to each of the memory arrays, the first bit line connected to the end of the memory array, and the memory array adjacent to the memory array to which the first bit line is connected. At the end, a dummy bit line pair is formed by the first bit line and a second bit line wired in parallel, and the bit line pair is continuous between each memory array. I try to make it exist.

<Operation> A dummy bit line is formed to balance the line capacitance by pairing the bit lines provided at each end of one adjacent memory array and the other memory array. form a pair. This makes it possible to balance the line-to-line capacitance of regular bit lines just by using one bit line, and by providing a dummy bit line pair, the layout area can be reduced. The increase can be kept to a minimum.

<Embodiment> FIG. 1 is a block diagram of main parts of a memory device showing an embodiment of the present invention.

As is clear from FIG. 1, the memory device of this embodiment is
A plurality of memory arrays such as a first memory array 1, a second memory array 2, etc. are provided, and a large number of precharge circuits A, sense amplifiers B, etc. are connected to these memory arrays 1.2, respectively. has been done. These precharge circuits A, sense amplifiers B, etc. are connected to each memory array 1.2 by a bit line pair 3 consisting of a bit vi3a and a bit line 3b. Further, the sense amplifier B is connected to a data hummer 6 via a column selector 5.

In this way, when a plurality of bit lines 3a and 3b are wired in parallel, an inter-bit line capacitance 4 is parasitically formed between each bit line and the focus line, as shown by the broken line in FIG. be done. If the sizes of the inter-bit line capacitances 4 are uneven, the above-mentioned problems will occur, so it is necessary to make the sizes of the inter-bit line capacitances 4 the same.

In order to make the size of the inter-bit line capacitance 4 the same, dummy bit line pairs are arranged. In this embodiment, the dummy bit line pairs are arranged as follows. The line capacitances 4 of the regular bit lines are set to have the same size.

That is, dummy bit lines 10a are wired at the ends of one of the memory arrays 1 provided adjacent to each other.

Further, at the end of the other memory array 2, a dummy bit line 10b is wired in parallel to the dummy bit line 10a, and these bit lines 10a and 10b form a dummy bit line pair 10. By forming the dummy bit line pairs 10 in this way, it is possible to prevent discontinuous bit line pairs from occurring between each memory array as shown in FIG.

Therefore, in a regular bit line, the magnitude of the line capacitance 4 can be made the same for all the focus lines, and stable operation can be obtained. Moreover, in this embodiment, each memory array 1.2 has one dummy bit line.
Since the capacitance 4 between the bit lines is balanced by simply wiring each bit line, the area required to provide the dummy bit line pairs 10 can be significantly reduced compared to the conventional method. 10, the increase in layout area can be minimized.

Next, a second embodiment of the present invention will be described in detail with reference to the main part configuration diagram of the memory device shown in FIG.

In the case of this second embodiment as well, the first memory array 1, the second
A plurality of memory arrays such as memory array 2 to memory array n are provided, and a word line driver section 11 is connected to the memory array n provided at the end to form a memory device.

Recently, when configuring such a memory device, it has become common to provide two layers of the same word line. When two layers of the same word line are provided, one of the two layers uses a wiring material with a small resistance value, such as aluminum A]. In addition, by dividing the memory array into several parts for one memory mat and shorting the word lines of the two layers at the joints between the divided parts,
By shunting the original word line with a wire with a low resistance value, the time constant becomes small and high-speed operation can be performed. In a memory device configured in this manner, it is particularly susceptible to the adverse effects of unbalanced line capacitance due to high-speed operation, so it is particularly necessary to provide a dummy bit line pair 10 to balance the bit line capacitance 4. It is. Therefore, when providing the dummy bit line pair 10 for each word line shunt section 11 indicated by the arrow 12 in FIG. 2, if the dummy bit line pair 10 is provided in the conventional manner, the area of the layout due to the dummy bit line pair will increase significantly. . However, if the dummy bit line pair 10 according to the present invention is applied to each word line shunt section 11, it is possible to suppress the increase in layout area due to the provision of the dummy bit line pair, thereby achieving both stable operation and miniaturization. This requirement can be satisfactorily achieved.

<Effects of the Invention> As described above, the present invention pairs the bit lines provided at the ends of one memory array and the other memory array adjacent to each other to form dummy bit lines. The above dummy bit line pair prevents discontinuity in the distance between the bit line pairs between memory arrays, so only one focus line is used for one memory array. This allows you to balance the line capacitance of regular bit lines, and by providing bit line pairs, you can minimize the increase in layout area and obtain stable operating performance, increasing the operating margin. It can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of main parts of a memory device showing one embodiment of the present invention, FIG. 2 is a block diagram of main parts of a memory device showing a second embodiment, and FIG. 3 is a diagram of a conventional memory device. The main part configuration diagram, Figure 4, is
FIG. 2 is a configuration diagram of main parts of a memory device showing a conventional dummy bit line pair. ■...First memory array. 2...Second memory array. 3...Bit line pair, 3a, 3b bit lines. 4...Capacitance between bit lines. 10...Dummy bit line pair. 10a, 10b...Dummy bit lines. Patent applicant Sony Corporation agent Patent attorney Funa Hashikuni Nori 2nd capsule M! ,
fV's Kumoso Thorn 1 Figure 2

Claims (1)

[Claims] A plurality of memory arrays configured by arranging memory cells in an array for holding data are provided, and a plurality of bit lines for transmitting data are provided in the memory array. In the connected memory device, among the bit lines connected to each of the memory arrays, the first bit line connected to the end of the memory array is connected to the first bit line. By forming a dummy bit line pair with a second bit line wired in parallel with the first bit line at the end of the memory array adjacent to the memory array, each memory array can be connected to the other memory array. 1. A memory device characterized in that a bit line pair exists continuously even between the bit lines.