JP3204386B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device for simultaneously selecting two digit line pairs of two memory cells in the same selected word to read and write 2-bit data, and in particular, to the digit line pair and a read data line. The present invention relates to a semiconductor memory device having a read / write data transfer circuit for transmitting data between a pair and a write data line pair.

[0002]

2. Description of the Related Art In recent years, a semiconductor memory device which selects two digit pairs at the same time in the same selected word to read and write 2-bit data has been proposed in order to increase the integration of the semiconductor memory device and stabilize its operation. Have been. FIG. 5 is a diagram showing an example of the configuration, in which a sub-word driver SWD is connected to a main word line W connected to the X decoder XDEC, and a large number of memory cells CELL are arranged in a matrix with the sub-word driver SWD interposed therebetween. Is done. Further, in the above sub-word drivers SWD by the same word of the sub-word lines W1, W2 are selected, two digit lines pairs D of the memory cell at a position sandwiching the sub-word drivers SWD, D ^- is selected, the digit line The pair is connected to the read / write data transfer circuits RWDT1 and RWDT1 via the sense amplifier SA.
In WDT2, two pairs (four) of read data line pairs RB1 and RB1 are arranged in parallel with the word lines.
B, RB2, RB2B, write data line pair WB1, W
Data transmission is performed between B1B, WB2, and WB2B.

In such a conventional semiconductor memory device, each of the read / write data transfer circuits RWDT1, RWDT1, RWD1,
The WDT 2 has a configuration in which the read data transfer RT and the write data transfer WT are arranged in an integrated manner in the same direction, and therefore, the WDT 2 is passed through each of the read data transfer RDT and the write data transfer WDT. Read data line pair R
B1, RB1B, RB2, RB2B and write data line pairs WB1, WB1B, WB, and WB2B are arranged in a united state. Therefore, in particular, two read data line pairs RB1, RB1B, RB2, RB2
The arrangement of B is fixed, which causes noise due to mutual line capacitance, which causes a read error. For this reason, as shown in FIG.
Write data transfer circuits RWDT1, RWDT2
By using the space secured between the two, the two read data line pairs RB1, RB1B, RB2, and RB2B are subjected to twist processing, and the adjacently arranged read data lines are replaced with each other, so that the above-described line capacitance is used. Techniques have been proposed that prevent such problems. For example, as a technique for performing such a twist processing, there is a technique described in Japanese Patent Application Laid-Open No. 1-76494.

[0004]

However, with the recent demand for higher integration of semiconductor memory devices and the development of process technology, if the sub-word driver can be reduced in size, the above-mentioned space is also reduced. In addition, it becomes difficult to secure a space for twisting two pairs of read data lines. For this reason, it is difficult to solve the above-described problem of the line capacitance due to the twisting process. Conversely, if this twisting process is prioritized, a wasteful space is generated around the sub-word driver, and the semiconductor memory device becomes expensive. It becomes difficult to realize integration and reduction of the configuration size.

An object of the present invention is to provide a semiconductor memory device which solves the problem of the line capacitance in a read data line, and realizes high integration and a reduced configuration size.

[0006]

According to the semiconductor memory device of the present invention, a sub-word driver for selecting a word line is arranged between a first memory cell region and a second memory cell region. First and second bit lines are respectively arranged in the second memory cell area, and a plurality of read data lines and a plurality of write data lines are formed so as to intersect with the first and second bit lines. In the semiconductor memory device disposed over the first and second memory cell regions, the plurality of read data lines include a first read data line and a second read data line, and the first and second read data lines are provided. Data lines are separately arranged on both sides of the plurality of write data lines, and the first and second bit lines and the first and second bit lines are respectively provided in the first memory cell region and the second memory cell region. Two And first and second read / write data transfer connections for connecting between the read data line and the write data line, respectively, wherein the first read data line is connected to a first read / write terminal of the first memory cell area. A read data transfer of a write data transfer connection is connected to the first bit line, and the second read data line is a read data transfer of a second read / write data transfer connection of the second memory cell area. It is characterized by being connected to the second bit line.

Further, in the present invention, each of the read / write data transfer circuits in the memory cell areas on both sides includes a read data transfer and a write data transfer constituting each read / write data transfer circuit. It is characterized by being arranged in the opposite direction along the parallel direction of the data lines. Here, each of the read / write data transfer circuits on both sides has a configuration in which the read data transfer and the write data transfer are arranged in a parallel state along the parallel direction of the read data line and the write data line. .

In a read operation, the read data line pairs are arranged on both sides of the deactivated write data line pair, so that there is no line capacitance and no interference between the read data line pairs, and the read data line pairs are twisted. This eliminates the need for processing, and enables high integration and miniaturization of the semiconductor memory device. During a write operation, the read data line pair is in an inactive state, and the write data line pair is sandwiched on both sides by the read data line pair, so that interference from other operation wiring is shielded. You.

[0009]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a memory cell array configuration used in the semiconductor memory device of the present invention.
A memory cell array group CELL including a large number of memory cells arranged in a matrix, a main X decoder MainXDEC for selecting and driving a word line, and a sub-word driver Sub connected to the main C decoder
XDEC, a digit precharge circuit PDL for precharging the digit line, and digit line data
A transfer gate TG for transmitting to sense amplifier circuits SEN and SEP constituted by channel and P channel transistors, a Y decoder YDEC, and data amplified by the sense amplifier circuit selected by the Y decoder are transmitted to a read data line. Read data transfer RS
W and a write data transfer W-SW for transmitting the data on the write data line to the digit line selected by the Y decoder. It should be noted that IO1 to IO4 schematically show data groups input and output by the read data lines and the write data lines.

FIG. 2 is a diagram showing a detailed circuit of FIG.
In particular, FIG. 3 is a diagram showing a layout configuration of a read / write data transfer circuit including the read data transfer and the write data transfer, and an arrangement relationship between a read data line pair and a write data line pair. As in the conventional configuration shown in FIG. 5, the memory cell CELL, the sense amplifier circuit SA, and the read / write data transfer circuits RWDT1 and RWDT2 include a sub-word driver S
The read / write data transfer circuits RWDT1 and RWD are arranged on both sides of the WD.
In T2, the digit line pair D connected to each sense amplifier SA, D ^- respectively, is crossing the 2
A pair (four) of read data line pairs RB1, RB1B, R
B2, RB2B, write data line pair WB1, WB1
Data is transmitted between B, WB2, and WB2B.

Here, the write data line pair WB1,
WB1B, WB2, WB2B are arranged in a united state as before, but the read data line pairs RB1, RB1B, RB2, RB2B are each paired with the write data line pair WB1, WB1B, WB
2, WB2B are arranged at positions separated on both sides thereof so as to sandwich the WB2B in the juxtaposition direction. Further, the sub-word sandwiching the driver SWD read-write data transfer circuit RWDT1 In accordance with this, RWDT2 is read data transfer RDT and the write data transfer the WDT digit line D, respectively, D ^- distribution in opposite directions along the extension direction of the Has been established. That is, in the case of this embodiment, the read / write data transfer circuit RWDT1 on the upper side of the drawing of the sub-word driver SWD is shown.
In the figure, a write data transfer WDT is arranged on the left side in the figure and a read data transfer RDT is arranged on the right side in the figure. On the other hand, the read / write data transfer circuit RWDT2 on the lower side of the sub-word driver SWD is provided with a write data transfer WDT on the right side of the figure.
The read data transfer RDT is arranged on the left side in the figure.

Therefore, in the read / write data transfer circuit RWDT1 on the upper side in the figure, the read data line pair R extended on the read data transfer RDT is provided.
B1, RB1B digit line pair D relative to, D ^- connection is made with respect to, one of the write data line pair to be extended on the write data transfer WDT, here WB1, but connected to WB1B is performed The read data line pair RB2, RB2B extending to the write data transfer WDT side is configured to simply pass over the write data transfer WDT and a position adjacent thereto. Similarly, in the lower read / write data transfer circuit RWDT2 in the figure, a read data line pair RB2, RB extended on the read data transfer RDT is provided.
Digit line pair D relative 2B, D ^- connection is made with respect to, the other of the write data line pair to be extended on the write data transfer WDT, i.e. WB2,
A connection is made to WB2B, but a read data line pair RB extended to the write data transfer WDT side.
1 and RB1B are simply passed through the write data transfer WDT and adjacent positions thereof. In order to realize this configuration, the read data line pairs RB1, RB1B, RB2, RB2B and the write data line pairs WB1, WB1B, WB2, WB2B have a wiring path in a region where the sub-word driver SWD is provided. It is slightly bent.

FIG. 3 is a diagram schematically showing the configuration of the read / write data transfer circuit RWDT.
Read / write data transfer circuit R on the lower side of FIG.
A part of WDT2 is shown. This read-write data transfer circuit, the read data transfer RDT to the left side being disposed write data transfer WDT to the right side, and one Didetto line pair D, D ^- and, crossing the unshown One element including a gate polysilicon G, a diffusion layer SD, and a contact CT for connection with the data line of FIG. In the read / write data transfer circuit RWDT2 having this configuration, when the left and right sides of the read data transfer RT and the write data transfer WDT are exchanged to constitute the upper read / write data transfer circuit RWDT1 in FIG. As shown in FIG. 4A, each data transfer RDT, WDT is cross-translated in parallel, or as shown in FIG. 4B, a mirror in which the entire read / write data transfer circuit RWDT2 is rotated by 180 degrees in a plane. A configuration can be employed.

The read operation in the above configuration will be described. The memory cell C is connected to the word line W2 selected by the main X decoder XDEC and the sub-word driver SWD.
The memory cell data is transmitted from the ELL to the sense amplifier circuit SA. The memory cell data amplified by the sense amplifier circuit SA is read data transfer RD selected by two Y decoders (not shown) activated simultaneously.
T only the digit line pair D, D ^- read data line pair RB1 from, RB1B, RB2, transmits the memory cell data in RB2B. Two read data line pairs RB1,
RB1B and read data line pairs RB2, RB2B are two write data line pairs WB1, WB1 in an inactive state.
Since they are arranged on both sides of B, WB2 and WB2B, there is no line capacitance and no interference between the read data line pairs. Incidentally, in the conventional structure shown in FIG. 2, the line capacitance between adjacent read data line pairs is about 0.3 PF. Therefore, it is not necessary to perform the twisting process on the read word line pair in the arrangement region of the sub-word driver SWD as in the related art, and the semiconductor memory device can be highly integrated and reduced in size.

At the time of write operation, the read / write data transfer circuit RWDT is performed in reverse to the read operation.
1 and RWDT2, respectively.
B1, WB1B, WB2, WB2B digit line pair from D, D ^- to transmit the data to. At this time, the read data line pairs RB1, RB1B, RB2, RB2B are in the inactive state, and the write data line pairs WB1, WB1
B, WB2, WB2B are read data line pairs RB1, R
Since both sides are sandwiched by B1B, RB2, and RB2B, an effect of shielding interference from other operation wiring can be obtained.

When a read / write data transfer circuit in which the read data transfer and the write data transfer are arranged opposite to each other as described above is constructed, as described above, the read data transfer RD
A configuration in which the T and the write data transfer WDT are translated in parallel and a configuration in which the mirror is rotated can be employed. When these two are compared, as shown in FIGS. 4C and 4D, the gate poly G of the element is misaligned. Is caused, the dimensions between the gate poly G and the contact CT are different from each other in the mirror configuration as compared with the above-described parallel movement configuration, and the digit line capacitance is unbalanced. In order to prevent imbalance, replacement by parallel movement is more effective.

[0017]

As described above, according to the present invention, a plurality of read data lines and write data lines arranged in
The read data line is extended on both sides of the write data line in a separated state, and each data line performs data transmission in each read / write data transfer circuit of the memory cell area separated by the sub-word driver. In the read operation, the read data line pairs are separated by the deactivated write data line pairs during the read operation, and there is no line capacitance and no interference between the read data line pairs. It is not necessary to perform the twisting process, and the semiconductor memory device can be highly integrated and reduced in size. During a write operation, the read data line pair is in an inactive state, and the write data line pair is sandwiched on both sides by the read data line pair, so that interference from other operation wiring is shielded. You. As a result, the sub-word driver becomes smaller as the process technology advances, and the above-described effects can be expected even if the twist processing of the data lines cannot be performed in the sub-word driver region. Reduction can be realized.

[Brief description of the drawings]

FIG. 1 is a detailed layout diagram of a semiconductor memory device to which the present invention is applied.

FIG. 2 is a circuit configuration diagram of a main part of the semiconductor memory device of the present invention.

FIG. 3 is a schematic configuration diagram of a read / write data transfer circuit.

FIG. 4 is a diagram illustrating a configuration of a read / write data transfer circuit.

FIG. 5 is a circuit diagram of a part of a conventional semiconductor memory device.

[Explanation of symbols]

CELL memory cell SWD sub-word driver SA sense amplifier D, D ^- digit line pair RB1, RB1B, RB2, RB2B read data line pair WB1, WB1B, WB2, WB2B write data line pair RWDT1, RWDT2 read / write data transfer circuit RDT read data Transfer WDT Write data transfer W, W1, W2 Word line XDEC X decoder

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuhiko Matsuki 1-403-3, Kosugi-cho, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Within NEC Ic Microcomputer System Co., Ltd. (56) References JP-A-4-283495 (JP, A) JP-A-7-334985 (JP, A)

Claims (1)

(57) [Claims] 1. A sub-word driver for selecting a word line is disposed between a first memory cell region and a second memory cell region, and a first and a second memory cell region are provided in the first and second memory cell regions, respectively. A second bit line is arranged, and a plurality of read data lines and a plurality of write data lines are arranged across the first and second memory cell areas in a form intersecting with the first and second bit lines. In the semiconductor memory device, the plurality of read data lines include a first read data line and a second read data line, and the first and second read data lines are connected to both sides of the plurality of write data lines. The first and second bit lines and the first and second read data lines and the write data line are respectively arranged in the first memory cell region and the second memory cell region. And first and second read / write data transfer connection sections for connecting the first and second read / write data transfer sections, respectively, wherein the first read data line is a read data transfer of a first read / write data transfer connection section of the first memory cell area. The second read data line is connected to the first bit line, and the second read data line is connected to the second bit line at a read data transfer of a second read / write data transfer connection part of the second memory cell area. A semiconductor memory device characterized by the above-mentioned.